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Searched refs:CLK_TOP_SYSPLL4_D2 (Results 1 – 20 of 20) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-topckgen.h23 #define CLK_TOP_SYSPLL4_D2 16 macro
H A Dmt7629-clk.h46 #define CLK_TOP_SYSPLL4_D2 36 macro
H A Dmt7622-clk.h39 #define CLK_TOP_SYSPLL4_D2 27 macro
H A Dmt6797-clk.h60 #define CLK_TOP_SYSPLL4_D2 50 macro
H A Dmediatek,mt6795-clk.h63 #define CLK_TOP_SYSPLL4_D2 52 macro
H A Dmt8173-clk.h65 #define CLK_TOP_SYSPLL4_D2 55 macro
H A Dmt6765-clk.h49 #define CLK_TOP_SYSPLL4_D2 14 macro
H A Dmediatek,mt8365-clk.h29 #define CLK_TOP_SYSPLL4_D2 19 macro
H A Dmt2712-clk.h48 #define CLK_TOP_SYSPLL4_D2 17 macro
H A Dmt2701-clk.h25 #define CLK_TOP_SYSPLL4_D2 15 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-topckgen.c83 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 2),
H A Dclk-mt6795-topckgen.c417 FACTOR_FLAGS(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2, 0),
H A Dclk-mt8173-topckgen.c496 FACTOR_FLAGS(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2, 0),
H A Dclk-mt7622.c281 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
H A Dclk-mt7629.c389 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
H A Dclk-mt6797.c40 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
H A Dclk-mt2712.c56 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
H A Dclk-mt8365.c48 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
H A Dclk-mt6765.c97 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
H A Dclk-mt2701.c71 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),