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Searched refs:CLK_TOP_SYSPLL1_D16 (Results 1 – 18 of 18) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-topckgen.h18 #define CLK_TOP_SYSPLL1_D16 11 macro
H A Dmt7629-clk.h38 #define CLK_TOP_SYSPLL1_D16 28 macro
H A Dmt6797-clk.h50 #define CLK_TOP_SYSPLL1_D16 40 macro
H A Dmediatek,mt6795-clk.h55 #define CLK_TOP_SYSPLL1_D16 44 macro
H A Dmt8173-clk.h57 #define CLK_TOP_SYSPLL1_D16 47 macro
H A Dmt6765-clk.h40 #define CLK_TOP_SYSPLL1_D16 5 macro
H A Dmediatek,mt8365-clk.h20 #define CLK_TOP_SYSPLL1_D16 10 macro
H A Dmt2712-clk.h40 #define CLK_TOP_SYSPLL1_D16 9 macro
H A Dmt2701-clk.h19 #define CLK_TOP_SYSPLL1_D16 9 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-topckgen.c78 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 16),
H A Dclk-mt6795-topckgen.c409 FACTOR_FLAGS(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16, 0),
H A Dclk-mt8173-topckgen.c488 FACTOR_FLAGS(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16, 0),
H A Dclk-mt7629.c381 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32),
H A Dclk-mt6797.c30 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
H A Dclk-mt2712.c48 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
H A Dclk-mt8365.c39 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32),
H A Dclk-mt6765.c88 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
H A Dclk-mt2701.c65 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),