Searched refs:CLK_TOP_SPI0_BCLK (Results 1 – 2 of 2) sorted by relevance
36 #define CLK_TOP_SPI0_BCLK 23 macro
718 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI0_BCLK, "spi0_b", spi_b_parents,