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Searched refs:CLK_TOP_MUX_MSDC50_0 (Results 1 – 5 of 5) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmt6797-clk.h27 #define CLK_TOP_MUX_MSDC50_0 17 macro
H A Dmt8183-clk.h44 #define CLK_TOP_MUX_MSDC50_0 8 macro
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8183-evb.dts116 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
/linux/drivers/clk/mediatek/
H A Dclk-mt6797.c346 MUX_GATE(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", msdc50_0_parents,
H A Dclk-mt8183.c498 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel",