| /linux/include/dt-bindings/clock/ |
| H A D | mediatek,mt6735-topckgen.h | 55 #define CLK_TOP_MFG_SEL 47 macro
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| H A D | mt8135-clk.h | 75 #define CLK_TOP_MFG_SEL 64 macro
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| H A D | mediatek,mt6795-clk.h | 97 #define CLK_TOP_MFG_SEL 86 macro
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| H A D | mt8173-clk.h | 99 #define CLK_TOP_MFG_SEL 89 macro
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| H A D | mt6765-clk.h | 135 #define CLK_TOP_MFG_SEL 100 macro
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| H A D | mediatek,mt8365-clk.h | 75 #define CLK_TOP_MFG_SEL 65 macro
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| H A D | mt2712-clk.h | 136 #define CLK_TOP_MFG_SEL 105 macro
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| H A D | mt2701-clk.h | 92 #define CLK_TOP_MFG_SEL 81 macro
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt6735-topckgen.c | 341 …MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CF…
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| H A D | clk-mt6795-topckgen.c | 463 TOP_MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x50, 24, 4, 31, 0),
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| H A D | clk-mt8173-topckgen.c | 542 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 24, 4, 31),
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| H A D | clk-mt8135.c | 357 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23),
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| H A D | clk-mt2712.c | 653 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050, 24, 4, 31),
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| H A D | clk-mt8365.c | 420 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050,
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| H A D | clk-mt6765.c | 383 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, CLK_CFG_1,
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| H A D | clk-mt2701.c | 500 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents,
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| /linux/arch/arm/boot/dts/mediatek/ |
| H A D | mt2701.dtsi | 157 <&topckgen CLK_TOP_MFG_SEL>,
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt2712e.dtsi | 286 <&topckgen CLK_TOP_MFG_SEL>,
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