Searched refs:CLK_TOP_APLL_I2SOUT6 (Results 1 – 2 of 2) sorted by relevance
90 #define CLK_TOP_APLL_I2SOUT6 77 macro
944 MUX_DIV_GATE(CLK_TOP_APLL_I2SOUT6, "apll_i2sout6_m", apll_m_parents,