Searched refs:CLK_TOP_APLL_I2SOUT0 (Results 1 – 2 of 2) sorted by relevance
85 #define CLK_TOP_APLL_I2SOUT0 72 macro
933 MUX_DIV_GATE(CLK_TOP_APLL_I2SOUT0, "apll_i2sout0_m", apll_m_parents,