Searched refs:CLK_TOP_APLL_I2SIN6 (Results 1 – 2 of 2) sorted by relevance
84 #define CLK_TOP_APLL_I2SIN6 71 macro
931 MUX_DIV_GATE(CLK_TOP_APLL_I2SIN6, "apll_i2sin6_m", apll_m_parents,