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Searched refs:CLK_PERI_PWM2 (Results 1 – 15 of 15) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-pericfg.h9 #define CLK_PERI_PWM2 3 macro
H A Dmt8135-clk.h167 #define CLK_PERI_PWM2 29 macro
H A Dmediatek,mt6795-clk.h178 #define CLK_PERI_PWM2 3 macro
H A Dmt8173-clk.h197 #define CLK_PERI_PWM2 4 macro
H A Dmt2712-clk.h243 #define CLK_PERI_PWM2 4 macro
H A Dmt2701-clk.h225 #define CLK_PERI_PWM2 4 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt8173-pericfg.c54 GATE_PERI0(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3),
H A Dclk-mt6795-pericfg.c43 GATE_PERI(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3),
H A Dclk-mt6735-pericfg.c33 GATE_MTK(CLK_PERI_PWM2, "pwm2", "axi_sel", &peri_cg_regs, 3, &mtk_clk_gate_ops_setclr),
H A Dclk-mt8135.c478 GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
H A Dclk-mt2712.c889 GATE_PERI0(CLK_PERI_PWM2, "per_pwm2", "pwm_sel", 4),
H A Dclk-mt2701.c852 GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axisel_d4", 3),
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi486 <&pericfg CLK_PERI_PWM2>,
H A Dmt6795.dtsi607 <&pericfg CLK_PERI_PWM2>,
/linux/arch/arm/boot/dts/mediatek/
H A Dmt7623.dtsi426 <&pericfg CLK_PERI_PWM2>,