Searched refs:CLK_MUX_READ_ONLY (Results 1 – 14 of 14) sorted by relevance
| /linux/drivers/clk/zynqmp/ |
| H A D | clk-mux-zynqmp.c | 111 ccf_flag |= CLK_MUX_READ_ONLY; in zynqmp_clk_map_mux_ccf_flags()
146 if (nodes->type_flag & CLK_MUX_READ_ONLY) in zynqmp_clk_register_mux()
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| /linux/drivers/clk/sophgo/ |
| H A D | clk-sg2044.c | 836 0x020, 7, sg2044_mux_table, CLK_MUX_READ_ONLY);
846 0x020, 8, sg2044_mux_table, CLK_MUX_READ_ONLY);
856 0x020, 9, sg2044_mux_table, CLK_MUX_READ_ONLY);
866 0x020, 10, sg2044_mux_table, CLK_MUX_READ_ONLY);
876 0x020, 11, sg2044_mux_table, CLK_MUX_READ_ONLY);
886 0x020, 12, sg2044_mux_table, CLK_MUX_READ_ONLY);
896 0x020, 13, sg2044_mux_table, CLK_MUX_READ_ONLY);
906 0x020, 14, sg2044_mux_table, CLK_MUX_READ_ONLY);
1719 if (!(mux->mux.flags & CLK_MUX_READ_ONLY)) { in sg2044_clk_init_ctrl()
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| /linux/drivers/clk/renesas/ |
| H A D | r9a09g077-cpg.c | 259 sel_clk_pll0, ARRAY_SIZE(sel_clk_pll0), CLK_MUX_READ_ONLY),
261 sel_clk_pll1, ARRAY_SIZE(sel_clk_pll1), CLK_MUX_READ_ONLY),
263 sel_clk_pll2, ARRAY_SIZE(sel_clk_pll2), CLK_MUX_READ_ONLY),
265 sel_clk_pll3, ARRAY_SIZE(sel_clk_pll3), CLK_MUX_READ_ONLY),
267 sel_clk_pll4, ARRAY_SIZE(sel_clk_pll4), CLK_MUX_READ_ONLY),
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| H A D | rzg2l-cpg.h | 190 .mux_flags = CLK_MUX_READ_ONLY)
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-half-divider.c | 188 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops in rockchip_clk_register_halfdiv()
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| H A D | clk-cpu.c | 491 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops in rockchip_clk_register_cpuclk_multi_pll()
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| H A D | clk.c | 68 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops in rockchip_clk_register_branch()
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| H A D | clk-rk3588.c | 1324 RK3588_CLKSEL_CON(165), 6, 2, MFLAGS | CLK_MUX_READ_ONLY,
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| /linux/drivers/clk/ |
| H A D | clk-mux.c | 177 if (clk_mux_flags & CLK_MUX_READ_ONLY) in __clk_hw_register_mux()
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| /linux/drivers/pinctrl/tegra/ |
| H A D | pinctrl-tegra20.c | 2242 pmx->regs[1] + 0x8, 2, 2, CLK_MUX_READ_ONLY, NULL); in tegra20_pinctrl_register_clock_muxes()
2245 pmx->regs[1] + 0x8, 4, 2, CLK_MUX_READ_ONLY, NULL); in tegra20_pinctrl_register_clock_muxes()
2248 pmx->regs[1] + 0x8, 6, 2, CLK_MUX_READ_ONLY, NULL); in tegra20_pinctrl_register_clock_muxes()
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| /linux/drivers/clk/nxp/ |
| H A D | clk-lpc18xx-cgu.c | 220 LPC1XX_CGU_BASE_CLK(SAFE, base_irc_src_ids, CLK_MUX_READ_ONLY),
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| /linux/drivers/clk/imx/ |
| H A D | clk.h | 209 …x_clk_hw_mux(name, reg, shift, width, parents, num_parents, CLK_SET_RATE_PARENT, CLK_MUX_READ_ONLY)
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| /linux/include/linux/ |
| H A D | clk-provider.h | 1066 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ macro
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| /linux/drivers/clk/stm32/ |
| H A D | clk-stm32mp1.c | 924 element->mux.flags = CLK_MUX_READ_ONLY; in clk_register_pll()
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