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Searched refs:CLK_MM_MDP_WROT1 (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt6795-mm.c46 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
H A Dclk-mt6797-mm.c46 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
H A Dclk-mt6779-mm.c54 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 18),
H A Dclk-mt8173-mm.c49 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
H A Dclk-mt2712-mm.c57 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
/linux/include/dt-bindings/clock/
H A Dmt6797-clk.h228 #define CLK_MM_MDP_WROT1 14 macro
H A Dmediatek,mt6795-clk.h232 #define CLK_MM_MDP_WROT1 13 macro
H A Dmt8173-clk.h260 #define CLK_MM_MDP_WROT1 13 macro
H A Dmt6779-clk.h387 #define CLK_MM_MDP_WROT1 47 macro
H A Dmt2712-clk.h314 #define CLK_MM_MDP_WROT1 13 macro
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi1078 clocks = <&mmsys CLK_MM_MDP_WROT1>;