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Searched refs:CLK_MM_DISP_WDMA1 (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt6795-mm.c55 GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
H A Dclk-mt6797-mm.c55 GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
H A Dclk-mt8173-mm.c58 GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
H A Dclk-mt2712-mm.c66 GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
/linux/include/dt-bindings/clock/
H A Dmt6797-clk.h237 #define CLK_MM_DISP_WDMA1 23 macro
H A Dmediatek,mt6795-clk.h241 #define CLK_MM_DISP_WDMA1 22 macro
H A Dmt8173-clk.h269 #define CLK_MM_DISP_WDMA1 22 macro
H A Dmt2712-clk.h323 #define CLK_MM_DISP_WDMA1 22 macro
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6795.dtsi797 clocks = <&mmsys CLK_MM_DISP_WDMA1>;
H A Dmt8173.dtsi1139 clocks = <&mmsys CLK_MM_DISP_WDMA1>;