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Searched refs:CLK_MM_DISP_OVL0_2L (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt6765-mm.c34 GATE_MM(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_ck", 8),
H A Dclk-mt8186-mm.c37 GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "top_disp", 4),
H A Dclk-mt6797-mm.c50 GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 17),
H A Dclk-mt8183-mm.c57 GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 21),
H A Dclk-mt8192-mm.c47 GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "disp_sel", 4),
H A Dclk-mt6779-mm.c57 GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 21),
/linux/include/dt-bindings/clock/
H A Dmt6797-clk.h232 #define CLK_MM_DISP_OVL0_2L 18 macro
H A Dmt6765-clk.h259 #define CLK_MM_DISP_OVL0_2L 8 macro
H A Dmt6779-clk.h361 #define CLK_MM_DISP_OVL0_2L 21 macro
H A Dmt8183-clk.h329 #define CLK_MM_DISP_OVL0_2L 20 macro
H A Dmt8186-clk.h305 #define CLK_MM_DISP_OVL0_2L 4 macro
H A Dmt8192-clk.h428 #define CLK_MM_DISP_OVL0_2L 4 macro
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8183.dtsi1742 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
H A Dmt8192.dtsi1520 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
H A Dmt8186.dtsi1835 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;