Home
last modified time | relevance | path

Searched refs:CLK_IS_CRITICAL (Results 1 – 25 of 196) sorted by relevance

12345678

/linux/drivers/clk/sophgo/
H A Dclk-sg2042-rpgate.c157 CLK_IS_CRITICAL, R_MP0_CONTROL_REG, 0),
159 CLK_IS_CRITICAL, R_MP1_CONTROL_REG, 0),
161 CLK_IS_CRITICAL, R_MP2_CONTROL_REG, 0),
163 CLK_IS_CRITICAL, R_MP3_CONTROL_REG, 0),
165 CLK_IS_CRITICAL, R_MP4_CONTROL_REG, 0),
167 CLK_IS_CRITICAL, R_MP5_CONTROL_REG, 0),
169 CLK_IS_CRITICAL, R_MP6_CONTROL_REG, 0),
171 CLK_IS_CRITICAL, R_MP7_CONTROL_REG, 0),
173 CLK_IS_CRITICAL, R_MP8_CONTROL_REG, 0),
175 CLK_IS_CRITICAL, R_MP9_CONTROL_REG, 0),
[all …]
H A Dclk-cv1800.c61 CLK_IS_CRITICAL);
68 CLK_IS_CRITICAL);
94 CLK_IS_CRITICAL);
108 CLK_IS_CRITICAL);
122 CLK_IS_CRITICAL);
136 CLK_IS_CRITICAL);
164 CLK_IS_CRITICAL);
208 CLK_IS_CRITICAL);
230 CLK_IS_CRITICAL);
239 CLK_IS_CRITICAL);
[all …]
/linux/drivers/clk/st/
H A Dclk-flexgen.c308 { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
318 { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
319 { .name = "clk-ic-lmi1", .flags = CLK_IS_CRITICAL },
337 { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
339 { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
344 { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
354 { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL },
357 { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL },
382 { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
384 { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
[all …]
/linux/drivers/clk/rockchip/
H A Dclk-rk3576.c393 COMPOSITE_FRAC(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IS_CRITICAL,
404 COMPOSITE(CLK_CPLL_DIV20, "clk_cpll_div20", gpll_cpll_p, CLK_IS_CRITICAL,
407 COMPOSITE(CLK_CPLL_DIV10, "clk_cpll_div10", gpll_cpll_p, CLK_IS_CRITICAL,
410 COMPOSITE(CLK_GPLL_DIV8, "clk_gpll_div8", gpll_cpll_p, CLK_IS_CRITICAL,
413 COMPOSITE(CLK_GPLL_DIV6, "clk_gpll_div6", gpll_cpll_p, CLK_IS_CRITICAL,
416 COMPOSITE(CLK_CPLL_DIV4, "clk_cpll_div4", gpll_cpll_p, CLK_IS_CRITICAL,
419 COMPOSITE(CLK_GPLL_DIV4, "clk_gpll_div4", gpll_cpll_p, CLK_IS_CRITICAL,
422 COMPOSITE(CLK_SPLL_DIV2, "clk_spll_div2", gpll_cpll_spll_bpll_p, CLK_IS_CRITICAL,
425 COMPOSITE(CLK_GPLL_DIV3, "clk_gpll_div3", gpll_cpll_p, CLK_IS_CRITICAL,
428 COMPOSITE(CLK_CPLL_DIV2, "clk_cpll_div2", gpll_cpll_p, CLK_IS_CRITICAL,
[all …]
H A Dclk-rk3588.c34 #define RK3588_LINKED_CLK CLK_IS_CRITICAL
705 COMPOSITE(CLK_50M_SRC, "clk_50m_src", gpll_cpll_p, CLK_IS_CRITICAL,
708 COMPOSITE(CLK_100M_SRC, "clk_100m_src", gpll_cpll_p, CLK_IS_CRITICAL,
711 COMPOSITE(CLK_150M_SRC, "clk_150m_src", gpll_cpll_p, CLK_IS_CRITICAL,
714 COMPOSITE(CLK_200M_SRC, "clk_200m_src", gpll_cpll_p, CLK_IS_CRITICAL,
717 COMPOSITE(CLK_250M_SRC, "clk_250m_src", gpll_cpll_p, CLK_IS_CRITICAL,
720 COMPOSITE(CLK_300M_SRC, "clk_300m_src", gpll_cpll_p, CLK_IS_CRITICAL,
723 COMPOSITE(CLK_350M_SRC, "clk_350m_src", gpll_spll_p, CLK_IS_CRITICAL,
726 COMPOSITE(CLK_400M_SRC, "clk_400m_src", gpll_cpll_p, CLK_IS_CRITICAL,
732 COMPOSITE(CLK_500M_SRC, "clk_500m_src", gpll_cpll_p, CLK_IS_CRITICAL,
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt7988-topckgen.c126 0x024, 0x028, 0, 1, 7, 0x1C0, 8, CLK_IS_CRITICAL),
193 0x090, 0x094, 0x098, 16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL),
198 0x0a0, 0x0a4, 0x0a8, 0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL),
205 0x0a4, 0x0a8, 24, 1, 31, 0x1C4, 12, CLK_IS_CRITICAL),
207 0x0b8, 0, 1, 7, 0x1c4, 13, CLK_IS_CRITICAL),
222 0x0c8, 24, 1, 31, 0x1C4, 20, CLK_IS_CRITICAL),
225 0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x1C4, 21, CLK_IS_CRITICAL),
227 0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL),
298 CLK_IS_CRITICAL),
301 CLK_IS_CRITICAL),
H A Dclk-mt8186-infra_ao.c74 "infra_ao_scp_core", "top_scp", 4, CLK_IS_CRITICAL),
77 "infra_ao_sej", "top_axi", 5, CLK_IS_CRITICAL),
106 "infra_ao_dvfsrc", "top_dvfsrc", 7, CLK_IS_CRITICAL),
118 "infra_ao_dapc", "top_axi", 20, CLK_IS_CRITICAL),
145 GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_SSPM, "infra_ao_sspm", "top_sspm", 15, CLK_IS_CRITICAL),
167 CLK_IS_CRITICAL),
169 CLK_IS_CRITICAL),
177 "infra_ao_sej_f13m", "clk26m", 15, CLK_IS_CRITICAL),
180 "infra_ao_aes_top0_bclk", "top_axi", 16, CLK_IS_CRITICAL),
H A Dclk-mt8188-infra_ao.c87 GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SEJ, "infra_ao_sej", "top_axi", 5, CLK_IS_CRITICAL),
115 "clk26m", 7, CLK_IS_CRITICAL),
127 "top_axi", 20, CLK_IS_CRITICAL),
143 "top_sspm", 15, CLK_IS_CRITICAL),
145 "top_axi", 17, CLK_IS_CRITICAL),
166 "top_axi", 25, CLK_IS_CRITICAL),
171 "top_axi", 0, CLK_IS_CRITICAL),
173 "top_axi", 1, CLK_IS_CRITICAL),
H A Dclk-mt7988-infracfg.c181 CLK_IS_CRITICAL),
184 CLK_IS_CRITICAL),
198 CLK_IS_CRITICAL),
200 CLK_IS_CRITICAL),
204 CLK_IS_CRITICAL),
208 GATE_INFRA2_FLAGS(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", 19, CLK_IS_CRITICAL),
229 CLK_IS_CRITICAL),
231 9, CLK_IS_CRITICAL),
H A Dclk-mt8195-topckgen.c877 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
880 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
883 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
886 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
970 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1040 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1051 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1163 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1166 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1169 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
[all …]
H A Dclk-mt7986-topckgen.c206 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
211 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
215 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
219 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
245 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
264 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
H A Dclk-mt8195-infra_ao.c86 GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SEJ, "infra_ao_sej", "top_axi", 5, CLK_IS_CRITICAL),
124 CLK_IS_CRITICAL),
145 CLK_IS_CRITICAL),
147 CLK_IS_CRITICAL),
172 CLK_IS_CRITICAL),
179 CLK_IS_CRITICAL),
181 CLK_IS_CRITICAL),
H A Dclk-mt7981-topckgen.c320 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
324 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
329 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
333 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
337 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
362 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
H A Dclk-mt8186-topckgen.c507 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
510 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
562 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
573 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
576 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
630 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
H A Dclk-mt8188-topckgen.c960 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
963 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
966 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
969 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1090 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1101 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1178 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1181 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
/linux/drivers/clk/starfive/
H A Dclk-starfive-jh7110-stg.c49 JH71X0_GATE(JH7110_STGCLK_PCIE_SLV_MAIN, "pcie_slv_main", CLK_IS_CRITICAL,
55 JH71X0_GATE(JH7110_STGCLK_GRP0_MAIN, "mtrx_grp0_main", CLK_IS_CRITICAL,
57 JH71X0_GATE(JH7110_STGCLK_GRP0_BUS, "mtrx_grp0_bus", CLK_IS_CRITICAL,
59 JH71X0_GATE(JH7110_STGCLK_GRP0_STG, "mtrx_grp0_stg", CLK_IS_CRITICAL,
61 JH71X0_GATE(JH7110_STGCLK_GRP1_MAIN, "mtrx_grp1_main", CLK_IS_CRITICAL,
63 JH71X0_GATE(JH7110_STGCLK_GRP1_BUS, "mtrx_grp1_bus", CLK_IS_CRITICAL,
65 JH71X0_GATE(JH7110_STGCLK_GRP1_STG, "mtrx_grp1_stg", CLK_IS_CRITICAL,
67 JH71X0_GATE(JH7110_STGCLK_GRP1_HIFI, "mtrx_grp1_hifi", CLK_IS_CRITICAL,
H A Dclk-starfive-jh7110-sys.c56 JH71X0_GATE(JH7110_SYSCLK_AHB0, "ahb0", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
57 JH71X0_GATE(JH7110_SYSCLK_AHB1, "ahb1", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
59 JH71X0_GATE(JH7110_SYSCLK_APB0, "apb0", CLK_IS_CRITICAL, JH7110_SYSCLK_APB_BUS),
77 JH71X0_GATE(JH7110_SYSCLK_CORE, "core", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
78 JH71X0_GATE(JH7110_SYSCLK_CORE1, "core1", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
79 JH71X0_GATE(JH7110_SYSCLK_CORE2, "core2", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
80 JH71X0_GATE(JH7110_SYSCLK_CORE3, "core3", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
81 JH71X0_GATE(JH7110_SYSCLK_CORE4, "core4", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
91 JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_CPU_AXI, "noc_bus_cpu_axi", CLK_IS_CRITICAL,
93 JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI, "noc_bus_axicfg0_axi", CLK_IS_CRITICAL,
[all …]
H A Dclk-starfive-jh7100.c87 JH71X0_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
88 JH71X0_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
89 JH71X0_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
90 JH71X0_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
91 JH71X0_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
92 JH71X0_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),
124 JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT),
125 JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2,
127 JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2,
129 JH71X0_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS),
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx93.c64 { IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL },
65 { IMX93_CLK_A55_MTR_BUS, "a55_mtr_bus_root", 0x0080, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
66 { IMX93_CLK_A55, "a55_alt_root", 0x0100, FAST_SEL, CLK_IS_CRITICAL },
67 { IMX93_CLK_M33, "m33_root", 0x0180, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
68 { IMX93_CLK_BUS_WAKEUP, "bus_wakeup_root", 0x0280, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
69 { IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
70 { IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", 0x0380, FAST_SEL, CLK_IS_CRITICAL },
124 { IMX93_CLK_HSIO, "hsio_root", 0x1e80, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL},
128 { IMX93_CLK_NIC_AXI, "nic_axi_root", 0x2080, FAST_SEL, CLK_IS_CRITICAL, },
171 { IMX93_CLK_CM33_GATE, "cm33", "m33_root", 0x8040, CLK_IS_CRITICAL },
[all …]
H A Dclk-imx6sx.c323 … = imx_clk_hw_divider_flags("perclk", "perclk_sel", base + 0x1c, 0, 6, CLK_IS_CRITICAL); in imx6sx_clocks_init()
371 …6SX_CLK_AIPS_TZ1] = imx_clk_hw_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL); in imx6sx_clocks_init()
372 …6SX_CLK_AIPS_TZ2] = imx_clk_hw_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL); in imx6sx_clocks_init()
385 …SX_CLK_AIPS_TZ3] = imx_clk_hw_gate2_flags("aips_tz3", "ahb", base + 0x68, 30, CLK_IS_CRITICAL); in imx6sx_clocks_init()
398 …X6SX_CLK_WAKEUP] = imx_clk_hw_gate2_flags("wakeup", "ipg", base + 0x6c, 18, CLK_IS_CRITICAL); in imx6sx_clocks_init()
412 …X6SX_CLK_IPMUX1] = imx_clk_hw_gate2_flags("ipmux1", "ahb", base + 0x70, 16, CLK_IS_CRITICAL); in imx6sx_clocks_init()
413 …X6SX_CLK_IPMUX2] = imx_clk_hw_gate2_flags("ipmux2", "ahb", base + 0x70, 18, CLK_IS_CRITICAL); in imx6sx_clocks_init()
414 …X6SX_CLK_IPMUX3] = imx_clk_hw_gate2_flags("ipmux3", "ahb", base + 0x70, 20, CLK_IS_CRITICAL); in imx6sx_clocks_init()
415 …LK_TZASC1] = imx_clk_hw_gate2_flags("tzasc1", "mmdc_podf", base + 0x70, 22, CLK_IS_CRITICAL); in imx6sx_clocks_init()
429 …C_P0_FAST] = imx_clk_hw_gate2_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL); in imx6sx_clocks_init()
[all …]
H A Dclk-imx5.c147 clk[IMX5_CLK_AHB_MAX] = imx_clk_gate2_flags("ahb_max", "ahb", MXC_CCM_CCGR0, 28, CLK_IS_CRITICAL); in mx5_clocks_common_init()
148 …k[IMX5_CLK_AIPS_TZ1] = imx_clk_gate2_flags("aips_tz1", "ahb", MXC_CCM_CCGR0, 24, CLK_IS_CRITICAL); in mx5_clocks_common_init()
149 …k[IMX5_CLK_AIPS_TZ2] = imx_clk_gate2_flags("aips_tz2", "ahb", MXC_CCM_CCGR0, 26, CLK_IS_CRITICAL); in mx5_clocks_common_init()
150 clk[IMX5_CLK_TMAX1] = imx_clk_gate2_flags("tmax1", "ahb", MXC_CCM_CCGR1, 0, CLK_IS_CRITICAL); in mx5_clocks_common_init()
151 clk[IMX5_CLK_TMAX2] = imx_clk_gate2_flags("tmax2", "ahb", MXC_CCM_CCGR1, 2, CLK_IS_CRITICAL); in mx5_clocks_common_init()
152 clk[IMX5_CLK_TMAX3] = imx_clk_gate2_flags("tmax3", "ahb", MXC_CCM_CCGR1, 4, CLK_IS_CRITICAL); in mx5_clocks_common_init()
153 clk[IMX5_CLK_SPBA] = imx_clk_gate2_flags("spba", "ipg", MXC_CCM_CCGR5, 0, CLK_IS_CRITICAL); in mx5_clocks_common_init()
218 …EMI_FAST_GATE] = imx_clk_gate2_flags("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14, CLK_IS_CRITICAL); in mx5_clocks_common_init()
219 …_GATE] = imx_clk_gate2_flags("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16, CLK_IS_CRITICAL); in mx5_clocks_common_init()
233 …IMX5_CLK_GPC_DVFS] = imx_clk_gate2_flags("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24, CLK_IS_CRITICAL); in mx5_clocks_common_init()
[all …]
/linux/drivers/clk/samsung/
H A Dclk-exynos8895.c1409 21, CLK_IS_CRITICAL, 0),
1413 21, CLK_IS_CRITICAL, 0),
1417 21, CLK_IS_CRITICAL, 0),
1421 21, CLK_IS_CRITICAL, 0),
1425 21, CLK_IS_CRITICAL, 0),
1434 21, CLK_IS_CRITICAL, 0),
1438 21, CLK_IS_CRITICAL, 0),
1679 21, CLK_IS_CRITICAL, 0),
1687 21, CLK_IS_CRITICAL, 0),
1691 21, CLK_IS_CRITICAL, 0),
[all …]
/linux/drivers/clk/bcm/
H A Dclk-bcm63xx-gate.c129 .flags = CLK_IS_CRITICAL,
142 .flags = CLK_IS_CRITICAL,
173 .flags = CLK_IS_CRITICAL,
177 .flags = CLK_IS_CRITICAL,
184 .flags = CLK_IS_CRITICAL,
221 .flags = CLK_IS_CRITICAL,
300 .flags = CLK_IS_CRITICAL,
424 .flags = CLK_IS_CRITICAL,
/linux/drivers/clk/microchip/
H A Dclk-mpfs.c309 CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL),
314 CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL),
326 CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, CLK_IS_CRITICAL),
331 CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL),
332 CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AXI), 24, CLK_IS_CRITICAL),
333 CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AXI), 25, CLK_IS_CRITICAL),
334 CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AXI), 26, CLK_IS_CRITICAL),
335 CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AXI), 27, CLK_IS_CRITICAL),
336 CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AXI), 28, CLK_IS_CRITICAL),
/linux/drivers/clk/baikal-t1/
H A Dclk-ccu-pll.c67 CLK_IS_CRITICAL, CCU_PLL_BASIC),
69 CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0),
71 CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0),
73 CLK_IS_CRITICAL, CCU_PLL_BASIC),
75 CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0)

12345678