Searched refs:CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK (Results 1 – 2 of 2) sorted by relevance
217 #define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK 22 macro
1332 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK,