Searched refs:CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK (Results 1 – 2 of 2) sorted by relevance
215 #define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK 20 macro
1324 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK,