Searched refs:CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK (Results 1 – 2 of 2) sorted by relevance
214 #define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK 19 macro
1320 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK,