Searched refs:CLK_CPU_HAS_DIV1 (Results 1 – 2 of 2) sorted by relevance
12 #define CLK_CPU_HAS_DIV1 BIT(0) macro
221 if (cpuclk->flags & CLK_CPU_HAS_DIV1) { in exynos_cpuclk_pre_rate_change()264 if (cpuclk->flags & CLK_CPU_HAS_DIV1) { in exynos_cpuclk_pre_rate_change()