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Searched refs:CLK_CFG_1_CLR (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt6735-topckgen.c19 #define CLK_CFG_1_CLR 0x58 macro
339 …LK_TOP_PWM_SEL, "pwm_sel", pwm_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 2, 7, 0, 0…
340 …TOP_VDEC_SEL, "vdec_sel", vdec_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 3, 15, 0, …
341 …LK_TOP_MFG_SEL, "mfg_sel", mfg_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 16, 4, 23, 0,…
342 …_CAMTG_SEL, "camtg_sel", camtg_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 24, 3, 31, 0,…
H A Dclk-mt6765.c46 #define CLK_CFG_1_CLR 0x58 macro
384 CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 2, 7,
387 CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 2, 15,
391 CLK_CFG_1_CLR, 16, 3, 23, CLK_CFG_UPDATE, 6),
393 CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR,