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Searched refs:CLK_APMIXED_UNIVPLL (Results 1 – 16 of 16) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-apmixedsys.h8 #define CLK_APMIXED_UNIVPLL 2 macro
H A Dmt8135-clk.h111 #define CLK_APMIXED_UNIVPLL 4 macro
H A Dmt8516-clk.h15 #define CLK_APMIXED_UNIVPLL 2 macro
H A Dmt6797-clk.h109 #define CLK_APMIXED_UNIVPLL 2 macro
H A Dmediatek,mt6795-clk.h143 #define CLK_APMIXED_UNIVPLL 2 macro
H A Dmt8173-clk.h159 #define CLK_APMIXED_UNIVPLL 4 macro
H A Dmediatek,mt8365-clk.h233 #define CLK_APMIXED_UNIVPLL 2 macro
H A Dmt2712-clk.h13 #define CLK_APMIXED_UNIVPLL 1 macro
H A Dmt2701-clk.h177 #define CLK_APMIXED_UNIVPLL 3 macro
H A Dmt8192-clk.h302 #define CLK_APMIXED_UNIVPLL 1 macro
H A Dmediatek,mt8196-clock.h146 #define CLK_APMIXED_UNIVPLL 1 macro
H A Dmt8195-clk.h369 #define CLK_APMIXED_UNIVPLL 10 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt8188-apmixedsys.c74 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0504, 0x0510, 0xff000000,
H A Dclk-mt6735-apmixedsys.c71 …PLL(CLK_APMIXED_UNIVPLL, "univpll", UNIVPLL_CON0, UNIVPLL_PWR_CON0, 0xfc000001, CON0_RST_BAR, UNIV…
H A Dclk-mt8195-apmixedsys.c81 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x01f0, 0x0700, 0xff000000,
H A Dclk-mt2701.c943 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000000,