| /linux/include/dt-bindings/clock/ |
| H A D | mediatek,mt6735-apmixedsys.h | 10 #define CLK_APMIXED_MSDCPLL 4 macro
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| H A D | mt8135-clk.h | 113 #define CLK_APMIXED_MSDCPLL 6 macro
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| H A D | mediatek,mt7988-clk.h | 24 #define CLK_APMIXED_MSDCPLL 11 macro
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| H A D | mt6797-clk.h | 111 #define CLK_APMIXED_MSDCPLL 4 macro
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| H A D | mediatek,mt6795-clk.h | 145 #define CLK_APMIXED_MSDCPLL 4 macro
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| H A D | mt6765-clk.h | 17 #define CLK_APMIXED_MSDCPLL 7 macro
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| H A D | mt8173-clk.h | 161 #define CLK_APMIXED_MSDCPLL 6 macro
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| H A D | mediatek,mt8365-clk.h | 235 #define CLK_APMIXED_MSDCPLL 4 macro
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| H A D | mt6779-clk.h | 172 #define CLK_APMIXED_MSDCPLL 7 macro
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| H A D | mt8183-clk.h | 16 #define CLK_APMIXED_MSDCPLL 5 macro
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| H A D | mt2712-clk.h | 20 #define CLK_APMIXED_MSDCPLL 8 macro
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| H A D | mt8186-clk.h | 269 #define CLK_APMIXED_MSDCPLL 5 macro
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| H A D | mt2701-clk.h | 179 #define CLK_APMIXED_MSDCPLL 5 macro
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| H A D | mt8192-clk.h | 304 #define CLK_APMIXED_MSDCPLL 3 macro
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| H A D | mediatek,mt8196-clock.h | 147 #define CLK_APMIXED_MSDCPLL 2 macro
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| H A D | mt8195-clk.h | 362 #define CLK_APMIXED_MSDCPLL 3 macro
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt8195-apmixedsys.c | 67 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0,
158 FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118),
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| H A D | clk-mt8188-apmixedsys.c | 62 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0514, 0x0520, 0,
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| H A D | clk-mt6735-apmixedsys.c | 73 …PLL(CLK_APMIXED_MSDCPLL, "msdcpll", MSDCPLL_CON0, MSDCPLL_PWR_CON0, 0x00000001, 0, MSDCPLL_CON1, 2…
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| H A D | clk-mt2701.c | 947 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
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| H A D | clk-mt6765.c | 719 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, 0,
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