xref: /linux/drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h (revision 1ac731c529cd4d6adbce134754b51ff7d822b145)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright 2019-2020 NXP
4  */
5 
6 #ifndef __IMX8_ISI_REGS_H__
7 #define __IMX8_ISI_REGS_H__
8 
9 #include <linux/bits.h>
10 
11 /* ISI Registers Define  */
12 /* Channel Control Register */
13 #define CHNL_CTRL						0x0000
14 #define CHNL_CTRL_CHNL_EN					BIT(31)
15 #define CHNL_CTRL_CLK_EN					BIT(30)
16 #define CHNL_CTRL_CHNL_BYPASS					BIT(29)
17 #define CHNL_CTRL_CHAIN_BUF(n)					((n) << 25)
18 #define CHNL_CTRL_CHAIN_BUF_MASK				GENMASK(26, 25)
19 #define CHNL_CTRL_CHAIN_BUF_NO_CHAIN				0
20 #define CHNL_CTRL_CHAIN_BUF_2_CHAIN				1
21 #define CHNL_CTRL_SW_RST					BIT(24)
22 #define CHNL_CTRL_BLANK_PXL(n)					((n) << 16)
23 #define CHNL_CTRL_BLANK_PXL_MASK				GENMASK(23, 16)
24 #define CHNL_CTRL_MIPI_VC_ID(n)					((n) << 6)
25 #define CHNL_CTRL_MIPI_VC_ID_MASK				GENMASK(7, 6)
26 #define CHNL_CTRL_SRC_TYPE(n)					((n) << 4)
27 #define CHNL_CTRL_SRC_TYPE_MASK					BIT(4)
28 #define CHNL_CTRL_SRC_TYPE_DEVICE				0
29 #define CHNL_CTRL_SRC_TYPE_MEMORY				1
30 #define CHNL_CTRL_SRC_INPUT(n)					((n) << 0)
31 #define CHNL_CTRL_SRC_INPUT_MASK				GENMASK(2, 0)
32 
33 /* Channel Image Control Register */
34 #define CHNL_IMG_CTRL						0x0004
35 #define CHNL_IMG_CTRL_FORMAT(n)					((n) << 24)
36 #define CHNL_IMG_CTRL_FORMAT_MASK				GENMASK(29, 24)
37 #define CHNL_IMG_CTRL_FORMAT_RGBA8888				0x00
38 #define CHNL_IMG_CTRL_FORMAT_ABGR8888				0x01
39 #define CHNL_IMG_CTRL_FORMAT_ARGB8888				0x02
40 #define CHNL_IMG_CTRL_FORMAT_RGBX888				0x03
41 #define CHNL_IMG_CTRL_FORMAT_XBGR888				0x04
42 #define CHNL_IMG_CTRL_FORMAT_XRGB888				0x05
43 #define CHNL_IMG_CTRL_FORMAT_RGB888P				0x06
44 #define CHNL_IMG_CTRL_FORMAT_BGR888P				0x07
45 #define CHNL_IMG_CTRL_FORMAT_A2BGR10				0x08
46 #define CHNL_IMG_CTRL_FORMAT_A2RGB10				0x09
47 #define CHNL_IMG_CTRL_FORMAT_RGB565				0x0a
48 #define CHNL_IMG_CTRL_FORMAT_RAW8				0x0b
49 #define CHNL_IMG_CTRL_FORMAT_RAW10				0x0c
50 #define CHNL_IMG_CTRL_FORMAT_RAW10P				0x0d
51 #define CHNL_IMG_CTRL_FORMAT_RAW12				0x0e
52 #define CHNL_IMG_CTRL_FORMAT_RAW16				0x0f
53 #define CHNL_IMG_CTRL_FORMAT_YUV444_1P8P			0x10
54 #define CHNL_IMG_CTRL_FORMAT_YUV444_2P8P			0x11
55 #define CHNL_IMG_CTRL_FORMAT_YUV444_3P8P			0x12
56 #define CHNL_IMG_CTRL_FORMAT_YUV444_1P8				0x13
57 #define CHNL_IMG_CTRL_FORMAT_YUV444_1P10			0x14
58 #define CHNL_IMG_CTRL_FORMAT_YUV444_2P10			0x15
59 #define CHNL_IMG_CTRL_FORMAT_YUV444_3P10			0x16
60 #define CHNL_IMG_CTRL_FORMAT_YUV444_1P10P			0x18
61 #define CHNL_IMG_CTRL_FORMAT_YUV444_2P10P			0x19
62 #define CHNL_IMG_CTRL_FORMAT_YUV444_3P10P			0x1a
63 #define CHNL_IMG_CTRL_FORMAT_YUV444_1P12			0x1c
64 #define CHNL_IMG_CTRL_FORMAT_YUV444_2P12			0x1d
65 #define CHNL_IMG_CTRL_FORMAT_YUV444_3P12			0x1e
66 #define CHNL_IMG_CTRL_FORMAT_YUV422_1P8P			0x20
67 #define CHNL_IMG_CTRL_FORMAT_YUV422_2P8P			0x21
68 #define CHNL_IMG_CTRL_FORMAT_YUV422_3P8P			0x22
69 #define CHNL_IMG_CTRL_FORMAT_YUV422_1P10			0x24
70 #define CHNL_IMG_CTRL_FORMAT_YUV422_2P10			0x25
71 #define CHNL_IMG_CTRL_FORMAT_YUV422_3P10			0x26
72 #define CHNL_IMG_CTRL_FORMAT_YUV422_1P10P			0x28
73 #define CHNL_IMG_CTRL_FORMAT_YUV422_2P10P			0x29
74 #define CHNL_IMG_CTRL_FORMAT_YUV422_3P10P			0x2a
75 #define CHNL_IMG_CTRL_FORMAT_YUV422_1P12			0x2c
76 #define CHNL_IMG_CTRL_FORMAT_YUV422_2P12			0x2d
77 #define CHNL_IMG_CTRL_FORMAT_YUV422_3P12			0x2e
78 #define CHNL_IMG_CTRL_FORMAT_YUV420_2P8P			0x31
79 #define CHNL_IMG_CTRL_FORMAT_YUV420_3P8P			0x32
80 #define CHNL_IMG_CTRL_FORMAT_YUV420_2P10			0x35
81 #define CHNL_IMG_CTRL_FORMAT_YUV420_3P10			0x36
82 #define CHNL_IMG_CTRL_FORMAT_YUV420_2P10P			0x39
83 #define CHNL_IMG_CTRL_FORMAT_YUV420_3P10P			0x3a
84 #define CHNL_IMG_CTRL_FORMAT_YUV420_2P12			0x3d
85 #define CHNL_IMG_CTRL_FORMAT_YUV420_3P12			0x3e
86 #define CHNL_IMG_CTRL_GBL_ALPHA_VAL(n)				((n) << 16)
87 #define CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK			GENMASK(23, 16)
88 #define CHNL_IMG_CTRL_GBL_ALPHA_EN				BIT(15)
89 #define CHNL_IMG_CTRL_DEINT(n)					((n) << 12)
90 #define CHNL_IMG_CTRL_DEINT_MASK				GENMASK(14, 12)
91 #define CHNL_IMG_CTRL_DEINT_WEAVE_ODD_EVEN			2
92 #define CHNL_IMG_CTRL_DEINT_WEAVE_EVEN_ODD			3
93 #define CHNL_IMG_CTRL_DEINT_BLEND_ODD_EVEN			4
94 #define CHNL_IMG_CTRL_DEINT_BLEND_EVEN_ODD			5
95 #define CHNL_IMG_CTRL_DEINT_LDOUBLE_ODD_EVEN			6
96 #define CHNL_IMG_CTRL_DEINT_LDOUBLE_EVEN_ODD			7
97 #define CHNL_IMG_CTRL_DEC_X(n)					((n) << 10)
98 #define CHNL_IMG_CTRL_DEC_X_MASK				GENMASK(11, 10)
99 #define CHNL_IMG_CTRL_DEC_Y(n)					((n) << 8)
100 #define CHNL_IMG_CTRL_DEC_Y_MASK				GENMASK(9, 8)
101 #define CHNL_IMG_CTRL_CROP_EN					BIT(7)
102 #define CHNL_IMG_CTRL_VFLIP_EN					BIT(6)
103 #define CHNL_IMG_CTRL_HFLIP_EN					BIT(5)
104 #define CHNL_IMG_CTRL_YCBCR_MODE				BIT(3)
105 #define CHNL_IMG_CTRL_CSC_MODE(n)				((n) << 1)
106 #define CHNL_IMG_CTRL_CSC_MODE_MASK				GENMASK(2, 1)
107 #define CHNL_IMG_CTRL_CSC_MODE_YUV2RGB				0
108 #define CHNL_IMG_CTRL_CSC_MODE_YCBCR2RGB			1
109 #define CHNL_IMG_CTRL_CSC_MODE_RGB2YUV				2
110 #define CHNL_IMG_CTRL_CSC_MODE_RGB2YCBCR			3
111 #define CHNL_IMG_CTRL_CSC_BYPASS				BIT(0)
112 
113 /* Channel Output Buffer Control Register */
114 #define CHNL_OUT_BUF_CTRL					0x0008
115 #define CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR			BIT(15)
116 #define CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR			BIT(14)
117 #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V(n)		((n) << 6)
118 #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_MASK		GENMASK(7, 6)
119 #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_NO_PANIC		0
120 #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_PANIC_25		1
121 #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_PANIC_50		2
122 #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_PANIC_75		3
123 #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U(n)		((n) << 3)
124 #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_MASK		GENMASK(4, 3)
125 #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_NO_PANIC		0
126 #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_PANIC_25		1
127 #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_PANIC_50		2
128 #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_PANIC_75		3
129 #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y(n)		((n) << 0)
130 #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_MASK		GENMASK(1, 0)
131 #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_NO_PANIC		0
132 #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_PANIC_25		1
133 #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_PANIC_50		2
134 #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_PANIC_75		3
135 
136 /* Channel Image Configuration */
137 #define CHNL_IMG_CFG						0x000c
138 #define CHNL_IMG_CFG_HEIGHT(n)					((n) << 16)
139 #define CHNL_IMG_CFG_HEIGHT_MASK				GENMASK(28, 16)
140 #define CHNL_IMG_CFG_WIDTH(n)					((n) << 0)
141 #define CHNL_IMG_CFG_WIDTH_MASK					GENMASK(12, 0)
142 
143 /* Channel Interrupt Enable Register */
144 #define CHNL_IER						0x0010
145 #define CHNL_IER_MEM_RD_DONE_EN					BIT(31)
146 #define CHNL_IER_LINE_RCVD_EN					BIT(30)
147 #define CHNL_IER_FRM_RCVD_EN					BIT(29)
148 #define CHNL_IER_AXI_WR_ERR_V_EN				BIT(28)
149 #define CHNL_IER_AXI_WR_ERR_U_EN				BIT(27)
150 #define CHNL_IER_AXI_WR_ERR_Y_EN				BIT(26)
151 #define CHNL_IER_AXI_RD_ERR_EN					BIT(25)
152 
153 /* Channel Status Register */
154 #define CHNL_STS						0x0014
155 #define CHNL_STS_MEM_RD_DONE					BIT(31)
156 #define CHNL_STS_LINE_STRD					BIT(30)
157 #define CHNL_STS_FRM_STRD					BIT(29)
158 #define CHNL_STS_AXI_WR_ERR_V					BIT(28)
159 #define CHNL_STS_AXI_WR_ERR_U					BIT(27)
160 #define CHNL_STS_AXI_WR_ERR_Y					BIT(26)
161 #define CHNL_STS_AXI_RD_ERR					BIT(25)
162 #define CHNL_STS_OFLW_PANIC_V_BUF				BIT(24)
163 #define CHNL_STS_EXCS_OFLW_V_BUF				BIT(23)
164 #define CHNL_STS_OFLW_V_BUF					BIT(22)
165 #define CHNL_STS_OFLW_PANIC_U_BUF				BIT(21)
166 #define CHNL_STS_EXCS_OFLW_U_BUF				BIT(20)
167 #define CHNL_STS_OFLW_U_BUF					BIT(19)
168 #define CHNL_STS_OFLW_PANIC_Y_BUF				BIT(18)
169 #define CHNL_STS_EXCS_OFLW_Y_BUF				BIT(17)
170 #define CHNL_STS_OFLW_Y_BUF					BIT(16)
171 #define CHNL_STS_EARLY_VSYNC_ERR				BIT(15)
172 #define CHNL_STS_LATE_VSYNC_ERR					BIT(14)
173 #define CHNL_STS_MEM_RD_OFLOW					BIT(10)
174 #define CHNL_STS_BUF2_ACTIVE					BIT(9)
175 #define CHNL_STS_BUF1_ACTIVE					BIT(8)
176 #define CHNL_STS_OFLW_BYTES(n)					((n) << 0)
177 #define CHNL_STS_OFLW_BYTES_MASK				GENMASK(7, 0)
178 
179 /* Channel Scale Factor Register */
180 #define CHNL_SCALE_FACTOR					0x0018
181 #define CHNL_SCALE_FACTOR_Y_SCALE(n)				((n) << 16)
182 #define CHNL_SCALE_FACTOR_Y_SCALE_MASK				GENMASK(29, 16)
183 #define CHNL_SCALE_FACTOR_X_SCALE(n)				((n) << 0)
184 #define CHNL_SCALE_FACTOR_X_SCALE_MASK				GENMASK(13, 0)
185 
186 /* Channel Scale Offset Register */
187 #define CHNL_SCALE_OFFSET					0x001c
188 #define CHNL_SCALE_OFFSET_Y_SCALE(n)				((n) << 16)
189 #define CHNL_SCALE_OFFSET_Y_SCALE_MASK				GENMASK(27, 16)
190 #define CHNL_SCALE_OFFSET_X_SCALE(n)				((n) << 0)
191 #define CHNL_SCALE_OFFSET_X_SCALE_MASK				GENMASK(11, 0)
192 
193 /* Channel Crop Upper Left Corner Coordinate Register */
194 #define CHNL_CROP_ULC						0x0020
195 #define CHNL_CROP_ULC_X(n)					((n) << 16)
196 #define CHNL_CROP_ULC_X_MASK					GENMASK(27, 16)
197 #define CHNL_CROP_ULC_Y(n)					((n) << 0)
198 #define CHNL_CROP_ULC_Y_MASK					GENMASK(11, 0)
199 
200 /* Channel Crop Lower Right Corner Coordinate Register */
201 #define CHNL_CROP_LRC						0x0024
202 #define CHNL_CROP_LRC_X(n)					((n) << 16)
203 #define CHNL_CROP_LRC_X_MASK					GENMASK(27, 16)
204 #define CHNL_CROP_LRC_Y(n)					((n) << 0)
205 #define CHNL_CROP_LRC_Y_MASK					GENMASK(11, 0)
206 
207 /* Channel Color Space Conversion Coefficient Register 0 */
208 #define CHNL_CSC_COEFF0						0x0028
209 #define CHNL_CSC_COEFF0_A2(n)					((n) << 16)
210 #define CHNL_CSC_COEFF0_A2_MASK					GENMASK(26, 16)
211 #define CHNL_CSC_COEFF0_A1(n)					((n) << 0)
212 #define CHNL_CSC_COEFF0_A1_MASK					GENMASK(10, 0)
213 
214 /* Channel Color Space Conversion Coefficient Register 1 */
215 #define CHNL_CSC_COEFF1						0x002c
216 #define CHNL_CSC_COEFF1_B1(n)					((n) << 16)
217 #define CHNL_CSC_COEFF1_B1_MASK					GENMASK(26, 16)
218 #define CHNL_CSC_COEFF1_A3(n)					((n) << 0)
219 #define CHNL_CSC_COEFF1_A3_MASK					GENMASK(10, 0)
220 
221 /* Channel Color Space Conversion Coefficient Register 2 */
222 #define CHNL_CSC_COEFF2						0x0030
223 #define CHNL_CSC_COEFF2_B3(n)					((n) << 16)
224 #define CHNL_CSC_COEFF2_B3_MASK					GENMASK(26, 16)
225 #define CHNL_CSC_COEFF2_B2(n)					((n) << 0)
226 #define CHNL_CSC_COEFF2_B2_MASK					GENMASK(10, 0)
227 
228 /* Channel Color Space Conversion Coefficient Register 3 */
229 #define CHNL_CSC_COEFF3						0x0034
230 #define CHNL_CSC_COEFF3_C2(n)					((n) << 16)
231 #define CHNL_CSC_COEFF3_C2_MASK					GENMASK(26, 16)
232 #define CHNL_CSC_COEFF3_C1(n)					((n) << 0)
233 #define CHNL_CSC_COEFF3_C1_MASK					GENMASK(10, 0)
234 
235 /* Channel Color Space Conversion Coefficient Register 4 */
236 #define CHNL_CSC_COEFF4						0x0038
237 #define CHNL_CSC_COEFF4_D1(n)					((n) << 16)
238 #define CHNL_CSC_COEFF4_D1_MASK					GENMASK(24, 16)
239 #define CHNL_CSC_COEFF4_C3(n)					((n) << 0)
240 #define CHNL_CSC_COEFF4_C3_MASK					GENMASK(10, 0)
241 
242 /* Channel Color Space Conversion Coefficient Register 5 */
243 #define CHNL_CSC_COEFF5						0x003c
244 #define CHNL_CSC_COEFF5_D3(n)					((n) << 16)
245 #define CHNL_CSC_COEFF5_D3_MASK					GENMASK(24, 16)
246 #define CHNL_CSC_COEFF5_D2(n)					((n) << 0)
247 #define CHNL_CSC_COEFF5_D2_MASK					GENMASK(8, 0)
248 
249 /* Channel Alpha Value Register for ROI 0 */
250 #define CHNL_ROI_0_ALPHA					0x0040
251 #define CHNL_ROI_0_ALPHA_VAL(n)					((n) << 24)
252 #define CHNL_ROI_0_ALPHA_MASK					GENMASK(31, 24)
253 #define CHNL_ROI_0_ALPHA_EN					BIT(16)
254 
255 /* Channel Upper Left Coordinate Register for ROI 0 */
256 #define CHNL_ROI_0_ULC						0x0044
257 #define CHNL_ROI_0_ULC_X(n)					((n) << 16)
258 #define CHNL_ROI_0_ULC_X_MASK					GENMASK(27, 16)
259 #define CHNL_ROI_0_ULC_Y(n)					((n) << 0)
260 #define CHNL_ROI_0_ULC_Y_MASK					GENMASK(11, 0)
261 
262 /* Channel Lower Right Coordinate Register for ROI 0 */
263 #define CHNL_ROI_0_LRC						0x0048
264 #define CHNL_ROI_0_LRC_X(n)					((n) << 16)
265 #define CHNL_ROI_0_LRC_X_MASK					GENMASK(27, 16)
266 #define CHNL_ROI_0_LRC_Y(n)					((n) << 0)
267 #define CHNL_ROI_0_LRC_Y_MASK					GENMASK(11, 0)
268 
269 /* Channel Alpha Value Register for ROI 1 */
270 #define CHNL_ROI_1_ALPHA					0x004c
271 #define CHNL_ROI_1_ALPHA_VAL(n)					((n) << 24)
272 #define CHNL_ROI_1_ALPHA_MASK					GENMASK(31, 24)
273 #define CHNL_ROI_1_ALPHA_EN					BIT(16)
274 
275 /* Channel Upper Left Coordinate Register for ROI 1 */
276 #define CHNL_ROI_1_ULC						0x0050
277 #define CHNL_ROI_1_ULC_X(n)					((n) << 16)
278 #define CHNL_ROI_1_ULC_X_MASK					GENMASK(27, 16)
279 #define CHNL_ROI_1_ULC_Y(n)					((n) << 0)
280 #define CHNL_ROI_1_ULC_Y_MASK					GENMASK(11, 0)
281 
282 /* Channel Lower Right Coordinate Register for ROI 1 */
283 #define CHNL_ROI_1_LRC						0x0054
284 #define CHNL_ROI_1_LRC_X(n)					((n) << 16)
285 #define CHNL_ROI_1_LRC_X_MASK					GENMASK(27, 16)
286 #define CHNL_ROI_1_LRC_Y(n)					((n) << 0)
287 #define CHNL_ROI_1_LRC_Y_MASK					GENMASK(11, 0)
288 
289 /* Channel Alpha Value Register for ROI 2 */
290 #define CHNL_ROI_2_ALPHA					0x0058
291 #define CHNL_ROI_2_ALPHA_VAL(n)					((n) << 24)
292 #define CHNL_ROI_2_ALPHA_MASK					GENMASK(31, 24)
293 #define CHNL_ROI_2_ALPHA_EN					BIT(16)
294 
295 /* Channel Upper Left Coordinate Register for ROI 2 */
296 #define CHNL_ROI_2_ULC						0x005c
297 #define CHNL_ROI_2_ULC_X(n)					((n) << 16)
298 #define CHNL_ROI_2_ULC_X_MASK					GENMASK(27, 16)
299 #define CHNL_ROI_2_ULC_Y(n)					((n) << 0)
300 #define CHNL_ROI_2_ULC_Y_MASK					GENMASK(11, 0)
301 
302 /* Channel Lower Right Coordinate Register for ROI 2 */
303 #define CHNL_ROI_2_LRC						0x0060
304 #define CHNL_ROI_2_LRC_X(n)					((n) << 16)
305 #define CHNL_ROI_2_LRC_X_MASK					GENMASK(27, 16)
306 #define CHNL_ROI_2_LRC_Y(n)					((n) << 0)
307 #define CHNL_ROI_2_LRC_Y_MASK					GENMASK(11, 0)
308 
309 /* Channel Alpha Value Register for ROI 3 */
310 #define CHNL_ROI_3_ALPHA					0x0064
311 #define CHNL_ROI_3_ALPHA_VAL(n)					((n) << 24)
312 #define CHNL_ROI_3_ALPHA_MASK					GENMASK(31, 24)
313 #define CHNL_ROI_3_ALPHA_EN					BIT(16)
314 
315 /* Channel Upper Left Coordinate Register for ROI 3 */
316 #define CHNL_ROI_3_ULC						0x0068
317 #define CHNL_ROI_3_ULC_X(n)					((n) << 16)
318 #define CHNL_ROI_3_ULC_X_MASK					GENMASK(27, 16)
319 #define CHNL_ROI_3_ULC_Y(n)					((n) << 0)
320 #define CHNL_ROI_3_ULC_Y_MASK					GENMASK(11, 0)
321 
322 /* Channel Lower Right Coordinate Register for ROI 3 */
323 #define CHNL_ROI_3_LRC						0x006c
324 #define CHNL_ROI_3_LRC_X(n)					((n) << 16)
325 #define CHNL_ROI_3_LRC_X_MASK					GENMASK(27, 16)
326 #define CHNL_ROI_3_LRC_Y(n)					((n) << 0)
327 #define CHNL_ROI_3_LRC_Y_MASK					GENMASK(11, 0)
328 /* Channel RGB or Luma (Y) Output Buffer 1 Address */
329 #define CHNL_OUT_BUF1_ADDR_Y					0x0070
330 
331 /* Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address */
332 #define CHNL_OUT_BUF1_ADDR_U					0x0074
333 
334 /* Channel Chroma (V/Cr) Output Buffer 1 Address */
335 #define CHNL_OUT_BUF1_ADDR_V					0x0078
336 
337 /* Channel Output Buffer Pitch */
338 #define CHNL_OUT_BUF_PITCH					0x007c
339 #define CHNL_OUT_BUF_PITCH_LINE_PITCH(n)			((n) << 0)
340 #define CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK			GENMASK(15, 0)
341 
342 /* Channel Input Buffer Address */
343 #define CHNL_IN_BUF_ADDR					0x0080
344 
345 /* Channel Input Buffer Pitch */
346 #define CHNL_IN_BUF_PITCH					0x0084
347 #define CHNL_IN_BUF_PITCH_FRM_PITCH(n)				((n) << 16)
348 #define CHNL_IN_BUF_PITCH_FRM_PITCH_MASK			GENMASK(31, 16)
349 #define CHNL_IN_BUF_PITCH_LINE_PITCH(n)				((n) << 0)
350 #define CHNL_IN_BUF_PITCH_LINE_PITCH_MASK			GENMASK(15, 0)
351 
352 /* Channel Memory Read Control */
353 #define CHNL_MEM_RD_CTRL					0x0088
354 #define CHNL_MEM_RD_CTRL_IMG_TYPE(n)				((n) << 28)
355 #define CHNL_MEM_RD_CTRL_IMG_TYPE_MASK				GENMASK(31, 28)
356 #define CHNL_MEM_RD_CTRL_IMG_TYPE_BGR8P				0x00
357 #define CHNL_MEM_RD_CTRL_IMG_TYPE_RGB8P				0x01
358 #define CHNL_MEM_RD_CTRL_IMG_TYPE_XRGB8				0x02
359 #define CHNL_MEM_RD_CTRL_IMG_TYPE_RGBX8				0x03
360 #define CHNL_MEM_RD_CTRL_IMG_TYPE_XBGR8				0x04
361 #define CHNL_MEM_RD_CTRL_IMG_TYPE_RGB565			0x05
362 #define CHNL_MEM_RD_CTRL_IMG_TYPE_A2BGR10			0x06
363 #define CHNL_MEM_RD_CTRL_IMG_TYPE_A2RGB10			0x07
364 #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P8P			0x08
365 #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P10			0x09
366 #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P10P			0x0a
367 #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P12			0x0b
368 #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P8			0x0c
369 #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV422_1P8P			0x0d
370 #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV422_1P10			0x0e
371 #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV422_1P12			0x0f
372 #define CHNL_MEM_RD_CTRL_READ_MEM				BIT(0)
373 
374 /* Channel RGB or Luma (Y) Output Buffer 2 Address */
375 #define CHNL_OUT_BUF2_ADDR_Y					0x008c
376 
377 /* Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address  */
378 #define CHNL_OUT_BUF2_ADDR_U					0x0090
379 
380 /* Channel Chroma (V/Cr) Output Buffer 2 Address   */
381 #define CHNL_OUT_BUF2_ADDR_V					0x0094
382 
383 /* Channel scale image config */
384 #define CHNL_SCL_IMG_CFG					0x0098
385 #define CHNL_SCL_IMG_CFG_HEIGHT(n)				((n) << 16)
386 #define CHNL_SCL_IMG_CFG_HEIGHT_MASK				GENMASK(28, 16)
387 #define CHNL_SCL_IMG_CFG_WIDTH(n)				((n) << 0)
388 #define CHNL_SCL_IMG_CFG_WIDTH_MASK				GENMASK(12, 0)
389 
390 /* Channel Flow Control Register */
391 #define CHNL_FLOW_CTRL						0x009c
392 #define CHNL_FLOW_CTRL_FC_DENOM_MASK				GENMASK(7, 0)
393 #define CHNL_FLOW_CTRL_FC_DENOM(n)				((n) << 0)
394 #define CHNL_FLOW_CTRL_FC_NUMER_MASK				GENMASK(23, 16)
395 #define CHNL_FLOW_CTRL_FC_NUMER(n)				((n) << 0)
396 
397 /* Channel Output Y-Buffer 1 Extended Address Bits */
398 #define CHNL_Y_BUF1_XTND_ADDR					0x00a0
399 
400 /* Channel Output U-Buffer 1 Extended Address Bits */
401 #define CHNL_U_BUF1_XTND_ADDR					0x00a4
402 
403 /* Channel Output V-Buffer 1 Extended Address Bits */
404 #define CHNL_V_BUF1_XTND_ADDR					0x00a8
405 
406 /* Channel Output Y-Buffer 2 Extended Address Bits */
407 #define CHNL_Y_BUF2_XTND_ADDR					0x00ac
408 
409 /* Channel Output U-Buffer 2 Extended Address Bits */
410 #define CHNL_U_BUF2_XTND_ADDR					0x00b0
411 
412 /* Channel Output V-Buffer 2 Extended Address Bits */
413 #define CHNL_V_BUF2_XTND_ADDR					0x00b4
414 
415 /* Channel Input Buffer Extended Address Bits */
416 #define CHNL_IN_BUF_XTND_ADDR					0x00b8
417 
418 #endif /* __IMX8_ISI_REGS_H__ */
419