1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * SPI core driver for the Ocelot chip family.
4 *
5 * This driver will handle everything necessary to allow for communication over
6 * SPI to the VSC7511, VSC7512, VSC7513 and VSC7514 chips. The main functions
7 * are to prepare the chip's SPI interface for a specific bus speed, and a host
8 * processor's endianness. This will create and distribute regmaps for any
9 * children.
10 *
11 * Copyright 2021-2022 Innovative Advantage Inc.
12 *
13 * Author: Colin Foster <colin.foster@in-advantage.com>
14 */
15
16 #include <linux/device.h>
17 #include <linux/err.h>
18 #include <linux/errno.h>
19 #include <linux/export.h>
20 #include <linux/ioport.h>
21 #include <linux/module.h>
22 #include <linux/regmap.h>
23 #include <linux/spi/spi.h>
24 #include <linux/types.h>
25 #include <linux/units.h>
26
27 #include "ocelot.h"
28
29 #define REG_DEV_CPUORG_IF_CTRL 0x0000
30 #define REG_DEV_CPUORG_IF_CFGSTAT 0x0004
31
32 #define CFGSTAT_IF_NUM_VCORE (0 << 24)
33 #define CFGSTAT_IF_NUM_VRAP (1 << 24)
34 #define CFGSTAT_IF_NUM_SI (2 << 24)
35 #define CFGSTAT_IF_NUM_MIIM (3 << 24)
36
37 #define VSC7512_DEVCPU_ORG_RES_START 0x71000000
38 #define VSC7512_DEVCPU_ORG_RES_SIZE 0x38
39
40 #define VSC7512_CHIP_REGS_RES_START 0x71070000
41 #define VSC7512_CHIP_REGS_RES_SIZE 0x14
42
43 static const struct resource vsc7512_dev_cpuorg_resource =
44 DEFINE_RES_REG_NAMED(VSC7512_DEVCPU_ORG_RES_START,
45 VSC7512_DEVCPU_ORG_RES_SIZE,
46 "devcpu_org");
47
48 static const struct resource vsc7512_gcb_resource =
49 DEFINE_RES_REG_NAMED(VSC7512_CHIP_REGS_RES_START,
50 VSC7512_CHIP_REGS_RES_SIZE,
51 "devcpu_gcb_chip_regs");
52
ocelot_spi_initialize(struct device * dev)53 static int ocelot_spi_initialize(struct device *dev)
54 {
55 struct ocelot_ddata *ddata = dev_get_drvdata(dev);
56 u32 val, check;
57 int err;
58
59 val = OCELOT_SPI_BYTE_ORDER;
60
61 /*
62 * The SPI address must be big-endian, but we want the payload to match
63 * our CPU. These are two bits (0 and 1) but they're repeated such that
64 * the write from any configuration will be valid. The four
65 * configurations are:
66 *
67 * 0b00: little-endian, MSB first
68 * | 111111 | 22221111 | 33222222 |
69 * | 76543210 | 54321098 | 32109876 | 10987654 |
70 *
71 * 0b01: big-endian, MSB first
72 * | 33222222 | 22221111 | 111111 | |
73 * | 10987654 | 32109876 | 54321098 | 76543210 |
74 *
75 * 0b10: little-endian, LSB first
76 * | 111111 | 11112222 | 22222233 |
77 * | 01234567 | 89012345 | 67890123 | 45678901 |
78 *
79 * 0b11: big-endian, LSB first
80 * | 22222233 | 11112222 | 111111 | |
81 * | 45678901 | 67890123 | 89012345 | 01234567 |
82 */
83 err = regmap_write(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CTRL, val);
84 if (err)
85 return err;
86
87 /*
88 * Apply the number of padding bytes between a read request and the data
89 * payload. Some registers have access times of up to 1us, so if the
90 * first payload bit is shifted out too quickly, the read will fail.
91 */
92 val = ddata->spi_padding_bytes;
93 err = regmap_write(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CFGSTAT, val);
94 if (err)
95 return err;
96
97 /*
98 * After we write the interface configuration, read it back here. This
99 * will verify several different things. The first is that the number of
100 * padding bytes actually got written correctly. These are found in bits
101 * 0:3.
102 *
103 * The second is that bit 16 is cleared. Bit 16 is IF_CFGSTAT:IF_STAT,
104 * and will be set if the register access is too fast. This would be in
105 * the condition that the number of padding bytes is insufficient for
106 * the SPI bus frequency.
107 *
108 * The last check is for bits 31:24, which define the interface by which
109 * the registers are being accessed. Since we're accessing them via the
110 * serial interface, it must return IF_NUM_SI.
111 */
112 check = val | CFGSTAT_IF_NUM_SI;
113
114 err = regmap_read(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CFGSTAT, &val);
115 if (err)
116 return err;
117
118 if (check != val)
119 return -ENODEV;
120
121 return 0;
122 }
123
124 static const struct regmap_config ocelot_spi_regmap_config = {
125 .reg_bits = 24,
126 .reg_stride = 4,
127 .reg_shift = REGMAP_DOWNSHIFT(2),
128 .val_bits = 32,
129
130 .write_flag_mask = 0x80,
131
132 .use_single_read = true,
133 .use_single_write = true,
134 .can_multi_write = false,
135
136 .reg_format_endian = REGMAP_ENDIAN_BIG,
137 .val_format_endian = REGMAP_ENDIAN_NATIVE,
138 };
139
ocelot_spi_regmap_bus_read(void * context,const void * reg,size_t reg_size,void * val,size_t val_size)140 static int ocelot_spi_regmap_bus_read(void *context, const void *reg, size_t reg_size,
141 void *val, size_t val_size)
142 {
143 struct spi_transfer xfers[3] = {0};
144 struct device *dev = context;
145 struct ocelot_ddata *ddata;
146 struct spi_device *spi;
147 unsigned int index = 0;
148
149 ddata = dev_get_drvdata(dev);
150 spi = to_spi_device(dev);
151
152 xfers[index].tx_buf = reg;
153 xfers[index].len = reg_size;
154 index++;
155
156 if (ddata->spi_padding_bytes) {
157 xfers[index].len = ddata->spi_padding_bytes;
158 xfers[index].tx_buf = ddata->dummy_buf;
159 xfers[index].dummy_data = 1;
160 index++;
161 }
162
163 xfers[index].rx_buf = val;
164 xfers[index].len = val_size;
165 index++;
166
167 return spi_sync_transfer(spi, xfers, index);
168 }
169
ocelot_spi_regmap_bus_write(void * context,const void * data,size_t count)170 static int ocelot_spi_regmap_bus_write(void *context, const void *data, size_t count)
171 {
172 struct device *dev = context;
173 struct spi_device *spi = to_spi_device(dev);
174
175 return spi_write(spi, data, count);
176 }
177
178 static const struct regmap_bus ocelot_spi_regmap_bus = {
179 .write = ocelot_spi_regmap_bus_write,
180 .read = ocelot_spi_regmap_bus_read,
181 };
182
ocelot_spi_init_regmap(struct device * dev,const struct resource * res)183 struct regmap *ocelot_spi_init_regmap(struct device *dev, const struct resource *res)
184 {
185 struct regmap_config regmap_config;
186
187 memcpy(®map_config, &ocelot_spi_regmap_config, sizeof(regmap_config));
188
189 regmap_config.name = res->name;
190 regmap_config.max_register = resource_size(res) - 1;
191 regmap_config.reg_base = res->start;
192
193 return devm_regmap_init(dev, &ocelot_spi_regmap_bus, dev, ®map_config);
194 }
195 EXPORT_SYMBOL_NS(ocelot_spi_init_regmap, "MFD_OCELOT_SPI");
196
ocelot_spi_probe(struct spi_device * spi)197 static int ocelot_spi_probe(struct spi_device *spi)
198 {
199 struct device *dev = &spi->dev;
200 struct ocelot_ddata *ddata;
201 struct regmap *r;
202 int err;
203
204 ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
205 if (!ddata)
206 return -ENOMEM;
207
208 spi_set_drvdata(spi, ddata);
209
210 if (spi->max_speed_hz <= 500000) {
211 ddata->spi_padding_bytes = 0;
212 } else {
213 /*
214 * Calculation taken from the manual for IF_CFGSTAT:IF_CFG.
215 * Register access time is 1us, so we need to configure and send
216 * out enough padding bytes between the read request and data
217 * transmission that lasts at least 1 microsecond.
218 */
219 ddata->spi_padding_bytes = 1 + (spi->max_speed_hz / HZ_PER_MHZ + 2) / 8;
220
221 ddata->dummy_buf = devm_kzalloc(dev, ddata->spi_padding_bytes, GFP_KERNEL);
222 if (!ddata->dummy_buf)
223 return -ENOMEM;
224 }
225
226 spi->bits_per_word = 8;
227
228 err = spi_setup(spi);
229 if (err)
230 return dev_err_probe(&spi->dev, err, "Error performing SPI setup\n");
231
232 r = ocelot_spi_init_regmap(dev, &vsc7512_dev_cpuorg_resource);
233 if (IS_ERR(r))
234 return PTR_ERR(r);
235
236 ddata->cpuorg_regmap = r;
237
238 r = ocelot_spi_init_regmap(dev, &vsc7512_gcb_resource);
239 if (IS_ERR(r))
240 return PTR_ERR(r);
241
242 ddata->gcb_regmap = r;
243
244 /*
245 * The chip must be set up for SPI before it gets initialized and reset.
246 * This must be done before calling init, and after a chip reset is
247 * performed.
248 */
249 err = ocelot_spi_initialize(dev);
250 if (err)
251 return dev_err_probe(dev, err, "Error initializing SPI bus\n");
252
253 err = ocelot_chip_reset(dev);
254 if (err)
255 return dev_err_probe(dev, err, "Error resetting device\n");
256
257 /*
258 * A chip reset will clear the SPI configuration, so it needs to be done
259 * again before we can access any registers.
260 */
261 err = ocelot_spi_initialize(dev);
262 if (err)
263 return dev_err_probe(dev, err, "Error initializing SPI bus after reset\n");
264
265 err = ocelot_core_init(dev);
266 if (err)
267 return dev_err_probe(dev, err, "Error initializing Ocelot core\n");
268
269 return 0;
270 }
271
272 static const struct spi_device_id ocelot_spi_ids[] = {
273 { .name = "vsc7512" },
274 { }
275 };
276 MODULE_DEVICE_TABLE(spi, ocelot_spi_ids);
277
278 static const struct of_device_id ocelot_spi_of_match[] = {
279 { .compatible = "mscc,vsc7512" },
280 { }
281 };
282 MODULE_DEVICE_TABLE(of, ocelot_spi_of_match);
283
284 static struct spi_driver ocelot_spi_driver = {
285 .driver = {
286 .name = "ocelot-soc",
287 .of_match_table = ocelot_spi_of_match,
288 },
289 .id_table = ocelot_spi_ids,
290 .probe = ocelot_spi_probe,
291 };
292 module_spi_driver(ocelot_spi_driver);
293
294 MODULE_DESCRIPTION("SPI Controlled Ocelot Chip Driver");
295 MODULE_AUTHOR("Colin Foster <colin.foster@in-advantage.com>");
296 MODULE_LICENSE("Dual MIT/GPL");
297 MODULE_IMPORT_NS("MFD_OCELOT");
298