1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
3
4 #define CREATE_TRACE_POINTS
5 #include <trace/events/qcom_geni_i2c.h>
6
7 #include <linux/acpi.h>
8 #include <linux/clk.h>
9 #include <linux/dmaengine.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/dma/qcom-gpi-dma.h>
12 #include <linux/err.h>
13 #include <linux/i2c.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/soc/qcom/geni-se.h>
21 #include <linux/spinlock.h>
22 #include <linux/units.h>
23
24 #define SE_I2C_TX_TRANS_LEN 0x26c
25 #define SE_I2C_RX_TRANS_LEN 0x270
26 #define SE_I2C_SCL_COUNTERS 0x278
27
28 #define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
29 M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
30 #define SE_I2C_ABORT BIT(1)
31
32 /* M_CMD OP codes for I2C */
33 #define I2C_WRITE 0x1
34 #define I2C_READ 0x2
35 #define I2C_WRITE_READ 0x3
36 #define I2C_ADDR_ONLY 0x4
37 #define I2C_BUS_CLEAR 0x6
38 #define I2C_STOP_ON_BUS 0x7
39 /* M_CMD params for I2C */
40 #define PRE_CMD_DELAY BIT(0)
41 #define TIMESTAMP_BEFORE BIT(1)
42 #define STOP_STRETCH BIT(2)
43 #define TIMESTAMP_AFTER BIT(3)
44 #define POST_COMMAND_DELAY BIT(4)
45 #define IGNORE_ADD_NACK BIT(6)
46 #define READ_FINISHED_WITH_ACK BIT(7)
47 #define BYPASS_ADDR_PHASE BIT(8)
48 #define SLV_ADDR_MSK GENMASK(15, 9)
49 #define SLV_ADDR_SHFT 9
50 /* I2C SCL COUNTER fields */
51 #define HIGH_COUNTER_MSK GENMASK(29, 20)
52 #define HIGH_COUNTER_SHFT 20
53 #define LOW_COUNTER_MSK GENMASK(19, 10)
54 #define LOW_COUNTER_SHFT 10
55 #define CYCLE_COUNTER_MSK GENMASK(9, 0)
56
57 #define I2C_PACK_TX BIT(0)
58 #define I2C_PACK_RX BIT(1)
59
60 enum geni_i2c_err_code {
61 GP_IRQ0,
62 ADDR_NACK,
63 DATA_NACK,
64 GP_IRQ2,
65 BUS_PROTO,
66 ARB_LOST,
67 GP_IRQ5,
68 GENI_OVERRUN,
69 GENI_ILLEGAL_CMD,
70 GENI_ABORT_DONE,
71 GENI_TIMEOUT,
72 };
73
74 #define DM_I2C_CB_ERR ((BIT(ADDR_NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \
75 << 5)
76
77 #define I2C_AUTO_SUSPEND_DELAY 250
78 #define PACKING_BYTES_PW 4
79
80 #define ABORT_TIMEOUT HZ
81 #define CANCEL_TIMEOUT HZ
82 #define XFER_TIMEOUT HZ
83 #define RST_TIMEOUT HZ
84
85 struct geni_i2c_desc {
86 bool no_dma_support;
87 unsigned int tx_fifo_depth;
88 int (*resources_init)(struct geni_se *se);
89 int (*set_rate)(struct geni_se *se, unsigned long freq);
90 int (*power_on)(struct geni_se *se);
91 int (*power_off)(struct geni_se *se);
92 };
93
94 #define QCOM_I2C_MIN_NUM_OF_MSGS_MULTI_DESC 2
95
96 /**
97 * struct geni_i2c_gpi_multi_desc_xfer - Structure for multi transfer support
98 *
99 * @msg_idx_cnt: Current message index being processed in the transfer
100 * @unmap_msg_cnt: Number of messages that have been unmapped
101 * @irq_cnt: Number of transfer completion interrupts received
102 * @dma_buf: Array of virtual addresses for DMA-safe buffers
103 * @dma_addr: Array of DMA addresses corresponding to the buffers
104 */
105 struct geni_i2c_gpi_multi_desc_xfer {
106 u32 msg_idx_cnt;
107 u32 unmap_msg_cnt;
108 u32 irq_cnt;
109 void **dma_buf;
110 dma_addr_t *dma_addr;
111 };
112
113 struct geni_i2c_dev {
114 struct geni_se se;
115 u32 tx_wm;
116 int irq;
117 int err;
118 struct i2c_adapter adap;
119 struct completion done;
120 struct completion abort_done;
121 struct completion cancel_done;
122 struct completion tx_reset_done;
123 struct completion rx_reset_done;
124 struct i2c_msg *cur;
125 int cur_wr;
126 int cur_rd;
127 spinlock_t lock;
128 u32 clk_freq_out;
129 const struct geni_i2c_clk_fld *clk_fld;
130 void *dma_buf;
131 size_t xfer_len;
132 dma_addr_t dma_addr;
133 struct dma_chan *tx_c;
134 struct dma_chan *rx_c;
135 bool no_dma;
136 bool gpi_mode;
137 bool is_tx_multi_desc_xfer;
138 u32 num_msgs;
139 struct geni_i2c_gpi_multi_desc_xfer i2c_multi_desc_config;
140 const struct geni_i2c_desc *dev_data;
141 };
142
143 struct geni_i2c_err_log {
144 int err;
145 const char *msg;
146 };
147
148 static const struct geni_i2c_err_log gi2c_log[] = {
149 [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"},
150 [ADDR_NACK] = {-ENXIO, "NACK: target device unresponsive, check its power/reset-ln"},
151 [DATA_NACK] = {-EIO, "Data NACK: TX transfer NACK"},
152 [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"},
153 [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unexpected start/stop"},
154 [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"},
155 [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"},
156 [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"},
157 [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"},
158 [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"},
159 [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"},
160 };
161
162 struct geni_i2c_clk_fld {
163 u32 clk_freq_out;
164 u8 clk_div;
165 u8 t_high_cnt;
166 u8 t_low_cnt;
167 u8 t_cycle_cnt;
168 };
169
170 /*
171 * Hardware uses the underlying formula to calculate time periods of
172 * SCL clock cycle. Firmware uses some additional cycles excluded from the
173 * below formula and it is confirmed that the time periods are within
174 * specification limits.
175 *
176 * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock
177 * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock
178 * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock
179 * clk_freq_out = t / t_cycle
180 * source_clock = 19.2 MHz
181 */
182 static const struct geni_i2c_clk_fld geni_i2c_clk_map_19p2mhz[] = {
183 { I2C_MAX_STANDARD_MODE_FREQ, 7, 10, 12, 26 },
184 { I2C_MAX_FAST_MODE_FREQ, 2, 5, 11, 22 },
185 { I2C_MAX_FAST_MODE_PLUS_FREQ, 1, 2, 8, 18 },
186 {}
187 };
188
189 /* source_clock = 32 MHz */
190 static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = {
191 { I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 26 },
192 { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 19 },
193 { I2C_MAX_FAST_MODE_PLUS_FREQ, 2, 3, 5, 15 },
194 {}
195 };
196
geni_i2c_clk_map_idx(struct geni_i2c_dev * gi2c)197 static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c)
198 {
199 const struct geni_i2c_clk_fld *itr;
200
201 if (clk_get_rate(gi2c->se.clk) == 32 * HZ_PER_MHZ)
202 itr = geni_i2c_clk_map_32mhz;
203 else
204 itr = geni_i2c_clk_map_19p2mhz;
205
206 while (itr->clk_freq_out != 0) {
207 if (itr->clk_freq_out == gi2c->clk_freq_out) {
208 gi2c->clk_fld = itr;
209 return 0;
210 }
211 itr++;
212 }
213 return -EINVAL;
214 }
215
qcom_geni_i2c_conf(struct geni_se * se,unsigned long freq)216 static int qcom_geni_i2c_conf(struct geni_se *se, unsigned long freq)
217 {
218 struct geni_i2c_dev *gi2c = dev_get_drvdata(se->dev);
219 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
220 u32 val;
221
222 writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL);
223
224 val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN;
225 writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG);
226
227 val = itr->t_high_cnt << HIGH_COUNTER_SHFT;
228 val |= itr->t_low_cnt << LOW_COUNTER_SHFT;
229 val |= itr->t_cycle_cnt;
230 writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
231 trace_geni_i2c_bus_setup(gi2c->se.dev, gi2c->clk_freq_out,
232 itr->clk_div, itr->t_high_cnt,
233 itr->t_low_cnt, itr->t_cycle_cnt);
234 return 0;
235 }
236
geni_i2c_err_misc(struct geni_i2c_dev * gi2c)237 static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
238 {
239 u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
240 u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
241 u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS);
242 u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS);
243 u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN);
244 u32 rx_st, tx_st;
245
246 if (dma) {
247 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
248 tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
249 } else {
250 rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS);
251 tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS);
252 }
253 dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n",
254 dma, tx_st, rx_st, m_stat);
255 dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n",
256 m_cmd, geni_s, geni_ios);
257 }
258
geni_i2c_err(struct geni_i2c_dev * gi2c,int err)259 static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err)
260 {
261 if (!gi2c->err)
262 gi2c->err = gi2c_log[err].err;
263 if (gi2c->cur)
264 dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n",
265 gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags);
266
267 trace_geni_i2c_err(gi2c->se.dev, gi2c_log[err].err, gi2c_log[err].msg);
268
269 switch (err) {
270 case GENI_ABORT_DONE:
271 case ADDR_NACK:
272 case DATA_NACK:
273 case GENI_TIMEOUT:
274 dev_dbg(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
275 break;
276 default:
277 dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
278 geni_i2c_err_misc(gi2c);
279 break;
280 }
281 }
282
geni_i2c_check_addr_data_nack(struct geni_i2c_dev * gi2c)283 static void geni_i2c_check_addr_data_nack(struct geni_i2c_dev *gi2c)
284 {
285 if (!readl_relaxed(gi2c->se.base + SE_GENI_M_GP_LENGTH))
286 geni_i2c_err(gi2c, ADDR_NACK);
287 else if (!(gi2c->cur->flags & I2C_M_RD))
288 geni_i2c_err(gi2c, DATA_NACK);
289 }
290
geni_i2c_irq(int irq,void * dev)291 static irqreturn_t geni_i2c_irq(int irq, void *dev)
292 {
293 struct geni_i2c_dev *gi2c = dev;
294 void __iomem *base = gi2c->se.base;
295 int j, p;
296 u32 m_stat;
297 u32 rx_st;
298 u32 dm_tx_st;
299 u32 dm_rx_st;
300 u32 dma;
301 u32 val;
302 struct i2c_msg *cur;
303
304 spin_lock(&gi2c->lock);
305 m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS);
306 rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS);
307 dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT);
308 dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT);
309 dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
310 cur = gi2c->cur;
311
312 trace_geni_i2c_irq(gi2c->se.dev, m_stat, rx_st, dm_tx_st, dm_rx_st);
313
314 if (!cur ||
315 m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) ||
316 dm_rx_st & (DM_I2C_CB_ERR)) {
317 if (m_stat & M_GP_IRQ_1_EN)
318 geni_i2c_check_addr_data_nack(gi2c);
319 if (m_stat & M_GP_IRQ_3_EN)
320 geni_i2c_err(gi2c, BUS_PROTO);
321 if (m_stat & M_GP_IRQ_4_EN)
322 geni_i2c_err(gi2c, ARB_LOST);
323 if (m_stat & M_CMD_OVERRUN_EN)
324 geni_i2c_err(gi2c, GENI_OVERRUN);
325 if (m_stat & M_ILLEGAL_CMD_EN)
326 geni_i2c_err(gi2c, GENI_ILLEGAL_CMD);
327 if (m_stat & M_CMD_ABORT_EN)
328 geni_i2c_err(gi2c, GENI_ABORT_DONE);
329 if (m_stat & M_GP_IRQ_0_EN)
330 geni_i2c_err(gi2c, GP_IRQ0);
331
332 /* Disable the TX Watermark interrupt to stop TX */
333 if (!dma)
334 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
335 } else if (dma) {
336 dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n",
337 dm_tx_st, dm_rx_st);
338 } else if (cur->flags & I2C_M_RD &&
339 m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) {
340 u32 rxcnt = rx_st & RX_FIFO_WC_MSK;
341
342 for (j = 0; j < rxcnt; j++) {
343 p = 0;
344 val = readl_relaxed(base + SE_GENI_RX_FIFOn);
345 while (gi2c->cur_rd < cur->len && p < sizeof(val)) {
346 cur->buf[gi2c->cur_rd++] = val & 0xff;
347 val >>= 8;
348 p++;
349 }
350 if (gi2c->cur_rd == cur->len)
351 break;
352 }
353 } else if (!(cur->flags & I2C_M_RD) &&
354 m_stat & M_TX_FIFO_WATERMARK_EN) {
355 for (j = 0; j < gi2c->tx_wm; j++) {
356 u32 temp;
357
358 val = 0;
359 p = 0;
360 while (gi2c->cur_wr < cur->len && p < sizeof(val)) {
361 temp = cur->buf[gi2c->cur_wr++];
362 val |= temp << (p * 8);
363 p++;
364 }
365 writel_relaxed(val, base + SE_GENI_TX_FIFOn);
366 /* TX Complete, Disable the TX Watermark interrupt */
367 if (gi2c->cur_wr == cur->len) {
368 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
369 break;
370 }
371 }
372 }
373
374 if (m_stat)
375 writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR);
376
377 if (dma && dm_tx_st)
378 writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR);
379 if (dma && dm_rx_st)
380 writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR);
381
382 /* if this is err with done-bit not set, handle that through timeout. */
383 if (m_stat & M_CMD_DONE_EN ||
384 dm_tx_st & TX_DMA_DONE ||
385 dm_rx_st & RX_DMA_DONE)
386 complete(&gi2c->done);
387 if (m_stat & M_CMD_CANCEL_EN)
388 complete(&gi2c->cancel_done);
389 if (m_stat & M_CMD_ABORT_EN)
390 complete(&gi2c->abort_done);
391 if (dm_tx_st & TX_RESET_DONE)
392 complete(&gi2c->tx_reset_done);
393 if (dm_rx_st & RX_RESET_DONE)
394 complete(&gi2c->rx_reset_done);
395
396 spin_unlock(&gi2c->lock);
397
398 return IRQ_HANDLED;
399 }
400
geni_i2c_abort_xfer(struct geni_i2c_dev * gi2c)401 static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c)
402 {
403 unsigned long time_left = ABORT_TIMEOUT;
404 unsigned long flags;
405
406 reinit_completion(&gi2c->abort_done);
407
408 spin_lock_irqsave(&gi2c->lock, flags);
409 geni_se_abort_m_cmd(&gi2c->se);
410 spin_unlock_irqrestore(&gi2c->lock, flags);
411
412 time_left = wait_for_completion_timeout(&gi2c->abort_done, time_left);
413 if (!time_left)
414 dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n");
415 }
416
geni_i2c_cancel_xfer(struct geni_i2c_dev * gi2c)417 static void geni_i2c_cancel_xfer(struct geni_i2c_dev *gi2c)
418 {
419 unsigned long time_left = msecs_to_jiffies(CANCEL_TIMEOUT);
420 unsigned long flags;
421
422 reinit_completion(&gi2c->cancel_done);
423
424 spin_lock_irqsave(&gi2c->lock, flags);
425 if (!gi2c->err)
426 geni_i2c_err(gi2c, GENI_TIMEOUT);
427 gi2c->cur = NULL;
428 geni_se_cancel_m_cmd(&gi2c->se);
429 spin_unlock_irqrestore(&gi2c->lock, flags);
430
431 time_left = wait_for_completion_timeout(&gi2c->cancel_done, time_left);
432 if (!time_left) {
433 dev_err(gi2c->se.dev, "Timeout cancel_m_cmd\n");
434 geni_i2c_abort_xfer(gi2c);
435 }
436 }
437
geni_i2c_rx_fsm_rst(struct geni_i2c_dev * gi2c)438 static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c)
439 {
440 unsigned long time_left = RST_TIMEOUT;
441
442 reinit_completion(&gi2c->rx_reset_done);
443 writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST);
444
445 time_left = wait_for_completion_timeout(&gi2c->rx_reset_done, time_left);
446 if (!time_left)
447 dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n");
448 }
449
geni_i2c_tx_fsm_rst(struct geni_i2c_dev * gi2c)450 static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c)
451 {
452 unsigned long time_left = RST_TIMEOUT;
453
454 reinit_completion(&gi2c->tx_reset_done);
455 writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST);
456
457 time_left = wait_for_completion_timeout(&gi2c->tx_reset_done, time_left);
458 if (!time_left)
459 dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n");
460 }
461
geni_i2c_rx_msg_cleanup(struct geni_i2c_dev * gi2c,struct i2c_msg * cur)462 static void geni_i2c_rx_msg_cleanup(struct geni_i2c_dev *gi2c,
463 struct i2c_msg *cur)
464 {
465 gi2c->cur_rd = 0;
466 if (gi2c->dma_buf) {
467 if (gi2c->err && gi2c->err != gi2c_log[ADDR_NACK].err)
468 geni_i2c_rx_fsm_rst(gi2c);
469 geni_se_rx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
470 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err);
471 }
472 }
473
geni_i2c_tx_msg_cleanup(struct geni_i2c_dev * gi2c,struct i2c_msg * cur)474 static void geni_i2c_tx_msg_cleanup(struct geni_i2c_dev *gi2c,
475 struct i2c_msg *cur)
476 {
477 gi2c->cur_wr = 0;
478 if (gi2c->dma_buf) {
479 if (gi2c->err && gi2c->err != gi2c_log[ADDR_NACK].err)
480 geni_i2c_tx_fsm_rst(gi2c);
481 geni_se_tx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
482 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err);
483 }
484 }
485
geni_i2c_rx_one_msg(struct geni_i2c_dev * gi2c,struct i2c_msg * msg,u32 m_param)486 static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
487 u32 m_param)
488 {
489 dma_addr_t rx_dma = 0;
490 unsigned long time_left;
491 void *dma_buf;
492 struct geni_se *se = &gi2c->se;
493 size_t len = msg->len;
494 struct i2c_msg *cur;
495
496 dma_buf = gi2c->no_dma ? NULL : i2c_get_dma_safe_msg_buf(msg, 32);
497 if (dma_buf)
498 geni_se_select_mode(se, GENI_SE_DMA);
499 else
500 geni_se_select_mode(se, GENI_SE_FIFO);
501
502 writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN);
503 geni_se_setup_m_cmd(se, I2C_READ, m_param);
504
505 if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) {
506 geni_se_select_mode(se, GENI_SE_FIFO);
507 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
508 dma_buf = NULL;
509 } else {
510 gi2c->xfer_len = len;
511 gi2c->dma_addr = rx_dma;
512 gi2c->dma_buf = dma_buf;
513 }
514
515 cur = gi2c->cur;
516 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
517 if (!time_left || (gi2c->err && gi2c->err != gi2c_log[ADDR_NACK].err))
518 geni_i2c_cancel_xfer(gi2c);
519
520 geni_i2c_rx_msg_cleanup(gi2c, cur);
521
522 return gi2c->err;
523 }
524
geni_i2c_tx_one_msg(struct geni_i2c_dev * gi2c,struct i2c_msg * msg,u32 m_param)525 static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
526 u32 m_param)
527 {
528 dma_addr_t tx_dma = 0;
529 unsigned long time_left;
530 void *dma_buf;
531 struct geni_se *se = &gi2c->se;
532 size_t len = msg->len;
533 struct i2c_msg *cur;
534
535 dma_buf = gi2c->no_dma ? NULL : i2c_get_dma_safe_msg_buf(msg, 32);
536 if (dma_buf)
537 geni_se_select_mode(se, GENI_SE_DMA);
538 else
539 geni_se_select_mode(se, GENI_SE_FIFO);
540
541 writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN);
542 geni_se_setup_m_cmd(se, I2C_WRITE, m_param);
543
544 if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) {
545 geni_se_select_mode(se, GENI_SE_FIFO);
546 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
547 dma_buf = NULL;
548 } else {
549 gi2c->xfer_len = len;
550 gi2c->dma_addr = tx_dma;
551 gi2c->dma_buf = dma_buf;
552 }
553
554 if (!dma_buf) /* Get FIFO IRQ */
555 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG);
556
557 cur = gi2c->cur;
558 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
559 if (!time_left || (gi2c->err && gi2c->err != gi2c_log[ADDR_NACK].err))
560 geni_i2c_cancel_xfer(gi2c);
561
562 geni_i2c_tx_msg_cleanup(gi2c, cur);
563
564 return gi2c->err;
565 }
566
i2c_gpi_cb_result(void * cb,const struct dmaengine_result * result)567 static void i2c_gpi_cb_result(void *cb, const struct dmaengine_result *result)
568 {
569 struct geni_i2c_dev *gi2c = cb;
570 struct geni_i2c_gpi_multi_desc_xfer *tx_multi_xfer;
571
572 if (result->result != DMA_TRANS_NOERROR) {
573 dev_err(gi2c->se.dev, "DMA txn failed:%d\n", result->result);
574 gi2c->err = -EIO;
575 } else if (result->residue) {
576 dev_dbg(gi2c->se.dev, "DMA xfer has pending: %d\n", result->residue);
577 }
578
579 if (gi2c->is_tx_multi_desc_xfer) {
580 tx_multi_xfer = &gi2c->i2c_multi_desc_config;
581 tx_multi_xfer->irq_cnt++;
582 }
583
584 complete(&gi2c->done);
585 }
586
geni_i2c_gpi_unmap(struct geni_i2c_dev * gi2c,struct i2c_msg * msg,void * tx_buf,dma_addr_t tx_addr,void * rx_buf,dma_addr_t rx_addr)587 static void geni_i2c_gpi_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
588 void *tx_buf, dma_addr_t tx_addr,
589 void *rx_buf, dma_addr_t rx_addr)
590 {
591 if (tx_buf) {
592 dma_unmap_single(gi2c->se.dev->parent, tx_addr, msg->len, DMA_TO_DEVICE);
593 i2c_put_dma_safe_msg_buf(tx_buf, msg, !gi2c->err);
594 }
595
596 if (rx_buf) {
597 dma_unmap_single(gi2c->se.dev->parent, rx_addr, msg->len, DMA_FROM_DEVICE);
598 i2c_put_dma_safe_msg_buf(rx_buf, msg, !gi2c->err);
599 }
600 }
601
602 /**
603 * geni_i2c_gpi_multi_desc_unmap() - Unmaps DMA buffers post multi message TX transfers
604 * @gi2c: I2C dev handle
605 * @msgs: Array of I2C messages
606 * @peripheral: Pointer to gpi_i2c_config
607 */
geni_i2c_gpi_multi_desc_unmap(struct geni_i2c_dev * gi2c,struct i2c_msg msgs[],struct gpi_i2c_config * peripheral)608 static void geni_i2c_gpi_multi_desc_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[],
609 struct gpi_i2c_config *peripheral)
610 {
611 u32 msg_xfer_cnt, wr_idx = 0;
612 struct geni_i2c_gpi_multi_desc_xfer *tx_multi_xfer = &gi2c->i2c_multi_desc_config;
613
614 msg_xfer_cnt = gi2c->err ? tx_multi_xfer->msg_idx_cnt : tx_multi_xfer->irq_cnt;
615
616 /* Unmap the processed DMA buffers based on the received interrupt count */
617 for (; tx_multi_xfer->unmap_msg_cnt < msg_xfer_cnt; tx_multi_xfer->unmap_msg_cnt++) {
618 wr_idx = tx_multi_xfer->unmap_msg_cnt;
619 geni_i2c_gpi_unmap(gi2c, &msgs[wr_idx],
620 tx_multi_xfer->dma_buf[wr_idx],
621 tx_multi_xfer->dma_addr[wr_idx],
622 NULL, 0);
623
624 if (tx_multi_xfer->unmap_msg_cnt == gi2c->num_msgs - 1) {
625 kfree(tx_multi_xfer->dma_buf);
626 kfree(tx_multi_xfer->dma_addr);
627 break;
628 }
629 }
630 }
631
632 /**
633 * geni_i2c_gpi_multi_xfer_timeout_handler() - Handles multi message transfer timeout
634 * @dev: Pointer to the corresponding dev node
635 * @multi_xfer: Pointer to the geni_i2c_gpi_multi_desc_xfer
636 * @transfer_timeout_msecs: Timeout value in milliseconds
637 * @transfer_comp: Completion object of the transfer
638 *
639 * This function waits for the completion of each processed transfer messages
640 * based on the interrupts generated upon transfer completion.
641 *
642 * Return: On success returns 0, -ETIMEDOUT on timeout.
643 */
geni_i2c_gpi_multi_xfer_timeout_handler(struct device * dev,struct geni_i2c_gpi_multi_desc_xfer * multi_xfer,u32 transfer_timeout_msecs,struct completion * transfer_comp)644 static int geni_i2c_gpi_multi_xfer_timeout_handler(struct device *dev,
645 struct geni_i2c_gpi_multi_desc_xfer *multi_xfer,
646 u32 transfer_timeout_msecs,
647 struct completion *transfer_comp)
648 {
649 int i;
650 u32 time_left;
651
652 for (i = 0; i < multi_xfer->msg_idx_cnt - 1; i++) {
653 reinit_completion(transfer_comp);
654
655 if (multi_xfer->msg_idx_cnt != multi_xfer->irq_cnt) {
656 time_left = wait_for_completion_timeout(transfer_comp,
657 transfer_timeout_msecs);
658 if (!time_left) {
659 dev_err(dev, "%s: Transfer timeout\n", __func__);
660 return -ETIMEDOUT;
661 }
662 }
663 }
664 return 0;
665 }
666
geni_i2c_gpi(struct geni_i2c_dev * gi2c,struct i2c_msg msgs[],struct dma_slave_config * config,dma_addr_t * dma_addr_p,void ** buf,unsigned int op,struct dma_chan * dma_chan)667 static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[],
668 struct dma_slave_config *config, dma_addr_t *dma_addr_p,
669 void **buf, unsigned int op, struct dma_chan *dma_chan)
670 {
671 struct gpi_i2c_config *peripheral;
672 unsigned int flags;
673 void *dma_buf = NULL;
674 dma_addr_t addr = 0;
675 enum dma_data_direction map_dirn;
676 enum dma_transfer_direction dma_dirn;
677 struct dma_async_tx_descriptor *desc;
678 int ret;
679 struct geni_i2c_gpi_multi_desc_xfer *gi2c_gpi_xfer;
680 dma_cookie_t cookie;
681 u32 msg_idx;
682
683 peripheral = config->peripheral_config;
684 gi2c_gpi_xfer = &gi2c->i2c_multi_desc_config;
685 msg_idx = gi2c_gpi_xfer->msg_idx_cnt;
686
687 /*
688 * Skip TX DMA mapping for a read message (I2C_M_RD) to avoid
689 * programming an extra TX DMA TRE that would cause an unintended
690 * write cycle on the I2C bus before the actual read operation.
691 */
692 if (op == I2C_WRITE && msgs[msg_idx].flags & I2C_M_RD) {
693 peripheral->multi_msg = true;
694 goto skip_tx_dma_map;
695 }
696
697 dma_buf = i2c_get_dma_safe_msg_buf(&msgs[msg_idx], 1);
698 if (!dma_buf) {
699 ret = -ENOMEM;
700 goto out;
701 }
702
703 if (op == I2C_WRITE)
704 map_dirn = DMA_TO_DEVICE;
705 else
706 map_dirn = DMA_FROM_DEVICE;
707
708 addr = dma_map_single(gi2c->se.dev->parent, dma_buf,
709 msgs[msg_idx].len, map_dirn);
710 if (dma_mapping_error(gi2c->se.dev->parent, addr)) {
711 i2c_put_dma_safe_msg_buf(dma_buf, &msgs[msg_idx], false);
712 ret = -ENOMEM;
713 goto out;
714 }
715
716 skip_tx_dma_map:
717 if (gi2c->is_tx_multi_desc_xfer) {
718 flags = DMA_CTRL_ACK;
719
720 /* BEI bit to be cleared for last TRE */
721 if (msg_idx == gi2c->num_msgs - 1)
722 flags |= DMA_PREP_INTERRUPT;
723 } else {
724 flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
725 }
726
727 /* set the length as message for rx txn */
728 peripheral->rx_len = msgs[msg_idx].len;
729 peripheral->op = op;
730
731 ret = dmaengine_slave_config(dma_chan, config);
732 if (ret) {
733 dev_err(gi2c->se.dev, "dma config error: %d for op:%d\n", ret, op);
734 goto err_config;
735 }
736
737 peripheral->set_config = 0;
738 peripheral->multi_msg = true;
739
740 if (op == I2C_WRITE)
741 dma_dirn = DMA_MEM_TO_DEV;
742 else
743 dma_dirn = DMA_DEV_TO_MEM;
744
745 desc = dmaengine_prep_slave_single(dma_chan, addr, msgs[msg_idx].len,
746 dma_dirn, flags);
747 if (!desc && !(flags & DMA_PREP_INTERRUPT)) {
748 /* Retry with interrupt if not enough TREs */
749 flags |= DMA_PREP_INTERRUPT;
750 desc = dmaengine_prep_slave_single(dma_chan, addr, msgs[msg_idx].len,
751 dma_dirn, flags);
752 }
753
754 if (!desc) {
755 dev_err(gi2c->se.dev, "prep_slave_sg failed\n");
756 ret = -EIO;
757 goto err_config;
758 }
759
760 desc->callback_result = i2c_gpi_cb_result;
761 desc->callback_param = gi2c;
762
763 if (!((msgs[msg_idx].flags & I2C_M_RD) && op == I2C_WRITE))
764 gi2c_gpi_xfer->msg_idx_cnt++;
765
766 cookie = dmaengine_submit(desc);
767 if (dma_submit_error(cookie)) {
768 dev_err(gi2c->se.dev,
769 "%s: dmaengine_submit failed (%d)\n", __func__, cookie);
770 ret = -EINVAL;
771 goto err_config;
772 }
773
774 if (gi2c->is_tx_multi_desc_xfer) {
775 gi2c_gpi_xfer->dma_buf[msg_idx] = dma_buf;
776 gi2c_gpi_xfer->dma_addr[msg_idx] = addr;
777
778 dma_async_issue_pending(gi2c->tx_c);
779
780 if ((msg_idx == (gi2c->num_msgs - 1)) || flags & DMA_PREP_INTERRUPT) {
781 ret = geni_i2c_gpi_multi_xfer_timeout_handler(gi2c->se.dev, gi2c_gpi_xfer,
782 XFER_TIMEOUT, &gi2c->done);
783 if (ret) {
784 dev_err(gi2c->se.dev,
785 "I2C multi write msg transfer timeout: %d\n",
786 ret);
787 gi2c->err = ret;
788 return ret;
789 }
790 }
791 } else {
792 /* Non multi descriptor message transfer */
793 *buf = dma_buf;
794 *dma_addr_p = addr;
795 }
796 return 0;
797
798 err_config:
799 /* Avoid DMA unmap as the write operation skipped DMA mapping */
800 if (dma_buf) {
801 dma_unmap_single(gi2c->se.dev->parent, addr,
802 msgs[msg_idx].len, map_dirn);
803 i2c_put_dma_safe_msg_buf(dma_buf, &msgs[msg_idx], false);
804 }
805
806 out:
807 gi2c->err = ret;
808 return ret;
809 }
810
geni_i2c_gpi_xfer(struct geni_i2c_dev * gi2c,struct i2c_msg msgs[],int num)811 static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], int num)
812 {
813 struct dma_slave_config config = {};
814 struct gpi_i2c_config peripheral = {};
815 int i, ret = 0;
816 unsigned long time_left;
817 dma_addr_t tx_addr, rx_addr;
818 void *tx_buf = NULL, *rx_buf = NULL;
819 struct geni_i2c_gpi_multi_desc_xfer *tx_multi_xfer;
820 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
821
822 config.peripheral_config = &peripheral;
823 config.peripheral_size = sizeof(peripheral);
824
825 peripheral.pack_enable = I2C_PACK_TX | I2C_PACK_RX;
826 peripheral.cycle_count = itr->t_cycle_cnt;
827 peripheral.high_count = itr->t_high_cnt;
828 peripheral.low_count = itr->t_low_cnt;
829 peripheral.clk_div = itr->clk_div;
830 peripheral.set_config = 1;
831 peripheral.multi_msg = false;
832
833 trace_geni_i2c_bus_setup(gi2c->se.dev, gi2c->clk_freq_out,
834 itr->clk_div, itr->t_high_cnt,
835 itr->t_low_cnt, itr->t_cycle_cnt);
836
837 gi2c->num_msgs = num;
838 gi2c->is_tx_multi_desc_xfer = false;
839
840 tx_multi_xfer = &gi2c->i2c_multi_desc_config;
841 memset(tx_multi_xfer, 0, sizeof(struct geni_i2c_gpi_multi_desc_xfer));
842
843 /*
844 * If number of write messages are two and higher then
845 * configure hardware for multi descriptor transfers with BEI.
846 */
847 if (num >= QCOM_I2C_MIN_NUM_OF_MSGS_MULTI_DESC) {
848 gi2c->is_tx_multi_desc_xfer = true;
849 for (i = 0; i < num; i++) {
850 if (msgs[i].flags & I2C_M_RD) {
851 /*
852 * Multi descriptor transfer with BEI
853 * support is enabled for write transfers.
854 * TODO: Add BEI optimization support for
855 * read transfers later.
856 */
857 gi2c->is_tx_multi_desc_xfer = false;
858 break;
859 }
860 }
861 }
862
863 if (gi2c->is_tx_multi_desc_xfer) {
864 tx_multi_xfer->dma_buf = kcalloc(num, sizeof(void *), GFP_KERNEL);
865 tx_multi_xfer->dma_addr = kzalloc_objs(dma_addr_t, num);
866 if (!tx_multi_xfer->dma_buf || !tx_multi_xfer->dma_addr) {
867 ret = -ENOMEM;
868 goto err;
869 }
870 }
871
872 for (i = 0; i < num; i++) {
873 gi2c->cur = &msgs[i];
874 gi2c->err = 0;
875 reinit_completion(&gi2c->done);
876 dev_dbg(gi2c->se.dev, "msg[%d].len:%d\n", i, gi2c->cur->len);
877
878 peripheral.stretch = 0;
879 if (i < num - 1)
880 peripheral.stretch = 1;
881
882 peripheral.addr = msgs[i].addr;
883 if (i > 0 && (!(msgs[i].flags & I2C_M_RD)))
884 peripheral.multi_msg = false;
885
886 ret = geni_i2c_gpi(gi2c, msgs, &config,
887 &tx_addr, &tx_buf, I2C_WRITE, gi2c->tx_c);
888 if (ret)
889 goto err;
890
891 if (msgs[i].flags & I2C_M_RD) {
892 ret = geni_i2c_gpi(gi2c, msgs, &config,
893 &rx_addr, &rx_buf, I2C_READ, gi2c->rx_c);
894 if (ret)
895 goto err;
896
897 dma_async_issue_pending(gi2c->rx_c);
898 }
899
900 if (!gi2c->is_tx_multi_desc_xfer) {
901 dma_async_issue_pending(gi2c->tx_c);
902 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
903 if (!time_left) {
904 dev_err(gi2c->se.dev, "%s:I2C timeout\n", __func__);
905 gi2c->err = -ETIMEDOUT;
906 }
907 }
908
909 if (gi2c->err) {
910 ret = gi2c->err;
911 goto err;
912 }
913
914 if (!gi2c->is_tx_multi_desc_xfer)
915 geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr);
916 else if (tx_multi_xfer->unmap_msg_cnt != tx_multi_xfer->irq_cnt)
917 geni_i2c_gpi_multi_desc_unmap(gi2c, msgs, &peripheral);
918 }
919
920 return num;
921
922 err:
923 dev_err(gi2c->se.dev, "GPI transfer failed: %d\n", ret);
924 dmaengine_terminate_sync(gi2c->rx_c);
925 dmaengine_terminate_sync(gi2c->tx_c);
926 if (gi2c->is_tx_multi_desc_xfer)
927 geni_i2c_gpi_multi_desc_unmap(gi2c, msgs, &peripheral);
928 else
929 geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr);
930
931 return ret;
932 }
933
geni_i2c_fifo_xfer(struct geni_i2c_dev * gi2c,struct i2c_msg msgs[],int num)934 static int geni_i2c_fifo_xfer(struct geni_i2c_dev *gi2c,
935 struct i2c_msg msgs[], int num)
936 {
937 int i, ret = 0;
938
939 for (i = 0; i < num; i++) {
940 u32 m_param = i < (num - 1) ? STOP_STRETCH : 0;
941
942 m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK);
943
944 gi2c->cur = &msgs[i];
945 gi2c->err = 0;
946 reinit_completion(&gi2c->done);
947 if (msgs[i].flags & I2C_M_RD)
948 ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param);
949 else
950 ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param);
951
952 if (ret)
953 return ret;
954 }
955
956 return num;
957 }
958
geni_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)959 static int geni_i2c_xfer(struct i2c_adapter *adap,
960 struct i2c_msg msgs[],
961 int num)
962 {
963 struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap);
964 int ret;
965
966 ret = pm_runtime_get_sync(gi2c->se.dev);
967 if (ret < 0) {
968 dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret);
969 pm_runtime_put_noidle(gi2c->se.dev);
970 /* Set device in suspended since resume failed */
971 pm_runtime_set_suspended(gi2c->se.dev);
972 return ret;
973 }
974
975 ret = gi2c->dev_data->set_rate(&gi2c->se, gi2c->clk_freq_out);
976 if (ret)
977 return ret;
978
979 if (gi2c->gpi_mode)
980 ret = geni_i2c_gpi_xfer(gi2c, msgs, num);
981 else
982 ret = geni_i2c_fifo_xfer(gi2c, msgs, num);
983
984 pm_runtime_put_autosuspend(gi2c->se.dev);
985 gi2c->cur = NULL;
986 gi2c->err = 0;
987 return ret;
988 }
989
geni_i2c_func(struct i2c_adapter * adap)990 static u32 geni_i2c_func(struct i2c_adapter *adap)
991 {
992 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
993 }
994
995 static const struct i2c_algorithm geni_i2c_algo = {
996 .xfer = geni_i2c_xfer,
997 .functionality = geni_i2c_func,
998 };
999
release_gpi_dma(struct geni_i2c_dev * gi2c)1000 static void release_gpi_dma(struct geni_i2c_dev *gi2c)
1001 {
1002 if (gi2c->rx_c)
1003 dma_release_channel(gi2c->rx_c);
1004
1005 if (gi2c->tx_c)
1006 dma_release_channel(gi2c->tx_c);
1007 }
1008
setup_gpi_dma(struct geni_i2c_dev * gi2c)1009 static int setup_gpi_dma(struct geni_i2c_dev *gi2c)
1010 {
1011 int ret;
1012
1013 geni_se_select_mode(&gi2c->se, GENI_GPI_DMA);
1014 gi2c->tx_c = dma_request_chan(gi2c->se.dev, "tx");
1015 if (IS_ERR(gi2c->tx_c)) {
1016 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->tx_c),
1017 "Failed to get tx DMA ch\n");
1018 goto err_tx;
1019 }
1020
1021 gi2c->rx_c = dma_request_chan(gi2c->se.dev, "rx");
1022 if (IS_ERR(gi2c->rx_c)) {
1023 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->rx_c),
1024 "Failed to get rx DMA ch\n");
1025 goto err_rx;
1026 }
1027
1028 dev_dbg(gi2c->se.dev, "Grabbed GPI dma channels\n");
1029 return 0;
1030
1031 err_rx:
1032 dma_release_channel(gi2c->tx_c);
1033 err_tx:
1034 return ret;
1035 }
1036
geni_i2c_init(struct geni_i2c_dev * gi2c)1037 static int geni_i2c_init(struct geni_i2c_dev *gi2c)
1038 {
1039 u32 proto, tx_depth;
1040 bool fifo_disable;
1041 int ret;
1042
1043 ret = pm_runtime_resume_and_get(gi2c->se.dev);
1044 if (ret < 0) {
1045 dev_err(gi2c->se.dev, "error turning on device :%d\n", ret);
1046 return ret;
1047 }
1048
1049 proto = geni_se_read_proto(&gi2c->se);
1050 if (proto == GENI_SE_INVALID_PROTO) {
1051 ret = geni_load_se_firmware(&gi2c->se, GENI_SE_I2C);
1052 if (ret) {
1053 dev_err_probe(gi2c->se.dev, ret, "i2c firmware load failed ret: %d\n", ret);
1054 goto err;
1055 }
1056 } else if (proto != GENI_SE_I2C) {
1057 ret = dev_err_probe(gi2c->se.dev, -ENXIO, "Invalid proto %d\n", proto);
1058 goto err;
1059 }
1060
1061 if (gi2c->dev_data->no_dma_support) {
1062 fifo_disable = false;
1063 gi2c->no_dma = true;
1064 } else {
1065 fifo_disable = readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;
1066 }
1067
1068 if (fifo_disable) {
1069 /* FIFO is disabled, so we can only use GPI DMA */
1070 gi2c->gpi_mode = true;
1071 ret = setup_gpi_dma(gi2c);
1072 if (ret)
1073 goto err;
1074
1075 dev_dbg(gi2c->se.dev, "Using GPI DMA mode for I2C\n");
1076 } else {
1077 gi2c->gpi_mode = false;
1078 tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se);
1079
1080 /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */
1081 if (!tx_depth && gi2c->se.core_clk)
1082 tx_depth = gi2c->dev_data->tx_fifo_depth;
1083
1084 if (!tx_depth) {
1085 ret = dev_err_probe(gi2c->se.dev, -EINVAL,
1086 "Invalid TX FIFO depth\n");
1087 goto err;
1088 }
1089
1090 gi2c->tx_wm = tx_depth - 1;
1091 geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth);
1092 geni_se_config_packing(&gi2c->se, BITS_PER_BYTE,
1093 PACKING_BYTES_PW, true, true, true);
1094
1095 dev_dbg(gi2c->se.dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth);
1096 }
1097
1098 err:
1099 pm_runtime_put(gi2c->se.dev);
1100 return ret;
1101 }
1102
geni_i2c_resources_init(struct geni_se * se)1103 static int geni_i2c_resources_init(struct geni_se *se)
1104 {
1105 struct geni_i2c_dev *gi2c = dev_get_drvdata(se->dev);
1106 int ret;
1107
1108 ret = geni_se_resources_init(&gi2c->se);
1109 if (ret)
1110 return ret;
1111
1112 ret = geni_i2c_clk_map_idx(gi2c);
1113 if (ret)
1114 return dev_err_probe(gi2c->se.dev, ret, "Invalid clk frequency %d Hz\n",
1115 gi2c->clk_freq_out);
1116
1117 return geni_icc_set_bw_ab(&gi2c->se, GENI_DEFAULT_BW, GENI_DEFAULT_BW,
1118 Bps_to_icc(gi2c->clk_freq_out));
1119 }
1120
geni_i2c_probe(struct platform_device * pdev)1121 static int geni_i2c_probe(struct platform_device *pdev)
1122 {
1123 struct geni_i2c_dev *gi2c;
1124 int ret;
1125 struct device *dev = &pdev->dev;
1126
1127 gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL);
1128 if (!gi2c)
1129 return -ENOMEM;
1130
1131 gi2c->se.dev = dev;
1132 gi2c->se.wrapper = dev_get_drvdata(dev->parent);
1133 gi2c->se.base = devm_platform_ioremap_resource(pdev, 0);
1134 if (IS_ERR(gi2c->se.base))
1135 return PTR_ERR(gi2c->se.base);
1136
1137 gi2c->dev_data = device_get_match_data(&pdev->dev);
1138 if (!gi2c->dev_data)
1139 return -EINVAL;
1140
1141 ret = device_property_read_u32(dev, "clock-frequency",
1142 &gi2c->clk_freq_out);
1143 if (ret) {
1144 dev_info(dev, "Bus frequency not specified, default to 100kHz.\n");
1145 gi2c->clk_freq_out = I2C_MAX_STANDARD_MODE_FREQ;
1146 }
1147
1148 if (has_acpi_companion(dev))
1149 ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev));
1150
1151 gi2c->irq = platform_get_irq(pdev, 0);
1152 if (gi2c->irq < 0)
1153 return gi2c->irq;
1154
1155 gi2c->adap.algo = &geni_i2c_algo;
1156 init_completion(&gi2c->done);
1157 init_completion(&gi2c->abort_done);
1158 init_completion(&gi2c->cancel_done);
1159 init_completion(&gi2c->tx_reset_done);
1160 init_completion(&gi2c->rx_reset_done);
1161 spin_lock_init(&gi2c->lock);
1162 platform_set_drvdata(pdev, gi2c);
1163
1164 ret = gi2c->dev_data->resources_init(&gi2c->se);
1165 if (ret)
1166 return ret;
1167
1168 /* Keep interrupts disabled initially to allow for low-power modes */
1169 ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, IRQF_NO_AUTOEN,
1170 dev_name(dev), gi2c);
1171 if (ret)
1172 return ret;
1173
1174 i2c_set_adapdata(&gi2c->adap, gi2c);
1175 gi2c->adap.dev.parent = dev;
1176 gi2c->adap.dev.of_node = dev->of_node;
1177 strscpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
1178
1179 pm_runtime_set_suspended(dev);
1180 pm_runtime_set_autosuspend_delay(dev, I2C_AUTO_SUSPEND_DELAY);
1181 pm_runtime_use_autosuspend(dev);
1182
1183 ret = devm_pm_runtime_enable(dev);
1184 if (ret)
1185 return ret;
1186
1187 ret = geni_i2c_init(gi2c);
1188 if (ret < 0)
1189 return ret;
1190
1191 ret = i2c_add_adapter(&gi2c->adap);
1192 if (ret)
1193 return dev_err_probe(dev, ret, "Error adding i2c adapter\n");
1194
1195 dev_dbg(dev, "Geni-I2C adaptor successfully added\n");
1196
1197 return 0;
1198 }
1199
geni_i2c_remove(struct platform_device * pdev)1200 static void geni_i2c_remove(struct platform_device *pdev)
1201 {
1202 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
1203
1204 i2c_del_adapter(&gi2c->adap);
1205 release_gpi_dma(gi2c);
1206 }
1207
geni_i2c_shutdown(struct platform_device * pdev)1208 static void geni_i2c_shutdown(struct platform_device *pdev)
1209 {
1210 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
1211
1212 /* Make client i2c transfers start failing */
1213 i2c_mark_adapter_suspended(&gi2c->adap);
1214 }
1215
geni_i2c_runtime_suspend(struct device * dev)1216 static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
1217 {
1218 int ret = 0;
1219 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
1220
1221 disable_irq(gi2c->irq);
1222
1223 if (gi2c->dev_data->power_off) {
1224 ret = gi2c->dev_data->power_off(&gi2c->se);
1225 if (ret) {
1226 enable_irq(gi2c->irq);
1227 return ret;
1228 }
1229 }
1230
1231 return 0;
1232 }
1233
geni_i2c_runtime_resume(struct device * dev)1234 static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
1235 {
1236 int ret = 0;
1237 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
1238
1239 if (gi2c->dev_data->power_on) {
1240 ret = gi2c->dev_data->power_on(&gi2c->se);
1241 if (ret)
1242 return ret;
1243 }
1244
1245 enable_irq(gi2c->irq);
1246
1247 return 0;
1248 }
1249
geni_i2c_suspend_noirq(struct device * dev)1250 static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev)
1251 {
1252 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
1253 int ret;
1254
1255 i2c_mark_adapter_suspended(&gi2c->adap);
1256
1257 ret = pm_runtime_force_suspend(dev);
1258 if (ret)
1259 i2c_mark_adapter_resumed(&gi2c->adap);
1260
1261 return ret;
1262 }
1263
geni_i2c_resume_noirq(struct device * dev)1264 static int __maybe_unused geni_i2c_resume_noirq(struct device *dev)
1265 {
1266 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
1267 int ret;
1268
1269 ret = pm_runtime_force_resume(dev);
1270 if (ret)
1271 return ret;
1272
1273 i2c_mark_adapter_resumed(&gi2c->adap);
1274 return 0;
1275 }
1276
1277 static const struct dev_pm_ops geni_i2c_pm_ops = {
1278 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, geni_i2c_resume_noirq)
1279 SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume,
1280 NULL)
1281 };
1282
1283 static const struct geni_i2c_desc geni_i2c = {
1284 .resources_init = geni_i2c_resources_init,
1285 .set_rate = qcom_geni_i2c_conf,
1286 .power_on = geni_se_resources_activate,
1287 .power_off = geni_se_resources_deactivate,
1288 };
1289
1290 static const struct geni_i2c_desc i2c_master_hub = {
1291 .no_dma_support = true,
1292 .tx_fifo_depth = 16,
1293 .resources_init = geni_i2c_resources_init,
1294 .set_rate = qcom_geni_i2c_conf,
1295 .power_on = geni_se_resources_activate,
1296 .power_off = geni_se_resources_deactivate,
1297 };
1298
1299 static const struct geni_i2c_desc sa8255p_geni_i2c = {
1300 .resources_init = geni_se_domain_attach,
1301 .set_rate = geni_se_set_perf_opp,
1302 };
1303
1304 #ifdef CONFIG_ACPI
1305 static const struct acpi_device_id geni_i2c_acpi_match[] = {
1306 { "QCOM0220", (kernel_ulong_t)&geni_i2c},
1307 { "QCOM0411", (kernel_ulong_t)&geni_i2c},
1308 { }
1309 };
1310 MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match);
1311 #endif
1312
1313 static const struct of_device_id geni_i2c_dt_match[] = {
1314 { .compatible = "qcom,geni-i2c", .data = &geni_i2c },
1315 { .compatible = "qcom,geni-i2c-master-hub", .data = &i2c_master_hub },
1316 { .compatible = "qcom,sa8255p-geni-i2c", .data = &sa8255p_geni_i2c },
1317 {}
1318 };
1319 MODULE_DEVICE_TABLE(of, geni_i2c_dt_match);
1320
1321 static struct platform_driver geni_i2c_driver = {
1322 .probe = geni_i2c_probe,
1323 .remove = geni_i2c_remove,
1324 .shutdown = geni_i2c_shutdown,
1325 .driver = {
1326 .name = "geni_i2c",
1327 .pm = &geni_i2c_pm_ops,
1328 .of_match_table = geni_i2c_dt_match,
1329 .acpi_match_table = ACPI_PTR(geni_i2c_acpi_match),
1330 },
1331 };
1332
1333 module_platform_driver(geni_i2c_driver);
1334
1335 MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores");
1336 MODULE_LICENSE("GPL v2");
1337