1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2025 Broadcom */
3
4 #ifndef _BNGE_H_
5 #define _BNGE_H_
6
7 #define DRV_NAME "bng_en"
8 #define DRV_SUMMARY "Broadcom ThorUltra NIC Ethernet Driver"
9
10 #include <linux/etherdevice.h>
11 #include <linux/bnge/hsi.h>
12 #include "bnge_rmem.h"
13 #include "bnge_resc.h"
14 #include "bnge_auxr.h"
15
16 #define DRV_VER_MAJ 1
17 #define DRV_VER_MIN 15
18 #define DRV_VER_UPD 1
19
20 extern char bnge_driver_name[];
21
22 enum board_idx {
23 BCM57708,
24 };
25
26 struct bnge_auxr_priv {
27 struct auxiliary_device aux_dev;
28 struct bnge_auxr_dev *auxr_dev;
29 int id;
30 };
31
32 struct bnge_pf_info {
33 u16 fw_fid;
34 u16 port_id;
35 u8 mac_addr[ETH_ALEN];
36 };
37
38 #define INVALID_HW_RING_ID ((u16)-1)
39 #define INVALID_HW_RING_ID_32BIT (U32_MAX)
40
41 enum {
42 BNGE_FW_CAP_SHORT_CMD = BIT_ULL(0),
43 BNGE_FW_CAP_LLDP_AGENT = BIT_ULL(1),
44 BNGE_FW_CAP_DCBX_AGENT = BIT_ULL(2),
45 BNGE_FW_CAP_IF_CHANGE = BIT_ULL(3),
46 BNGE_FW_CAP_KONG_MB_CHNL = BIT_ULL(4),
47 BNGE_FW_CAP_ERROR_RECOVERY = BIT_ULL(5),
48 BNGE_FW_CAP_PKG_VER = BIT_ULL(6),
49 BNGE_FW_CAP_CFA_ADV_FLOW = BIT_ULL(7),
50 BNGE_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 = BIT_ULL(8),
51 BNGE_FW_CAP_PCIE_STATS_SUPPORTED = BIT_ULL(9),
52 BNGE_FW_CAP_EXT_STATS_SUPPORTED = BIT_ULL(10),
53 BNGE_FW_CAP_ERR_RECOVER_RELOAD = BIT_ULL(11),
54 BNGE_FW_CAP_HOT_RESET = BIT_ULL(12),
55 BNGE_FW_CAP_RX_ALL_PKT_TS = BIT_ULL(13),
56 BNGE_FW_CAP_VLAN_RX_STRIP = BIT_ULL(14),
57 BNGE_FW_CAP_VLAN_TX_INSERT = BIT_ULL(15),
58 BNGE_FW_CAP_EXT_HW_STATS_SUPPORTED = BIT_ULL(16),
59 BNGE_FW_CAP_LIVEPATCH = BIT_ULL(17),
60 BNGE_FW_CAP_HOT_RESET_IF = BIT_ULL(18),
61 BNGE_FW_CAP_RING_MONITOR = BIT_ULL(19),
62 BNGE_FW_CAP_DBG_QCAPS = BIT_ULL(20),
63 BNGE_FW_CAP_THRESHOLD_TEMP_SUPPORTED = BIT_ULL(21),
64 BNGE_FW_CAP_DFLT_VLAN_TPID_PCP = BIT_ULL(22),
65 BNGE_FW_CAP_VNIC_TUNNEL_TPA = BIT_ULL(23),
66 BNGE_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO = BIT_ULL(24),
67 BNGE_FW_CAP_CFA_RFS_RING_TBL_IDX_V3 = BIT_ULL(25),
68 BNGE_FW_CAP_VNIC_RE_FLUSH = BIT_ULL(26),
69 };
70
71 enum {
72 BNGE_EN_ROCE_V1 = BIT_ULL(0),
73 BNGE_EN_ROCE_V2 = BIT_ULL(1),
74 BNGE_EN_STRIP_VLAN = BIT_ULL(2),
75 BNGE_EN_SHARED_CHNL = BIT_ULL(3),
76 BNGE_EN_UDP_GSO_SUPP = BIT_ULL(4),
77 };
78
79 #define BNGE_EN_ROCE (BNGE_EN_ROCE_V1 | BNGE_EN_ROCE_V2)
80
81 enum {
82 BNGE_RSS_CAP_RSS_HASH_TYPE_DELTA = BIT(0),
83 BNGE_RSS_CAP_UDP_RSS_CAP = BIT(1),
84 BNGE_RSS_CAP_NEW_RSS_CAP = BIT(2),
85 BNGE_RSS_CAP_RSS_TCAM = BIT(3),
86 BNGE_RSS_CAP_AH_V4_RSS_CAP = BIT(4),
87 BNGE_RSS_CAP_AH_V6_RSS_CAP = BIT(5),
88 BNGE_RSS_CAP_ESP_V4_RSS_CAP = BIT(6),
89 BNGE_RSS_CAP_ESP_V6_RSS_CAP = BIT(7),
90 };
91
92 #define BNGE_MAX_QUEUE 8
93 struct bnge_queue_info {
94 u8 queue_id;
95 u8 queue_profile;
96 };
97
98 #define BNGE_PHY_FLAGS2_SHIFT 8
99 #define BNGE_PHY_FL_NO_FCS PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS
100 #define BNGE_PHY_FL_NO_PAUSE \
101 (PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED << 8)
102
103 struct bnge_dev {
104 struct device *dev;
105 struct pci_dev *pdev;
106 struct net_device *netdev;
107 u64 dsn;
108 #define BNGE_VPD_FLD_LEN 32
109 char board_partno[BNGE_VPD_FLD_LEN];
110 char board_serialno[BNGE_VPD_FLD_LEN];
111
112 void __iomem *bar0;
113 void __iomem *bar1;
114
115 u16 chip_num;
116 u8 chip_rev;
117
118 #if BITS_PER_LONG == 32
119 /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
120 spinlock_t db_lock;
121 #endif
122 int db_offset; /* db_offset within db_size */
123 int db_size;
124
125 /* HWRM members */
126 u16 hwrm_cmd_seq;
127 u16 hwrm_cmd_kong_seq;
128 struct dma_pool *hwrm_dma_pool;
129 struct hlist_head hwrm_pending_list;
130 u16 hwrm_max_req_len;
131 u16 hwrm_max_ext_req_len;
132 unsigned int hwrm_cmd_timeout;
133 unsigned int hwrm_cmd_max_timeout;
134 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
135
136 struct hwrm_ver_get_output ver_resp;
137 #define FW_VER_STR_LEN 32
138 char fw_ver_str[FW_VER_STR_LEN];
139 char hwrm_ver_supp[FW_VER_STR_LEN];
140 char nvm_cfg_ver[FW_VER_STR_LEN];
141 u64 fw_ver_code;
142 #define BNGE_FW_VER_CODE(maj, min, bld, rsv) \
143 ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))
144
145 struct bnge_pf_info pf;
146
147 unsigned long state;
148 #define BNGE_STATE_DRV_REGISTERED 0
149 #define BNGE_STATE_OPEN 1
150
151 u64 fw_cap;
152
153 /* Backing stores */
154 struct bnge_ctx_mem_info *ctx;
155
156 u64 flags;
157
158 struct bnge_hw_resc hw_resc;
159
160 u16 tso_max_segs;
161
162 int max_fltr;
163 #define BNGE_L2_FLTR_MAX_FLTR 1024
164
165 u32 *rss_indir_tbl;
166 #define BNGE_RSS_TABLE_ENTRIES 64
167 #define BNGE_RSS_TABLE_SIZE (BNGE_RSS_TABLE_ENTRIES * 4)
168 #define BNGE_RSS_TABLE_MAX_TBL 8
169 #define BNGE_MAX_RSS_TABLE_SIZE \
170 (BNGE_RSS_TABLE_SIZE * BNGE_RSS_TABLE_MAX_TBL)
171 #define BNGE_MAX_RSS_TABLE_ENTRIES \
172 (BNGE_RSS_TABLE_ENTRIES * BNGE_RSS_TABLE_MAX_TBL)
173 u16 rss_indir_tbl_entries;
174
175 u32 rss_cap;
176 u32 rss_hash_cfg;
177
178 u16 rx_nr_rings;
179 u16 tx_nr_rings;
180 u16 tx_nr_rings_per_tc;
181 /* Number of NQs */
182 u16 nq_nr_rings;
183
184 /* Aux device resources */
185 u16 aux_num_msix;
186 u16 aux_num_stat_ctxs;
187
188 u16 max_mtu;
189 #define BNGE_MAX_MTU 9500
190
191 u16 hw_ring_stats_size;
192 #define BNGE_NUM_RX_RING_STATS 8
193 #define BNGE_NUM_TX_RING_STATS 8
194 #define BNGE_NUM_TPA_RING_STATS 6
195 #define BNGE_RING_STATS_SIZE \
196 ((BNGE_NUM_RX_RING_STATS + BNGE_NUM_TX_RING_STATS + \
197 BNGE_NUM_TPA_RING_STATS) * 8)
198
199 u16 max_tpa_v2;
200 #define BNGE_SUPPORTS_TPA(bd) ((bd)->max_tpa_v2)
201
202 u8 num_tc;
203 u8 max_tc;
204 u8 max_lltc; /* lossless TCs */
205 struct bnge_queue_info q_info[BNGE_MAX_QUEUE];
206 u8 tc_to_qidx[BNGE_MAX_QUEUE];
207 u8 q_ids[BNGE_MAX_QUEUE];
208 u8 max_q;
209 u8 port_count;
210
211 struct bnge_irq *irq_tbl;
212 u16 irqs_acquired;
213
214 struct bnge_auxr_priv *aux_priv;
215 struct bnge_auxr_dev *auxr_dev;
216
217 struct bnge_link_info link_info;
218
219 /* Copied from flags and flags2 in hwrm_port_phy_qcaps_output */
220 u32 phy_flags;
221 };
222
bnge_is_roce_en(struct bnge_dev * bd)223 static inline bool bnge_is_roce_en(struct bnge_dev *bd)
224 {
225 return bd->flags & BNGE_EN_ROCE;
226 }
227
bnge_is_agg_reqd(struct bnge_dev * bd)228 static inline bool bnge_is_agg_reqd(struct bnge_dev *bd)
229 {
230 if (bd->netdev) {
231 struct bnge_net *bn = netdev_priv(bd->netdev);
232
233 if (bn->priv_flags & BNGE_NET_EN_TPA ||
234 bn->priv_flags & BNGE_NET_EN_JUMBO)
235 return true;
236 else
237 return false;
238 }
239
240 return true;
241 }
242
bnge_writeq(struct bnge_dev * bd,u64 val,void __iomem * addr)243 static inline void bnge_writeq(struct bnge_dev *bd, u64 val,
244 void __iomem *addr)
245 {
246 #if BITS_PER_LONG == 32
247 spin_lock(&bd->db_lock);
248 lo_hi_writeq(val, addr);
249 spin_unlock(&bd->db_lock);
250 #else
251 writeq(val, addr);
252 #endif
253 }
254
255 /* For TX and RX ring doorbells */
bnge_db_write(struct bnge_dev * bd,struct bnge_db_info * db,u32 idx)256 static inline void bnge_db_write(struct bnge_dev *bd, struct bnge_db_info *db,
257 u32 idx)
258 {
259 bnge_writeq(bd, db->db_key64 | DB_RING_IDX(db, idx),
260 db->doorbell);
261 }
262
263 bool bnge_aux_registered(struct bnge_dev *bd);
264 u16 bnge_aux_get_msix(struct bnge_dev *bd);
265
266 #endif /* _BNGE_H_ */
267