Searched refs:BIT_1 (Results 1 – 25 of 28) sorted by relevance
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30 #define PDO_FORCE_ADISC BIT_145 #define PDF_HARD_ADDR BIT_1457 #define BD_READ_DATA BIT_1498 #define CF_READ_DATA BIT_1540 #define TMF_READ_DATA BIT_1974 #define TCF_TARGET_RESET BIT_11001 #define AOF_NO_RRQ BIT_1 /* Do not send RRQ. */1195 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */1265 #define GPDX_DATA_INOUT (BIT_1|BIT_0)1273 #define GPEX_ENABLE (BIT_1|BIT_0)[all …]
20 #define EDIF_SA_CTL_FLG_DEL BIT_180 #define SA_FLAG_TX BIT_1 // 1=tx, 0=rx
226 #define ATIO_EXEC_READ BIT_1423 #define EF_NEW_SA BIT_1484 #define CTIO7_FLAGS_DATA_IN BIT_1 /* data to initiator */853 TRC_DO_WORK = BIT_1,1001 #define QLA24XX_MGMT_ABORT_IO_ATTR_VALID BIT_1
65 #define CF_READ_DATA BIT_1
61 #define CAPTURE_FLAG_PHYS_VIRT BIT_1
884 options |= BIT_1; in qla25xx_create_rsp_que()
2150 else if (le16_to_cpu(mbx->mb1) & BIT_1) in qla2x00_mbx_iocb_entry()3398 if (unlikely((state_flags & BIT_1) && (sp->type == SRB_BIDI_CMD))) { in qla2x00_status_entry()
6174 else if (sfp[0] & BIT_1) in qla24xx_process_purex_rdp()6175 sfp_flags |= BIT_1; /* long wave 1310nm */ in qla24xx_process_purex_rdp()6177 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */ in qla24xx_process_purex_rdp()
2879 if ((cmd_sts_and_cntrl & BIT_1) == 0) in qla8044_start_pex_dma()
1007 (rd_reg_word(®->mctr) & (BIT_1 | BIT_0)) != 0))) { in qla2100_fw_dump()
18 #define BIT_1 0x2 macro134 #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */141 #define PCI_INT BIT_1 /* PCI interrupt */146 #define NV_SELECT BIT_1158 #define CDMA_CONF_BENAB BIT_1 /* Bus burst enable */175 #define DDMA_CONF_BENAB BIT_1 /* Bus burst enable */567 #define RF_FULL BIT_1 /* Full */965 #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */
140 #define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1))
196 #define BIT_1 0x2 macro493 #define TA_CTL_ENABLE BIT_1
1352 arg2 |= (BIT_0 | BIT_1); in qlcnic_config_switch_port()1364 arg2 &= ~(BIT_1 | BIT_2 | BIT_3); in qlcnic_config_switch_port()1365 if (!(esw_cfg->offload_flags & BIT_1)) in qlcnic_config_switch_port()
531 #define QLC_REGISTER_DCB_AEN BIT_1
815 #define QLCNIC_ENABLE_IPV6_LRO (BIT_1 | BIT_9)1033 if (!(offload_flags & BIT_1)) in qlcnic_process_flags()
24 #define QLCNIC_DUMP_RWCRB BIT_1753 if (dma_sts & BIT_1) in qlcnic_start_pex_dma()
390 cmd.req.arg[1] = ((func & 0xf) << 2) | BIT_6 | BIT_1; in qlcnic_sriov_pf_cfg_eswitch()703 cmd.req.arg[2] |= BIT_1 | BIT_3 | BIT_8; in qlcnic_sriov_set_vf_acl()
2022 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0); in qlcnic_83xx_config_hw_lro()3540 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16); in qlcnic_83xx_get_stats()3571 #define QLCNIC_83XX_ADD_PORT1 BIT_1
1022 #define QLC_83XX_ENCAP_TYPE_VXLAN BIT_1
381 if (status & BIT_1) in qlcnic_sriov_get_vf_vport_info()
364 #define QLCNIC_ENCAP_OUTER_L3_IP6 BIT_1
1495 esw_cfg.offload_flags |= (BIT_1 | BIT_2); in qlcnic_set_default_offload_settings()
81 #define BIT_1 0x2 macro
61 #define HSRX_RISC_IOCB_INT BIT_1 /* RISC to Host IOCB interrupt */