177adf3f0SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2f73cb695SChad Dupuis /* 3f73cb695SChad Dupuis * QLogic Fibre Channel HBA Driver 4bd21eaf9SArmen Baloyan * Copyright (c) 2003-2014 QLogic Corporation 5f73cb695SChad Dupuis */ 6f73cb695SChad Dupuis 7f73cb695SChad Dupuis #ifndef __QLA_DMP27_H__ 8f73cb695SChad Dupuis #define __QLA_DMP27_H__ 9f73cb695SChad Dupuis 10f73cb695SChad Dupuis #define IOBASE_ADDR offsetof(struct device_reg_24xx, iobase_addr) 11f73cb695SChad Dupuis 12f73cb695SChad Dupuis struct __packed qla27xx_fwdt_template { 13f8f97b0cSJoe Carnuccio __le32 template_type; 14f8f97b0cSJoe Carnuccio __le32 entry_offset; 15*8de309e7SArun Easi __le32 template_size; 162ff01671SJoe Carnuccio uint32_t count; /* borrow field for running/residual count */ 17f73cb695SChad Dupuis 18f8f97b0cSJoe Carnuccio __le32 entry_count; 19f73cb695SChad Dupuis uint32_t template_version; 200a36fd6cSHimanshu Madhani __le32 capture_timestamp; 21f73cb695SChad Dupuis uint32_t template_checksum; 22f73cb695SChad Dupuis 23f73cb695SChad Dupuis uint32_t reserved_2; 240a36fd6cSHimanshu Madhani __le32 driver_info[3]; 25f73cb695SChad Dupuis 26f73cb695SChad Dupuis uint32_t saved_state[16]; 27f73cb695SChad Dupuis 28f73cb695SChad Dupuis uint32_t reserved_3[8]; 2921038b09SBart Van Assche __le32 firmware_version[5]; 30f73cb695SChad Dupuis }; 31f73cb695SChad Dupuis 32f73cb695SChad Dupuis #define TEMPLATE_TYPE_FWDUMP 99 33f73cb695SChad Dupuis 34f73cb695SChad Dupuis #define ENTRY_TYPE_NOP 0 35f73cb695SChad Dupuis #define ENTRY_TYPE_TMP_END 255 36f73cb695SChad Dupuis #define ENTRY_TYPE_RD_IOB_T1 256 37f73cb695SChad Dupuis #define ENTRY_TYPE_WR_IOB_T1 257 38f73cb695SChad Dupuis #define ENTRY_TYPE_RD_IOB_T2 258 39f73cb695SChad Dupuis #define ENTRY_TYPE_WR_IOB_T2 259 40f73cb695SChad Dupuis #define ENTRY_TYPE_RD_PCI 260 41f73cb695SChad Dupuis #define ENTRY_TYPE_WR_PCI 261 42f73cb695SChad Dupuis #define ENTRY_TYPE_RD_RAM 262 43f73cb695SChad Dupuis #define ENTRY_TYPE_GET_QUEUE 263 44f73cb695SChad Dupuis #define ENTRY_TYPE_GET_FCE 264 45f73cb695SChad Dupuis #define ENTRY_TYPE_PSE_RISC 265 46f73cb695SChad Dupuis #define ENTRY_TYPE_RST_RISC 266 47f73cb695SChad Dupuis #define ENTRY_TYPE_DIS_INTR 267 48f73cb695SChad Dupuis #define ENTRY_TYPE_GET_HBUF 268 49f73cb695SChad Dupuis #define ENTRY_TYPE_SCRATCH 269 50f73cb695SChad Dupuis #define ENTRY_TYPE_RDREMREG 270 51f73cb695SChad Dupuis #define ENTRY_TYPE_WRREMREG 271 52f73cb695SChad Dupuis #define ENTRY_TYPE_RDREMRAM 272 53f73cb695SChad Dupuis #define ENTRY_TYPE_PCICFG 273 54c0496401SJoe Carnuccio #define ENTRY_TYPE_GET_SHADOW 274 552ac224bcSJoe Carnuccio #define ENTRY_TYPE_WRITE_BUF 275 5664f61d99SJoe Carnuccio #define ENTRY_TYPE_CONDITIONAL 276 5764f61d99SJoe Carnuccio #define ENTRY_TYPE_RDPEPREG 277 5864f61d99SJoe Carnuccio #define ENTRY_TYPE_WRPEPREG 278 59f73cb695SChad Dupuis 60f73cb695SChad Dupuis #define CAPTURE_FLAG_PHYS_ONLY BIT_0 61f73cb695SChad Dupuis #define CAPTURE_FLAG_PHYS_VIRT BIT_1 62f73cb695SChad Dupuis 63f73cb695SChad Dupuis #define DRIVER_FLAG_SKIP_ENTRY BIT_7 64f73cb695SChad Dupuis 65f73cb695SChad Dupuis struct __packed qla27xx_fwdt_entry { 66f73cb695SChad Dupuis struct __packed { 67f8f97b0cSJoe Carnuccio __le32 type; 68f8f97b0cSJoe Carnuccio __le32 size; 69f73cb695SChad Dupuis uint32_t reserved_1; 70f73cb695SChad Dupuis 71f73cb695SChad Dupuis uint8_t capture_flags; 72f73cb695SChad Dupuis uint8_t reserved_2[2]; 73f73cb695SChad Dupuis uint8_t driver_flags; 74f73cb695SChad Dupuis } hdr; 75f73cb695SChad Dupuis union __packed { 76f73cb695SChad Dupuis struct __packed { 77f73cb695SChad Dupuis } t0; 78f73cb695SChad Dupuis 79f73cb695SChad Dupuis struct __packed { 80f73cb695SChad Dupuis } t255; 81f73cb695SChad Dupuis 82f73cb695SChad Dupuis struct __packed { 83f8f97b0cSJoe Carnuccio __le32 base_addr; 84f73cb695SChad Dupuis uint8_t reg_width; 85f8f97b0cSJoe Carnuccio __le16 reg_count; 86f73cb695SChad Dupuis uint8_t pci_offset; 87f73cb695SChad Dupuis } t256; 88f73cb695SChad Dupuis 89f73cb695SChad Dupuis struct __packed { 90f8f97b0cSJoe Carnuccio __le32 base_addr; 91f8f97b0cSJoe Carnuccio __le32 write_data; 92f73cb695SChad Dupuis uint8_t pci_offset; 93f73cb695SChad Dupuis uint8_t reserved[3]; 94f73cb695SChad Dupuis } t257; 95f73cb695SChad Dupuis 96f73cb695SChad Dupuis struct __packed { 97f8f97b0cSJoe Carnuccio __le32 base_addr; 98f73cb695SChad Dupuis uint8_t reg_width; 99f8f97b0cSJoe Carnuccio __le16 reg_count; 100f73cb695SChad Dupuis uint8_t pci_offset; 101f73cb695SChad Dupuis uint8_t banksel_offset; 102f73cb695SChad Dupuis uint8_t reserved[3]; 103f8f97b0cSJoe Carnuccio __le32 bank; 104f73cb695SChad Dupuis } t258; 105f73cb695SChad Dupuis 106f73cb695SChad Dupuis struct __packed { 107f8f97b0cSJoe Carnuccio __le32 base_addr; 108f8f97b0cSJoe Carnuccio __le32 write_data; 109f73cb695SChad Dupuis uint8_t reserved[2]; 110f73cb695SChad Dupuis uint8_t pci_offset; 111f73cb695SChad Dupuis uint8_t banksel_offset; 112f8f97b0cSJoe Carnuccio __le32 bank; 113f73cb695SChad Dupuis } t259; 114f73cb695SChad Dupuis 115f73cb695SChad Dupuis struct __packed { 116c0496401SJoe Carnuccio uint8_t pci_offset; 117f73cb695SChad Dupuis uint8_t reserved[3]; 118f73cb695SChad Dupuis } t260; 119f73cb695SChad Dupuis 120f73cb695SChad Dupuis struct __packed { 121c0496401SJoe Carnuccio uint8_t pci_offset; 122f73cb695SChad Dupuis uint8_t reserved[3]; 123f8f97b0cSJoe Carnuccio __le32 write_data; 124f73cb695SChad Dupuis } t261; 125f73cb695SChad Dupuis 126f73cb695SChad Dupuis struct __packed { 127f73cb695SChad Dupuis uint8_t ram_area; 128f73cb695SChad Dupuis uint8_t reserved[3]; 129f8f97b0cSJoe Carnuccio __le32 start_addr; 130f8f97b0cSJoe Carnuccio __le32 end_addr; 131f73cb695SChad Dupuis } t262; 132f73cb695SChad Dupuis 133f73cb695SChad Dupuis struct __packed { 134f73cb695SChad Dupuis uint32_t num_queues; 135f73cb695SChad Dupuis uint8_t queue_type; 136f73cb695SChad Dupuis uint8_t reserved[3]; 137f73cb695SChad Dupuis } t263; 138f73cb695SChad Dupuis 139f73cb695SChad Dupuis struct __packed { 140f73cb695SChad Dupuis uint32_t fce_trace_size; 141f73cb695SChad Dupuis uint64_t write_pointer; 142f73cb695SChad Dupuis uint64_t base_pointer; 143f73cb695SChad Dupuis uint32_t fce_enable_mb0; 144f73cb695SChad Dupuis uint32_t fce_enable_mb2; 145f73cb695SChad Dupuis uint32_t fce_enable_mb3; 146f73cb695SChad Dupuis uint32_t fce_enable_mb4; 147f73cb695SChad Dupuis uint32_t fce_enable_mb5; 148f73cb695SChad Dupuis uint32_t fce_enable_mb6; 149f73cb695SChad Dupuis } t264; 150f73cb695SChad Dupuis 151f73cb695SChad Dupuis struct __packed { 152f73cb695SChad Dupuis } t265; 153f73cb695SChad Dupuis 154f73cb695SChad Dupuis struct __packed { 155f73cb695SChad Dupuis } t266; 156f73cb695SChad Dupuis 157f73cb695SChad Dupuis struct __packed { 158f73cb695SChad Dupuis uint8_t pci_offset; 159f73cb695SChad Dupuis uint8_t reserved[3]; 160f8f97b0cSJoe Carnuccio __le32 data; 161f73cb695SChad Dupuis } t267; 162f73cb695SChad Dupuis 163f73cb695SChad Dupuis struct __packed { 164f73cb695SChad Dupuis uint8_t buf_type; 165f73cb695SChad Dupuis uint8_t reserved[3]; 166f73cb695SChad Dupuis uint32_t buf_size; 167f73cb695SChad Dupuis uint64_t start_addr; 168f73cb695SChad Dupuis } t268; 169f73cb695SChad Dupuis 170f73cb695SChad Dupuis struct __packed { 171f73cb695SChad Dupuis uint32_t scratch_size; 172f73cb695SChad Dupuis } t269; 173f73cb695SChad Dupuis 174f73cb695SChad Dupuis struct __packed { 175f8f97b0cSJoe Carnuccio __le32 addr; 176f8f97b0cSJoe Carnuccio __le32 count; 177f73cb695SChad Dupuis } t270; 178f73cb695SChad Dupuis 179f73cb695SChad Dupuis struct __packed { 180f8f97b0cSJoe Carnuccio __le32 addr; 181f8f97b0cSJoe Carnuccio __le32 data; 182f73cb695SChad Dupuis } t271; 183f73cb695SChad Dupuis 184f73cb695SChad Dupuis struct __packed { 185f8f97b0cSJoe Carnuccio __le32 addr; 186f8f97b0cSJoe Carnuccio __le32 count; 187f73cb695SChad Dupuis } t272; 188f73cb695SChad Dupuis 189f73cb695SChad Dupuis struct __packed { 190f8f97b0cSJoe Carnuccio __le32 addr; 191f8f97b0cSJoe Carnuccio __le32 count; 192f73cb695SChad Dupuis } t273; 193c0496401SJoe Carnuccio 194c0496401SJoe Carnuccio struct __packed { 195c0496401SJoe Carnuccio uint32_t num_queues; 196c0496401SJoe Carnuccio uint8_t queue_type; 197c0496401SJoe Carnuccio uint8_t reserved[3]; 198c0496401SJoe Carnuccio } t274; 1992ac224bcSJoe Carnuccio 2002ac224bcSJoe Carnuccio struct __packed { 201f8f97b0cSJoe Carnuccio __le32 length; 2022ac224bcSJoe Carnuccio uint8_t buffer[]; 2032ac224bcSJoe Carnuccio } t275; 20464f61d99SJoe Carnuccio 20564f61d99SJoe Carnuccio struct __packed { 206f8f97b0cSJoe Carnuccio __le32 cond1; 207f8f97b0cSJoe Carnuccio __le32 cond2; 20864f61d99SJoe Carnuccio } t276; 20964f61d99SJoe Carnuccio 21064f61d99SJoe Carnuccio struct __packed { 211f8f97b0cSJoe Carnuccio __le32 cmd_addr; 212f8f97b0cSJoe Carnuccio __le32 wr_cmd_data; 213f8f97b0cSJoe Carnuccio __le32 data_addr; 21464f61d99SJoe Carnuccio } t277; 21564f61d99SJoe Carnuccio 21664f61d99SJoe Carnuccio struct __packed { 217f8f97b0cSJoe Carnuccio __le32 cmd_addr; 218f8f97b0cSJoe Carnuccio __le32 wr_cmd_data; 219f8f97b0cSJoe Carnuccio __le32 data_addr; 220f8f97b0cSJoe Carnuccio __le32 wr_data; 22164f61d99SJoe Carnuccio } t278; 222f73cb695SChad Dupuis }; 223f73cb695SChad Dupuis }; 224f73cb695SChad Dupuis 225f73cb695SChad Dupuis #define T262_RAM_AREA_CRITICAL_RAM 1 226f73cb695SChad Dupuis #define T262_RAM_AREA_EXTERNAL_RAM 2 227f73cb695SChad Dupuis #define T262_RAM_AREA_SHARED_RAM 3 228f73cb695SChad Dupuis #define T262_RAM_AREA_DDR_RAM 4 22964f61d99SJoe Carnuccio #define T262_RAM_AREA_MISC 5 230f73cb695SChad Dupuis 231f73cb695SChad Dupuis #define T263_QUEUE_TYPE_REQ 1 232f73cb695SChad Dupuis #define T263_QUEUE_TYPE_RSP 2 233f73cb695SChad Dupuis #define T263_QUEUE_TYPE_ATIO 3 234f73cb695SChad Dupuis 235f73cb695SChad Dupuis #define T268_BUF_TYPE_EXTD_TRACE 1 236f73cb695SChad Dupuis #define T268_BUF_TYPE_EXCH_BUFOFF 2 237f73cb695SChad Dupuis #define T268_BUF_TYPE_EXTD_LOGIN 3 238349c390fSJoe Carnuccio #define T268_BUF_TYPE_REQ_MIRROR 4 239349c390fSJoe Carnuccio #define T268_BUF_TYPE_RSP_MIRROR 5 240f73cb695SChad Dupuis 241c0496401SJoe Carnuccio #define T274_QUEUE_TYPE_REQ_SHAD 1 242c0496401SJoe Carnuccio #define T274_QUEUE_TYPE_RSP_SHAD 2 243c0496401SJoe Carnuccio #define T274_QUEUE_TYPE_ATIO_SHAD 3 244c0496401SJoe Carnuccio 245f73cb695SChad Dupuis #endif 246