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Searched refs:BIT_0 (Results 1 – 25 of 28) sorted by relevance

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/linux/drivers/scsi/qla2xxx/
H A Dqla_edif.h19 #define EDIF_SA_CTL_FLG_REPL BIT_0
44 EDB_ACTIVE = BIT_0,
79 #define SA_FLAG_INVALIDATE BIT_0
H A Dqla_fw.h22 #define FO1_ENABLE_8016 BIT_0
31 #define PDO_FORCE_PLOGI BIT_0
458 #define BD_WRITE_DATA BIT_0
499 #define CF_WRITE_DATA BIT_0
541 #define TMF_WRITE_DATA BIT_0
624 #define SF_FCP_RSP_DMA BIT_0
975 #define TCF_CLEAR_ACA BIT_0
1000 #define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */
1196 #define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */
1265 #define GPDX_DATA_INOUT (BIT_1|BIT_0)
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H A Dqla_target.h227 #define ATIO_EXEC_WRITE BIT_0
422 #define EF_EN_EDIF BIT_0
485 #define CTIO7_FLAGS_DATA_OUT BIT_0 /* data from initiator */
587 #define ABTS_PARAM_ABORT_SEQ BIT_0
625 #define ABTS_CONTR_FLG_TERM_EXCHG BIT_0
852 TRC_NEW_CMD = BIT_0,
1000 #define QLA24XX_MGMT_SEND_NACK BIT_0
H A Dqla_nvme.h66 #define CF_WRITE_DATA BIT_0
H A Dqla_tmpl.h60 #define CAPTURE_FLAG_PHYS_ONLY BIT_0
H A Dqla_isr.c388 if (rd_reg_word(&reg->semaphore) & BIT_0) { in qla2100_intr_handler()
591 if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0)) in qla2x00_mbx_completion()
593 else if (mboxes & BIT_0) in qla2x00_mbx_completion()
1473 if (mb[2] & BIT_0) in qla2x00_async_event()
2148 if (le16_to_cpu(mbx->mb1) & BIT_0) in qla2x00_mbx_iocb_entry()
3857 if (mboxes & BIT_0) in qla24xx_mbx_completion()
4200 for (cnt = 10000; (rd_reg_dword(&reg->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()
4213 for (cnt = 100; (rd_reg_dword(&reg->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()
H A Dqla_mid.c623 req->options |= BIT_0; in qla25xx_delete_req_que()
640 rsp->options |= BIT_0; in qla25xx_delete_rsp_que()
H A Dqla_iocb.c1714 #define QDSS_GOT_Q_SPACE BIT_0 in qla24xx_dif_start_scsi()
2083 #define QDSS_GOT_Q_SPACE BIT_0 in qla2xxx_dif_start_scsi_mq()
2454 opts = lio->u.logio.flags & SRB_LOGIN_COND_PLOGI ? BIT_0 : 0; in qla2x00_login_iocb()
2528 mbx->mb10 = cpu_to_le16(BIT_0); in qla2x00_adisc_iocb()
2530 mbx->mb1 = cpu_to_le16((sp->fcport->loop_id << 8) | BIT_0); in qla2x00_adisc_iocb()
H A Dqla_nvme.c1013 WARN_ON_ONCE(abt->options & cpu_to_le16(BIT_0)); in qla_nvme_abort_set_option()
H A Dqla_mr.c118 if (mboxes & BIT_0) in qlafx00_mailbox_command()
195 if (mboxes & BIT_0) in qlafx00_mailbox_command()
H A Dqla_dbg.c1007 (rd_reg_word(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) { in qla2100_fw_dump()
1045 if (rd_reg_word(&reg->semaphore) & BIT_0) { in qla2100_fw_dump()
/linux/drivers/scsi/
H A Dqla1280.h17 #define BIT_0 0x1 macro
131 #define ISP_CFG1_SXP BIT_0 /* SXP register select */
133 #define ISP_RESET BIT_0 /* ISP soft reset */
145 #define NV_CLOCK BIT_0
159 #define CDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */
176 #define DDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */
202 #define BIOS_ENABLE BIT_0
566 #define RF_CONT BIT_0 /* Continuation. */
/linux/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_hw.h140 #define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1))
H A Dqlcnic_83xx_hw.h364 #define QLC_83XX_LINK_STATS(data) ((data) & BIT_0)
530 #define QLC_REGISTER_LB_IDC BIT_0
H A Dqlcnic_hdr.h195 #define BIT_0 0x1 macro
492 #define TA_CTL_START BIT_0
H A Dqlcnic_ctx.c1341 arg1 = (adapter->npars[index].phy_port & BIT_0); in qlcnic_config_switch_port()
1352 arg2 |= (BIT_0 | BIT_1); in qlcnic_config_switch_port()
1362 arg2 &= ~BIT_0; in qlcnic_config_switch_port()
1363 if (!(esw_cfg->offload_flags & BIT_0)) in qlcnic_config_switch_port()
H A Dqlcnic_hw.c814 #define QLCNIC_ENABLE_IPV4_LRO BIT_0
1028 if (offload_flags & BIT_0) { in qlcnic_process_flags()
H A Dqlcnic_minidump.c23 #define QLCNIC_DUMP_WCRB BIT_0
298 fw_dump->use_pex_dma = (hdr->capabilities & BIT_0) ? true : false; in qlcnic_82xx_cache_tmpl_hdr_values()
H A Dqlcnic_io.c363 #define QLCNIC_ENCAP_VXLAN_PKT BIT_0
493 if (*(skb->data) & BIT_0) { in qlcnic_tx_pkt()
494 flags |= BIT_0; in qlcnic_tx_pkt()
H A Dqlcnic_sriov_pf.c392 cmd.req.arg[1] |= BIT_0; in qlcnic_sriov_pf_cfg_eswitch()
1895 nic_info.bit_offsets = BIT_0; in qlcnic_sriov_set_vf_tx_rate()
H A Dqlcnic_main.c1490 esw_cfg.mac_override = BIT_0; in qlcnic_set_default_offload_settings()
1491 esw_cfg.promisc_mode = BIT_0; in qlcnic_set_default_offload_settings()
1493 esw_cfg.offload_flags = BIT_0; in qlcnic_set_default_offload_settings()
H A Dqlcnic_83xx_hw.c2022 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0); in qlcnic_83xx_config_hw_lro()
3570 #define QLCNIC_83XX_ADD_PORT0 BIT_0
3670 cmd.req.arg[3] = BIT_0; in qlcnic_83xx_interrupt_test()
/linux/drivers/scsi/qla4xxx/
H A Dql4_fw.h54 #define HINT_MBX_INT_PENDING BIT_0
60 #define HSRX_RISC_MB_INT BIT_0 /* RISC to Host Mailbox interrupt */
64 #define ISRX_82XX_RISC_INT BIT_0 /* RISC interrupt. */
H A Dql4_def.h80 #define BIT_0 0x1 macro
H A Dql4_init.c291 if (!(le32_to_cpu(*cap_offset) & BIT_0)) { in qla4_80xx_is_minidump_dma_capable()

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