Searched refs:BIT_0 (Results 1 – 21 of 21) sorted by relevance
19 #define EDIF_SA_CTL_FLG_REPL BIT_044 EDB_ACTIVE = BIT_0,79 #define SA_FLAG_INVALIDATE BIT_0
227 #define ATIO_EXEC_WRITE BIT_0422 #define EF_EN_EDIF BIT_0485 #define CTIO7_FLAGS_DATA_OUT BIT_0 /* data from initiator */587 #define ABTS_PARAM_ABORT_SEQ BIT_0625 #define ABTS_CONTR_FLG_TERM_EXCHG BIT_0852 TRC_NEW_CMD = BIT_0,1000 #define QLA24XX_MGMT_SEND_NACK BIT_0
60 #define CAPTURE_FLAG_PHYS_ONLY BIT_0
2795 if (rd_reg_word(®->mailbox12) & BIT_0) in qla2x00_initialize_adapter()4596 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()4600 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()4610 ((rx_sens & (BIT_1 | BIT_0)) << 2) | in qla2x00_update_fw_options()4611 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()4616 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); in qla2x00_update_fw_options()4618 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()4628 ((rx_sens & (BIT_1 | BIT_0)) << 2) | in qla2x00_update_fw_options()4629 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()4736 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0) in qla24xx_update_fw_options()[all …]
118 if (mboxes & BIT_0) in qlafx00_mailbox_command()195 if (mboxes & BIT_0) in qlafx00_mailbox_command()
17 #define BIT_0 0x1 macro131 #define ISP_CFG1_SXP BIT_0 /* SXP register select */133 #define ISP_RESET BIT_0 /* ISP soft reset */145 #define NV_CLOCK BIT_0159 #define CDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */176 #define DDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */202 #define BIOS_ENABLE BIT_0566 #define RF_CONT BIT_0 /* Continuation. */
140 #define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1))
364 #define QLC_83XX_LINK_STATS(data) ((data) & BIT_0)530 #define QLC_REGISTER_LB_IDC BIT_0
195 #define BIT_0 0x1 macro492 #define TA_CTL_START BIT_0
1341 arg1 = (adapter->npars[index].phy_port & BIT_0); in qlcnic_config_switch_port()1352 arg2 |= (BIT_0 | BIT_1); in qlcnic_config_switch_port()1362 arg2 &= ~BIT_0; in qlcnic_config_switch_port()1363 if (!(esw_cfg->offload_flags & BIT_0)) in qlcnic_config_switch_port()
814 #define QLCNIC_ENABLE_IPV4_LRO BIT_01028 if (offload_flags & BIT_0) { in qlcnic_process_flags()
23 #define QLCNIC_DUMP_WCRB BIT_0298 fw_dump->use_pex_dma = (hdr->capabilities & BIT_0) ? true : false; in qlcnic_82xx_cache_tmpl_hdr_values()
363 #define QLCNIC_ENCAP_VXLAN_PKT BIT_0493 if (*(skb->data) & BIT_0) { in qlcnic_tx_pkt()494 flags |= BIT_0; in qlcnic_tx_pkt()
392 cmd.req.arg[1] |= BIT_0; in qlcnic_sriov_pf_cfg_eswitch()1895 nic_info.bit_offsets = BIT_0; in qlcnic_sriov_set_vf_tx_rate()
1490 esw_cfg.mac_override = BIT_0; in qlcnic_set_default_offload_settings()1491 esw_cfg.promisc_mode = BIT_0; in qlcnic_set_default_offload_settings()1493 esw_cfg.offload_flags = BIT_0; in qlcnic_set_default_offload_settings()
2022 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0); in qlcnic_83xx_config_hw_lro()3570 #define QLCNIC_83XX_ADD_PORT0 BIT_03670 cmd.req.arg[3] = BIT_0; in qlcnic_83xx_interrupt_test()
379 if (status & BIT_0) in qlcnic_sriov_get_vf_vport_info()
54 #define HINT_MBX_INT_PENDING BIT_060 #define HSRX_RISC_MB_INT BIT_0 /* RISC to Host Mailbox interrupt */64 #define ISRX_82XX_RISC_INT BIT_0 /* RISC interrupt. */
80 #define BIT_0 0x1 macro
291 if (!(le32_to_cpu(*cap_offset) & BIT_0)) { in qla4_80xx_is_minidump_dma_capable()
3552 sess->erl |= BIT_0; in qla4xxx_copy_from_fwddb_param()3681 SET_BITVAL(sess->erl & BIT_0, options, BIT_0); in qla4xxx_copy_to_fwddb_param()3690 SET_BITVAL(conn->tcp_timer_scale & BIT_0, options, BIT_1); in qla4xxx_copy_to_fwddb_param()3691 SET_BITVAL(conn->tcp_timestamp_en, options, BIT_0); in qla4xxx_copy_to_fwddb_param()3788 sess->erl |= BIT_0; in qla4xxx_copy_to_sess_conn_params()