/linux/drivers/scsi/qla2xxx/ |
H A D | qla_edif.h | 19 #define EDIF_SA_CTL_FLG_REPL BIT_0 44 EDB_ACTIVE = BIT_0, 79 #define SA_FLAG_INVALIDATE BIT_0
|
H A D | qla_fw.h | 22 #define FO1_ENABLE_8016 BIT_0 31 #define PDO_FORCE_PLOGI BIT_0 458 #define BD_WRITE_DATA BIT_0 499 #define CF_WRITE_DATA BIT_0 541 #define TMF_WRITE_DATA BIT_0 624 #define SF_FCP_RSP_DMA BIT_0 975 #define TCF_CLEAR_ACA BIT_0 1000 #define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */ 1196 #define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */ 1265 #define GPDX_DATA_INOUT (BIT_1|BIT_0) [all …]
|
H A D | qla_target.h | 226 #define ATIO_EXEC_WRITE BIT_0 421 #define EF_EN_EDIF BIT_0 484 #define CTIO7_FLAGS_DATA_OUT BIT_0 /* data from initiator */ 586 #define ABTS_PARAM_ABORT_SEQ BIT_0 624 #define ABTS_CONTR_FLG_TERM_EXCHG BIT_0 840 TRC_NEW_CMD = BIT_0, 966 #define QLA24XX_MGMT_SEND_NACK BIT_0
|
H A D | qla_def.h | 107 #define BIT_0 0x1 macro 229 #define IDC_DEVICE_STATE_CHANGE BIT_0 249 #define QLA83XX_IDC_RESET_DISABLED BIT_0 415 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 533 #define SRB_LOGIN_RETRIED BIT_0 583 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 825 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 843 #define NVR_CLOCK BIT_0 1098 #define MBX_DMA_IN BIT_0 1111 #define MBX_DMA_IN BIT_0 [all …]
|
H A D | qla_nvme.h | 66 #define CF_WRITE_DATA BIT_0
|
H A D | qla_tmpl.h | 60 #define CAPTURE_FLAG_PHYS_ONLY BIT_0
|
H A D | qla_inline.h | 381 return (data >> 6) & BIT_0 ? FC4_PRIORITY_FCP : FC4_PRIORITY_NVME; in qla2xxx_get_fc4_priority() 386 RESOURCE_IOCB = BIT_0,
|
H A D | qla_mbx.c | 237 if (mboxes & BIT_0) { in qla2x00_mailbox_command() 406 if (mboxes & BIT_0) { in qla2x00_mailbox_command() 579 if (mboxes & BIT_0) { in qla2x00_mailbox_command() 714 mcp->mb[4] = BIT_0; in qla2x00_execute_fw() 794 ha->max_supported_speed = mcp->mb[2] & (BIT_0|BIT_1); in qla2x00_execute_fw() 801 (BIT_0 | BIT_1 | BIT_2); in qla2x00_execute_fw() 1886 mcp->mb[1] = BIT_0; in qla2x00_init_firmware() 2530 if (opt & BIT_0) in qla24xx_login_fabric() 2594 mb[1] = BIT_0; in qla24xx_login_fabric() 2599 mb[10] |= BIT_0; /* Class 2. */ in qla24xx_login_fabric() [all …]
|
H A D | qla_init.c | 2771 if (rd_reg_word(®->mailbox12) & BIT_0) in qla2x00_initialize_adapter() 4492 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options() 4496 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options() 4506 ((rx_sens & (BIT_1 | BIT_0)) << 2) | in qla2x00_update_fw_options() 4507 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options() 4512 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); in qla2x00_update_fw_options() 4514 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options() 4524 ((rx_sens & (BIT_1 | BIT_0)) << 2) | in qla2x00_update_fw_options() 4525 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options() 4632 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0) in qla24xx_update_fw_options() [all …]
|
H A D | qla_nx.h | 842 #define HINT_MBX_INT_PENDING BIT_0 851 #define ISRX_NX_RISC_INT BIT_0 /* RISC interrupt. */
|
H A D | qla_isr.c | 388 if (rd_reg_word(®->semaphore) & BIT_0) { in qla2100_intr_handler() 591 if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0)) in qla2x00_mbx_completion() 593 else if (mboxes & BIT_0) in qla2x00_mbx_completion() 1466 if (mb[2] & BIT_0) in qla2x00_async_event() 2126 if (le16_to_cpu(mbx->mb1) & BIT_0) in qla2x00_mbx_iocb_entry() 3835 if (mboxes & BIT_0) in qla24xx_mbx_completion() 4178 for (cnt = 10000; (rd_reg_dword(®->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status() 4191 for (cnt = 100; (rd_reg_dword(®->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()
|
H A D | qla_mid.c | 623 req->options |= BIT_0; in qla25xx_delete_req_que() 640 rsp->options |= BIT_0; in qla25xx_delete_rsp_que()
|
H A D | qla_sup.c | 39 while ((data & BIT_0) == 0) { in qla2x00_lock_nvram_access() 128 data |= BIT_0; in qla2x00_nvram_request() 1179 if ((flags & BIT_0) == 0) in qla2xxx_flash_npiv_conf() 1252 if (!(dword & BIT_0)) in qla24xx_protect_flash()
|
H A D | qla_iocb.c | 1714 #define QDSS_GOT_Q_SPACE BIT_0 in qla24xx_dif_start_scsi() 2083 #define QDSS_GOT_Q_SPACE BIT_0 in qla2xxx_dif_start_scsi_mq() 2454 opts = lio->u.logio.flags & SRB_LOGIN_COND_PLOGI ? BIT_0 : 0; in qla2x00_login_iocb() 2528 mbx->mb10 = cpu_to_le16(BIT_0); in qla2x00_adisc_iocb() 2530 mbx->mb1 = cpu_to_le16((sp->fcport->loop_id << 8) | BIT_0); in qla2x00_adisc_iocb()
|
/linux/drivers/scsi/ |
H A D | qla1280.h | 17 #define BIT_0 0x1 macro 131 #define ISP_CFG1_SXP BIT_0 /* SXP register select */ 133 #define ISP_RESET BIT_0 /* ISP soft reset */ 145 #define NV_CLOCK BIT_0 159 #define CDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */ 176 #define DDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */ 202 #define BIOS_ENABLE BIT_0 566 #define RF_CONT BIT_0 /* Continuation. */
|
H A D | qla1280.c | 1116 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; in qla1280_set_target_parameters() 1190 (ha->bus_settings[bus].qtag_enables & (BIT_0 << target))) { in qla1280_slave_configure() 1682 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb); in qla1280_load_firmware_pio() 1696 #define CMD_ARGS (BIT_7 | BIT_6 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0) 1700 #define CMD_ARGS (BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0) 1824 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); in qla1280_start_firmware() 1834 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_start_firmware() 1901 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings() 1915 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings() 2089 flag = (BIT_0 << target); in qla1280_config_target() [all …]
|
/linux/drivers/net/ethernet/qlogic/qlcnic/ |
H A D | qlcnic_hw.h | 140 #define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1))
|
H A D | qlcnic_83xx_hw.h | 364 #define QLC_83XX_LINK_STATS(data) ((data) & BIT_0) 530 #define QLC_REGISTER_LB_IDC BIT_0
|
H A D | qlcnic_hdr.h | 195 #define BIT_0 0x1 macro 492 #define TA_CTL_START BIT_0
|
H A D | qlcnic_ctx.c | 1341 arg1 = (adapter->npars[index].phy_port & BIT_0); in qlcnic_config_switch_port() 1352 arg2 |= (BIT_0 | BIT_1); in qlcnic_config_switch_port() 1362 arg2 &= ~BIT_0; in qlcnic_config_switch_port() 1363 if (!(esw_cfg->offload_flags & BIT_0)) in qlcnic_config_switch_port()
|
H A D | qlcnic_hw.c | 814 #define QLCNIC_ENABLE_IPV4_LRO BIT_0 1028 if (offload_flags & BIT_0) { in qlcnic_process_flags()
|
H A D | qlcnic_minidump.c | 23 #define QLCNIC_DUMP_WCRB BIT_0 298 fw_dump->use_pex_dma = (hdr->capabilities & BIT_0) ? true : false; in qlcnic_82xx_cache_tmpl_hdr_values()
|
H A D | qlcnic_io.c | 363 #define QLCNIC_ENCAP_VXLAN_PKT BIT_0 493 if (*(skb->data) & BIT_0) { in qlcnic_tx_pkt() 494 flags |= BIT_0; in qlcnic_tx_pkt()
|
/linux/drivers/scsi/qla4xxx/ |
H A D | ql4_fw.h | 54 #define HINT_MBX_INT_PENDING BIT_0 60 #define HSRX_RISC_MB_INT BIT_0 /* RISC to Host Mailbox interrupt */ 64 #define ISRX_82XX_RISC_INT BIT_0 /* RISC interrupt. */
|
H A D | ql4_def.h | 80 #define BIT_0 0x1 macro
|