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Searched refs:BIT6 (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h
H A Dhal_com_reg.h
H A Drtl8723b_spec.h
/linux/drivers/scsi/
H A Ddc395x.h70 #define BIT6 0x00000040 macro
138 #define DATAIN BIT6
171 #define EN_ATN_STOP BIT6
/linux/drivers/video/fbdev/via/
H A Ddvi.c55 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
62 BIT5 + BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
421 viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0); in viafb_dvi_enable()
H A Dhw.c1669 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6); in viafb_init_dac()
1676 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6); in viafb_init_dac()
1680 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6); in viafb_init_dac()
2033 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); in enable_second_display_channel()
2035 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); in enable_second_display_channel()
2041 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); in disable_second_display_channel()
2043 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); in disable_second_display_channel()
H A Dshare.h20 #define BIT6 0x40 macro
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h285 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
420 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0 \
444 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 \
642 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
/linux/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbt_precomp.h37 #define BIT6 0x00000040 macro
H A Dhalbtc8821a2ant.h9 #define BT_INFO_8821A_2ANT_B_A2DP BIT6
H A Dhalbtc8192e2ant.h8 #define BT_INFO_8192E_2ANT_B_A2DP BIT6
H A Dhalbtc8821a1ant.h9 #define BT_INFO_8821A_1ANT_B_A2DP BIT6
H A Dhalbtc8723b2ant.h11 #define BT_INFO_8723B_2ANT_B_A2DP BIT6
H A Dhalbtc8821a1ant.c840 real_byte5 &= ~BIT6; in btc8821a1ant_set_fw_ps_tdma()
/linux/drivers/tty/serial/
H A Dzs.h172 #define BIT6 1 /* 6 bit/8bit sync */ macro
H A Dsunzilog.h156 #define BIT6 1 /* 6 bit/8bit sync */ macro
H A Dip22zilog.h154 #define BIT6 1 /* 6 bit/8bit sync */ macro
H A Dpmac_zilog.h237 #define BIT6 1 /* 6 bit/8bit sync */ macro
/linux/drivers/staging/rtl8723bs/hal/
H A DHalBtc8723b2Ant.h
H A DHalBtc8723b1Ant.h
/linux/include/uapi/linux/
H A Dsynclink.h
/linux/drivers/tty/
H A Dsynclink_gt.c
/linux/lib/zstd/common/
H A Dzstd_internal.h66 #define BIT6 64 macro