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Searched refs:BIT6 (Results 1 – 25 of 31) sorted by relevance

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/linux/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h55 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL co…
62 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 int…
73 …{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6…
156 …{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6…
205 …PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT6, BIT6},/*polling FW in…
H A Dhal_com_reg.h213 #define HSISR_RON_INT BIT6
225 #define RRSR_12M BIT6
290 #define RCR_CBSSID_DATA BIT6 /* Accept BSSID match packet (Data) */
557 #define SDIO_HISR_TXBCNOK BIT6
H A Drtl8723b_spec.h208 #define IMR_MGNTDOK_8723B BIT6 /* Management Queue DMA OK */
/linux/drivers/video/fbdev/via/
H A Dlcd.c376 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6); in load_lcd_scaling()
609 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
618 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
631 viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6); in integrated_lvds_disable()
637 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
661 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
670 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
686 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6); in integrated_lvds_enable()
692 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
H A Ddvi.c55 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
62 BIT5 + BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
421 viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0); in viafb_dvi_enable()
H A Dhw.c1669 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6); in viafb_init_dac()
1676 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6); in viafb_init_dac()
1680 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6); in viafb_init_dac()
2033 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); in enable_second_display_channel()
2035 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); in enable_second_display_channel()
2041 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); in disable_second_display_channel()
2043 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); in disable_second_display_channel()
H A Dshare.h20 #define BIT6 0x40 macro
/linux/drivers/scsi/
H A Ddc395x.h70 #define BIT6 0x00000040 macro
138 #define DATAIN BIT6
171 #define EN_ATN_STOP BIT6
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h285 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
420 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0 \
444 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 \
642 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
/linux/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbt_precomp.h37 #define BIT6 0x00000040 macro
H A Dhalbtc8821a2ant.h9 #define BT_INFO_8821A_2ANT_B_A2DP BIT6
H A Dhalbtc8192e2ant.h8 #define BT_INFO_8192E_2ANT_B_A2DP BIT6
H A Dhalbtc8821a1ant.h9 #define BT_INFO_8821A_1ANT_B_A2DP BIT6
H A Dhalbtc8723b2ant.h11 #define BT_INFO_8723B_2ANT_B_A2DP BIT6
/linux/drivers/net/hamradio/
H A Dz8530.h118 #define BIT6 1 /* 6 bit/8bit sync */ macro
/linux/drivers/tty/serial/
H A Dzs.h173 #define BIT6 1 /* 6 bit/8bit sync */ macro
H A Dsunzilog.h156 #define BIT6 1 /* 6 bit/8bit sync */ macro
H A Dip22zilog.h154 #define BIT6 1 /* 6 bit/8bit sync */ macro
/linux/drivers/staging/rtl8723bs/hal/
H A DHalHWImg8723B_MAC.c19 ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ in CheckPositive()
H A DHalBtc8723b2Ant.h9 #define BT_INFO_8723B_2ANT_B_A2DP BIT6
H A DHalBtc8723b1Ant.h9 #define BT_INFO_8723B_1ANT_B_A2DP BIT6
H A DHalHWImg8723B_RF.c19 ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ in CheckPositive()
H A DHalHWImg8723B_BB.c19 ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ in CheckPositive()
/linux/include/uapi/linux/
H A Dsynclink.h25 #define BIT6 0x0040 macro
/linux/drivers/tty/
H A Dsynclink_gt.c390 #define IRQ_CTS BIT6
1324 value |= BIT6; in set_break()
1326 value &= ~BIT6; in set_break()
3890 wr_reg32(info, RDCSR, BIT6); in rx_start()
3903 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); in rx_start()
4200 val |= BIT6; in sync_mode()
4292 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ in sync_mode()
4294 val |= BIT6; /* 010, txclk = BRG */ in sync_mode()
4323 val = BIT7 + BIT6; break; in sync_mode()
4324 default: val = BIT6; // NRZ encodings in sync_mode()
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