1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_FW_H__
6 #define __RTW89_FW_H__
7
8 #include "core.h"
9
10 enum rtw89_fw_dl_status {
11 RTW89_FWDL_INITIAL_STATE = 0,
12 RTW89_FWDL_FWDL_ONGOING = 1,
13 RTW89_FWDL_CHECKSUM_FAIL = 2,
14 RTW89_FWDL_SECURITY_FAIL = 3,
15 RTW89_FWDL_CV_NOT_MATCH = 4,
16 RTW89_FWDL_RSVD0 = 5,
17 RTW89_FWDL_WCPU_FWDL_RDY = 6,
18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7
19 };
20
21 struct rtw89_c2hreg_hdr {
22 u32 w0;
23 };
24
25 #define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0)
26 #define RTW89_C2HREG_HDR_ACK BIT(7)
27 #define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8)
28 #define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)
29
30 struct rtw89_c2hreg_phycap {
31 u32 w0;
32 u32 w1;
33 u32 w2;
34 u32 w3;
35 } __packed;
36
37 #define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0)
38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
39 #define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8)
40 #define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)
41 #define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16)
42 #define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)
43 #define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0)
44 #define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8)
45 #define RTW89_C2HREG_PHYCAP_W1_PROT_11N 1
46 #define RTW89_C2HREG_PHYCAP_W1_PROT_11AC 2
47 #define RTW89_C2HREG_PHYCAP_W1_PROT_11AX 3
48 #define RTW89_C2HREG_PHYCAP_W1_PROT_11BE 4
49 #define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16)
50 #define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24)
51 #define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0)
52 #define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8)
53 #define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16)
54 #define RTW89_C2HREG_PHYCAP_W3_BAND_SEL GENMASK(31, 24)
55
56 #define RTW89_C2HREG_PHYCAP_P1_W0_B1_RX_NSS GENMASK(23, 16)
57 #define RTW89_C2HREG_PHYCAP_P1_W0_B1_BW GENMASK(31, 24)
58 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_TX_NSS GENMASK(7, 0)
59 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_TX_NUM GENMASK(15, 8)
60 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_RX_NUM GENMASK(23, 16)
61 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_BAND_SEL GENMASK(31, 24)
62 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM GENMASK(7, 0)
63 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM_256 0x1
64 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024 0x2
65 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096 0x3
66 #define RTW89_C2HREG_PHYCAP_P1_W2_B1_QAM GENMASK(15, 8)
67
68 #define RTW89_C2HREG_AOAC_RPT_1_W0_KEY_IDX GENMASK(23, 16)
69 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_0 GENMASK(7, 0)
70 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_1 GENMASK(15, 8)
71 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_2 GENMASK(23, 16)
72 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_3 GENMASK(31, 24)
73 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_4 GENMASK(7, 0)
74 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_5 GENMASK(15, 8)
75 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_6 GENMASK(23, 16)
76 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_7 GENMASK(31, 24)
77 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_0 GENMASK(7, 0)
78 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_1 GENMASK(15, 8)
79 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_2 GENMASK(23, 16)
80 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_3 GENMASK(31, 24)
81 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_4 GENMASK(23, 16)
82 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_5 GENMASK(31, 24)
83 #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_6 GENMASK(7, 0)
84 #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_7 GENMASK(15, 8)
85 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_0 GENMASK(23, 16)
86 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_1 GENMASK(31, 24)
87 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_2 GENMASK(7, 0)
88 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_3 GENMASK(15, 8)
89 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_4 GENMASK(23, 16)
90 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_5 GENMASK(31, 24)
91 #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_6 GENMASK(7, 0)
92 #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_7 GENMASK(15, 8)
93
94 #define RTW89_C2HREG_PS_LEAVE_ACK_RET GENMASK(7, 0)
95 #define RTW89_C2HREG_PS_LEAVE_ACK_MACID GENMASK(31, 16)
96
97 struct rtw89_h2creg_hdr {
98 u32 w0;
99 };
100
101 #define RTW89_H2CREG_HDR_FUNC_MASK GENMASK(6, 0)
102 #define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8)
103
104 struct rtw89_h2creg_sch_tx_en {
105 u32 w0;
106 u32 w1;
107 } __packed;
108
109 #define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16)
110 #define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0)
111 #define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)
112
113 #define RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN GENMASK(23, 16)
114
115 #define RTW89_H2CREG_GET_FEATURE_PART_NUM GENMASK(23, 16)
116
117 #define RTW89_H2CREG_MAX 4
118 #define RTW89_C2HREG_MAX 4
119 #define RTW89_C2HREG_HDR_LEN 2
120 #define RTW89_H2CREG_HDR_LEN 2
121 #define RTW89_C2H_TIMEOUT 1000000
122 #define RTW89_C2H_TIMEOUT_USB 4000
123
124 struct rtw89_mac_c2h_info {
125 u8 id;
126 u8 content_len;
127 u32 timeout;
128 union {
129 u32 c2hreg[RTW89_C2HREG_MAX];
130 struct rtw89_c2hreg_hdr hdr;
131 struct rtw89_c2hreg_phycap phycap;
132 } u;
133 };
134
135 struct rtw89_mac_h2c_info {
136 u8 id;
137 u8 content_len;
138 union {
139 u32 h2creg[RTW89_H2CREG_MAX];
140 struct rtw89_h2creg_hdr hdr;
141 struct rtw89_h2creg_sch_tx_en sch_tx_en;
142 } u;
143 };
144
145 enum rtw89_mac_h2c_type {
146 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0,
147 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD,
148 RTW89_FWCMD_H2CREG_FUNC_FWERR,
149 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE,
150 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM,
151 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN,
152 RTW89_FWCMD_H2CREG_FUNC_WOW_TRX_STOP,
153 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_1,
154 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_2,
155 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_3_REQ,
156 RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL,
157 };
158
159 enum rtw89_mac_c2h_type {
160 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0,
161 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT,
162 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG,
163 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,
164 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,
165 RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK = 0xA,
166 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP_PART1 = 0xC,
167 RTW89_FWCMD_C2HREG_FUNC_PS_LEAVE_ACK = 0xD,
168 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF,
169 };
170
171 enum rtw89_fw_c2h_category {
172 RTW89_C2H_CAT_TEST,
173 RTW89_C2H_CAT_MAC,
174 RTW89_C2H_CAT_OUTSRC,
175 };
176
177 enum rtw89_fw_log_level {
178 RTW89_FW_LOG_LEVEL_OFF,
179 RTW89_FW_LOG_LEVEL_CRT,
180 RTW89_FW_LOG_LEVEL_SER,
181 RTW89_FW_LOG_LEVEL_WARN,
182 RTW89_FW_LOG_LEVEL_LOUD,
183 RTW89_FW_LOG_LEVEL_TR,
184 };
185
186 enum rtw89_fw_log_path {
187 RTW89_FW_LOG_LEVEL_UART,
188 RTW89_FW_LOG_LEVEL_C2H,
189 RTW89_FW_LOG_LEVEL_SNI,
190 };
191
192 enum rtw89_fw_log_comp {
193 RTW89_FW_LOG_COMP_VER,
194 RTW89_FW_LOG_COMP_INIT,
195 RTW89_FW_LOG_COMP_TASK,
196 RTW89_FW_LOG_COMP_CNS,
197 RTW89_FW_LOG_COMP_H2C,
198 RTW89_FW_LOG_COMP_C2H,
199 RTW89_FW_LOG_COMP_TX,
200 RTW89_FW_LOG_COMP_RX,
201 RTW89_FW_LOG_COMP_IPSEC,
202 RTW89_FW_LOG_COMP_TIMER,
203 RTW89_FW_LOG_COMP_DBGPKT,
204 RTW89_FW_LOG_COMP_PS,
205 RTW89_FW_LOG_COMP_ERROR,
206 RTW89_FW_LOG_COMP_WOWLAN,
207 RTW89_FW_LOG_COMP_SECURE_BOOT,
208 RTW89_FW_LOG_COMP_BTC,
209 RTW89_FW_LOG_COMP_BB,
210 RTW89_FW_LOG_COMP_TWT,
211 RTW89_FW_LOG_COMP_RF,
212 RTW89_FW_LOG_COMP_MCC = 20,
213 RTW89_FW_LOG_COMP_MLO = 26,
214 RTW89_FW_LOG_COMP_SCAN = 28,
215 };
216
217 enum rtw89_pkt_offload_op {
218 RTW89_PKT_OFLD_OP_ADD,
219 RTW89_PKT_OFLD_OP_DEL,
220 RTW89_PKT_OFLD_OP_READ,
221
222 NUM_OF_RTW89_PKT_OFFLOAD_OP,
223 };
224
225 #define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) \
226 ((pkt_id) * NUM_OF_RTW89_PKT_OFFLOAD_OP + (pkt_op))
227
228 enum rtw89_scanofld_notify_reason {
229 RTW89_SCAN_DWELL_NOTIFY,
230 RTW89_SCAN_PRE_TX_NOTIFY,
231 RTW89_SCAN_POST_TX_NOTIFY,
232 RTW89_SCAN_ENTER_CH_NOTIFY,
233 RTW89_SCAN_LEAVE_CH_NOTIFY,
234 RTW89_SCAN_END_SCAN_NOTIFY,
235 RTW89_SCAN_REPORT_NOTIFY,
236 RTW89_SCAN_CHKPT_NOTIFY,
237 RTW89_SCAN_ENTER_OP_NOTIFY,
238 RTW89_SCAN_LEAVE_OP_NOTIFY,
239 };
240
241 enum rtw89_scanofld_status {
242 RTW89_SCAN_STATUS_NOTIFY,
243 RTW89_SCAN_STATUS_SUCCESS,
244 RTW89_SCAN_STATUS_FAIL,
245 };
246
247 enum rtw89_chan_type {
248 RTW89_CHAN_OPERATE = 0,
249 RTW89_CHAN_ACTIVE,
250 RTW89_CHAN_DFS,
251 RTW89_CHAN_EXTRA_OP,
252 };
253
254 enum rtw89_p2pps_action {
255 RTW89_P2P_ACT_INIT = 0,
256 RTW89_P2P_ACT_UPDATE = 1,
257 RTW89_P2P_ACT_REMOVE = 2,
258 RTW89_P2P_ACT_TERMINATE = 3,
259 };
260
261 #define RTW89_DEFAULT_CQM_HYST 4
262 #define RTW89_DEFAULT_CQM_THOLD -70
263
264 enum rtw89_bcn_fltr_offload_mode {
265 RTW89_BCN_FLTR_OFFLOAD_MODE_0 = 0,
266 RTW89_BCN_FLTR_OFFLOAD_MODE_1,
267 RTW89_BCN_FLTR_OFFLOAD_MODE_2,
268 RTW89_BCN_FLTR_OFFLOAD_MODE_3,
269
270 RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT = RTW89_BCN_FLTR_OFFLOAD_MODE_0,
271 };
272
273 enum rtw89_bcn_fltr_type {
274 RTW89_BCN_FLTR_BEACON_LOSS,
275 RTW89_BCN_FLTR_RSSI,
276 RTW89_BCN_FLTR_NOTIFY,
277 };
278
279 enum rtw89_bcn_fltr_rssi_event {
280 RTW89_BCN_FLTR_RSSI_NOT_CHANGED,
281 RTW89_BCN_FLTR_RSSI_HIGH,
282 RTW89_BCN_FLTR_RSSI_LOW,
283 };
284
285 #define FWDL_SECTION_MAX_NUM 10
286 #define FWDL_SECTION_CHKSUM_LEN 8
287 #define FWDL_SECTION_PER_PKT_LEN 2020
288
289 struct rtw89_fw_hdr_section_info {
290 u8 redl;
291 const u8 *addr;
292 u32 len;
293 u32 len_override;
294 u32 dladdr;
295 u32 mssc;
296 u8 type;
297 bool ignore;
298 const u8 *key_addr;
299 u32 key_len;
300 u32 key_idx;
301 };
302
303 struct rtw89_fw_bin_info {
304 u8 section_num;
305 u32 part_size;
306 u32 hdr_len;
307 bool dynamic_hdr_en;
308 u32 dynamic_hdr_len;
309 u8 idmem_share_mode;
310 bool dsp_checksum;
311 bool secure_section_exist;
312 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];
313 };
314
315 struct rtw89_fw_macid_pause_grp {
316 __le32 pause_grp[4];
317 __le32 mask_grp[4];
318 } __packed;
319
320 struct rtw89_fw_macid_pause_sleep_grp {
321 struct {
322 __le32 pause_grp[4];
323 __le32 pause_mask_grp[4];
324 __le32 sleep_grp[4];
325 __le32 sleep_mask_grp[4];
326 } __packed n[4];
327 } __packed;
328
329 #define RTW89_H2C_MAX_SIZE 2048
330 #define RTW89_CHANNEL_TIME 45
331 #define RTW89_CHANNEL_TIME_6G 20
332 #define RTW89_CHANNEL_TIME_EXTRA_OP 30
333 #define RTW89_DFS_CHAN_TIME 105
334 #define RTW89_OFF_CHAN_TIME 100
335 #define RTW89_P2P_CHAN_TIME 105
336 #define RTW89_DWELL_TIME 20
337 #define RTW89_DWELL_TIME_6G 10
338 #define RTW89_SCAN_WIDTH 0
339 #define RTW89_SCANOFLD_MAX_SSID 8
340 #define RTW89_SCANOFLD_MAX_IE_LEN 512
341 #define RTW89_SCANOFLD_PKT_NONE 0xFF
342 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F
343 #define RTW89_CHAN_INVALID 0xFF
344 #define RTW89_MAC_CHINFO_SIZE 28
345 #define RTW89_MAC_CHINFO_SIZE_BE 32
346 #define RTW89_SCAN_LIST_GUARD 4
347 #define RTW89_SCAN_LIST_LIMIT(size) \
348 ((RTW89_H2C_MAX_SIZE / (size)) - RTW89_SCAN_LIST_GUARD)
349 #define RTW89_SCAN_LIST_LIMIT_AX RTW89_SCAN_LIST_LIMIT(RTW89_MAC_CHINFO_SIZE)
350 #define RTW89_SCAN_LIST_LIMIT_BE RTW89_SCAN_LIST_LIMIT(RTW89_MAC_CHINFO_SIZE_BE)
351
352 #define RTW89_BCN_LOSS_CNT 60
353
354 struct rtw89_mac_chinfo_ax {
355 u8 period;
356 u8 dwell_time;
357 u8 central_ch;
358 u8 pri_ch;
359 u8 bw:3;
360 u8 notify_action:5;
361 u8 num_pkt:4;
362 u8 tx_pkt:1;
363 u8 pause_data:1;
364 u8 ch_band:2;
365 u8 probe_id;
366 u8 dfs_ch:1;
367 u8 tx_null:1;
368 u8 rand_seq_num:1;
369 u8 cfg_tx_pwr:1;
370 u8 macid_tx: 1;
371 u8 rsvd0: 3;
372 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
373 u16 tx_pwr_idx;
374 u8 rsvd1;
375 struct list_head list;
376 bool is_psc;
377 };
378
379 struct rtw89_mac_chinfo_be {
380 u8 period;
381 u8 dwell_time;
382 u8 central_ch;
383 u8 pri_ch;
384 u8 bw:3;
385 u8 ch_band:2;
386 u8 dfs_ch:1;
387 u8 pause_data:1;
388 u8 tx_null:1;
389 u8 rand_seq_num:1;
390 u8 notify_action:5;
391 u8 probe_id;
392 u8 leave_crit;
393 u8 chkpt_timer;
394 u8 leave_time;
395 u8 leave_th;
396 u16 tx_pkt_ctrl;
397 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
398 u8 sw_def;
399 u16 fw_probe0_ssids;
400 u16 fw_probe0_shortssids;
401 u16 fw_probe0_bssids;
402
403 struct list_head list;
404 bool is_psc;
405 };
406
407 struct rtw89_pktofld_info {
408 struct list_head list;
409 u8 id;
410 bool wildcard_6ghz;
411
412 /* Below fields are for WiFi 6 chips 6 GHz RNR use only */
413 u8 ssid[IEEE80211_MAX_SSID_LEN];
414 u8 ssid_len;
415 u8 bssid[ETH_ALEN];
416 u16 channel_6ghz;
417 bool cancel;
418 };
419
420 struct rtw89_h2c_ra {
421 __le32 w0;
422 __le32 w1;
423 __le32 w2;
424 __le32 w3;
425 } __packed;
426
427 #define RTW89_H2C_RA_W0_IS_DIS BIT(0)
428 #define RTW89_H2C_RA_W0_MODE GENMASK(5, 1)
429 #define RTW89_H2C_RA_W0_BW_CAP GENMASK(7, 6)
430 #define RTW89_H2C_RA_W0_MACID GENMASK(15, 8)
431 #define RTW89_H2C_RA_W0_DCM BIT(16)
432 #define RTW89_H2C_RA_W0_ER BIT(17)
433 #define RTW89_H2C_RA_W0_INIT_RATE_LV GENMASK(19, 18)
434 #define RTW89_H2C_RA_W0_UPD_ALL BIT(20)
435 #define RTW89_H2C_RA_W0_SGI BIT(21)
436 #define RTW89_H2C_RA_W0_LDPC BIT(22)
437 #define RTW89_H2C_RA_W0_STBC BIT(23)
438 #define RTW89_H2C_RA_W0_SS_NUM GENMASK(26, 24)
439 #define RTW89_H2C_RA_W0_GILTF GENMASK(29, 27)
440 #define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK BIT(30)
441 #define RTW89_H2C_RA_W0_UPD_MASK BIT(31)
442 #define RTW89_H2C_RA_W1_RAMASK_LO32 GENMASK(31, 0)
443 #define RTW89_H2C_RA_W2_RAMASK_HI32 GENMASK(30, 0)
444 #define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31)
445 #define RTW89_H2C_RA_W3_BAND_NUM GENMASK(7, 0)
446 #define RTW89_H2C_RA_W3_RA_CSI_RATE_EN BIT(8)
447 #define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN BIT(9)
448 #define RTW89_H2C_RA_W3_CR_TBL_SEL BIT(10)
449 #define RTW89_H2C_RA_W3_FIX_GILTF_EN BIT(11)
450 #define RTW89_H2C_RA_W3_FIX_GILTF GENMASK(14, 12)
451 #define RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX GENMASK(23, 16)
452 #define RTW89_H2C_RA_W3_FIXED_CSI_MODE GENMASK(25, 24)
453 #define RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF GENMASK(28, 26)
454 #define RTW89_H2C_RA_W3_FIXED_CSI_BW GENMASK(31, 29)
455 #define RTW89_H2C_RA_V1_W3_PARTIAL_BW_SU_ER BIT(15)
456 #define RTW89_H2C_RA_V1_W3_FIXED_CSI_RATE_L GENMASK(23, 16)
457 #define RTW89_H2C_RA_V1_W3_IS_NOISY BIT(24)
458 #define RTW89_H2C_RA_V1_W3_PSRA_EN BIT(25)
459 #define RTW89_H2C_RA_V1_W3_MACID_MSB GENMASK(28, 27)
460 #define RTW89_H2C_RA_V1_W3_BAND GENMASK(30, 29)
461 #define RTW89_H2C_RA_V1_W3_NEW_DBGREG BIT(31)
462
463 struct rtw89_h2c_ra_v1 {
464 struct rtw89_h2c_ra v0;
465 __le32 w4;
466 __le32 w5;
467 } __packed;
468
469 #define RTW89_H2C_RA_V1_W4_MODE_EHT GENMASK(6, 0)
470 #define RTW89_H2C_RA_V1_W4_BW_EHT GENMASK(10, 8)
471 #define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16)
472 #define RTW89_H2C_RA_V1_W5_RAMASK_UHH16 GENMASK(15, 0)
473
474 struct rtw89_h2c_ra_tx_history {
475 __le32 w0;
476 } __packed;
477
478 #define RTW89_H2C_RA_TX_HISTORY_W0_MACID GENMASK(15, 0)
479 #define RTW89_H2C_RA_TX_HISTORY_W0_PER_PPDU GENMASK(23, 16)
480
481 struct rtw89_h2c_ra_phy_ch_rpt {
482 __le32 w0;
483 __le32 w1;
484 __le32 w2;
485 __le32 w3;
486 } __packed;
487
488 #define RTW89_H2C_RA_PHY_CH_RPT_W1_RPT_TX_COUNT BIT(10)
489
490 struct rtw89_h2c_ra_drv_ctrl_fw {
491 __le32 w0;
492 } __packed;
493
494 #define RTW89_H2C_RA_DRV_CTRL_FW_W0_RPT_TX_COUNT BIT(13)
495
RTW89_SET_FWCMD_SEC_IDX(void * cmd,u32 val)496 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)
497 {
498 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));
499 }
500
RTW89_SET_FWCMD_SEC_OFFSET(void * cmd,u32 val)501 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val)
502 {
503 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
504 }
505
RTW89_SET_FWCMD_SEC_LEN(void * cmd,u32 val)506 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val)
507 {
508 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16));
509 }
510
RTW89_SET_FWCMD_SEC_TYPE(void * cmd,u32 val)511 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val)
512 {
513 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0));
514 }
515
RTW89_SET_FWCMD_SEC_EXT_KEY(void * cmd,u32 val)516 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val)
517 {
518 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4));
519 }
520
RTW89_SET_FWCMD_SEC_SPP_MODE(void * cmd,u32 val)521 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val)
522 {
523 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5));
524 }
525
RTW89_SET_FWCMD_SEC_KEY0(void * cmd,u32 val)526 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val)
527 {
528 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0));
529 }
530
RTW89_SET_FWCMD_SEC_KEY1(void * cmd,u32 val)531 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val)
532 {
533 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0));
534 }
535
RTW89_SET_FWCMD_SEC_KEY2(void * cmd,u32 val)536 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val)
537 {
538 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0));
539 }
540
RTW89_SET_FWCMD_SEC_KEY3(void * cmd,u32 val)541 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val)
542 {
543 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0));
544 }
545
RTW89_SET_EDCA_SEL(void * cmd,u32 val)546 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val)
547 {
548 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0));
549 }
550
RTW89_SET_EDCA_BAND(void * cmd,u32 val)551 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val)
552 {
553 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3));
554 }
555
RTW89_SET_EDCA_WMM(void * cmd,u32 val)556 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val)
557 {
558 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4));
559 }
560
RTW89_SET_EDCA_AC(void * cmd,u32 val)561 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val)
562 {
563 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5));
564 }
565
RTW89_SET_EDCA_PARAM(void * cmd,u32 val)566 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val)
567 {
568 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0));
569 }
570 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)
571 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)
572 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)
573 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)
574
575 #define FWDL_SECURITY_SECTION_TYPE 9
576 #define FWDL_SECURITY_SIGLEN 512
577 #define FWDL_SECURITY_CHKSUM_LEN 8
578
579 struct rtw89_fw_dynhdr_sec {
580 __le32 w0;
581 u8 content[];
582 } __packed;
583
584 struct rtw89_fw_dynhdr_hdr {
585 __le32 hdr_len;
586 __le32 setcion_count;
587 /* struct rtw89_fw_dynhdr_sec (nested flexible structures) */
588 } __packed;
589
590 struct rtw89_fw_hdr_section {
591 __le32 w0;
592 __le32 w1;
593 __le32 w2;
594 __le32 w3;
595 } __packed;
596
597 #define FWSECTION_HDR_W0_DL_ADDR GENMASK(31, 0)
598 #define FWSECTION_HDR_W1_METADATA GENMASK(31, 24)
599 #define FWSECTION_HDR_W1_SECTIONTYPE GENMASK(27, 24)
600 #define FWSECTION_HDR_W1_SEC_SIZE GENMASK(23, 0)
601 #define FWSECTION_HDR_W1_CHECKSUM BIT(28)
602 #define FWSECTION_HDR_W1_REDL BIT(29)
603 #define FWSECTION_HDR_W2_MSSC GENMASK(31, 0)
604
605 struct rtw89_fw_hdr {
606 __le32 w0;
607 __le32 w1;
608 __le32 w2;
609 __le32 w3;
610 __le32 w4;
611 __le32 w5;
612 __le32 w6;
613 __le32 w7;
614 struct rtw89_fw_hdr_section sections[];
615 /* struct rtw89_fw_dynhdr_hdr (optional) */
616 } __packed;
617
618 #define FW_HDR_W1_MAJOR_VERSION GENMASK(7, 0)
619 #define FW_HDR_W1_MINOR_VERSION GENMASK(15, 8)
620 #define FW_HDR_W1_SUBVERSION GENMASK(23, 16)
621 #define FW_HDR_W1_SUBINDEX GENMASK(31, 24)
622 #define FW_HDR_W2_COMMITID GENMASK(31, 0)
623 #define FW_HDR_W3_LEN GENMASK(23, 16)
624 #define FW_HDR_W3_HDR_VER GENMASK(31, 24)
625 #define FW_HDR_W4_MONTH GENMASK(7, 0)
626 #define FW_HDR_W4_DATE GENMASK(15, 8)
627 #define FW_HDR_W4_HOUR GENMASK(23, 16)
628 #define FW_HDR_W4_MIN GENMASK(31, 24)
629 #define FW_HDR_W5_YEAR GENMASK(31, 0)
630 #define FW_HDR_W6_SEC_NUM GENMASK(15, 8)
631 #define FW_HDR_W7_PART_SIZE GENMASK(15, 0)
632 #define FW_HDR_W7_DYN_HDR BIT(16)
633 #define FW_HDR_W7_IDMEM_SHARE_MODE GENMASK(21, 18)
634 #define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24)
635
636 struct rtw89_fw_hdr_section_v1 {
637 __le32 w0;
638 __le32 w1;
639 __le32 w2;
640 __le32 w3;
641 } __packed;
642
643 #define FWSECTION_HDR_V1_W0_DL_ADDR GENMASK(31, 0)
644 #define FWSECTION_HDR_V1_W1_METADATA GENMASK(31, 24)
645 #define FWSECTION_HDR_V1_W1_SECTIONTYPE GENMASK(27, 24)
646 #define FWSECTION_HDR_V1_W1_SEC_SIZE GENMASK(23, 0)
647 #define FWSECTION_HDR_V1_W1_CHECKSUM BIT(28)
648 #define FWSECTION_HDR_V1_W1_REDL BIT(29)
649 #define FWSECTION_HDR_V1_W2_MSSC GENMASK(7, 0)
650 #define FORMATTED_MSSC 0xFF
651 #define FORMATTED_MSSC_MASK GENMASK(7, 0)
652 #define FWSECTION_HDR_V1_W2_BBMCU_IDX GENMASK(27, 24)
653
654 struct rtw89_fw_hdr_v1 {
655 __le32 w0;
656 __le32 w1;
657 __le32 w2;
658 __le32 w3;
659 __le32 w4;
660 __le32 w5;
661 __le32 w6;
662 __le32 w7;
663 __le32 w8;
664 __le32 w9;
665 __le32 w10;
666 __le32 w11;
667 struct rtw89_fw_hdr_section_v1 sections[];
668 } __packed;
669
670 #define FW_HDR_V1_W1_MAJOR_VERSION GENMASK(7, 0)
671 #define FW_HDR_V1_W1_MINOR_VERSION GENMASK(15, 8)
672 #define FW_HDR_V1_W1_SUBVERSION GENMASK(23, 16)
673 #define FW_HDR_V1_W1_SUBINDEX GENMASK(31, 24)
674 #define FW_HDR_V1_W2_COMMITID GENMASK(31, 0)
675 #define FW_HDR_V1_W3_CMD_VERSERION GENMASK(23, 16)
676 #define FW_HDR_V1_W3_HDR_VER GENMASK(31, 24)
677 #define FW_HDR_V1_W4_MONTH GENMASK(7, 0)
678 #define FW_HDR_V1_W4_DATE GENMASK(15, 8)
679 #define FW_HDR_V1_W4_HOUR GENMASK(23, 16)
680 #define FW_HDR_V1_W4_MIN GENMASK(31, 24)
681 #define FW_HDR_V1_W5_YEAR GENMASK(15, 0)
682 #define FW_HDR_V1_W5_HDR_SIZE GENMASK(31, 16)
683 #define FW_HDR_V1_W6_SEC_NUM GENMASK(15, 8)
684 #define FW_HDR_V1_W6_DSP_CHKSUM BIT(24)
685 #define FW_HDR_V1_W7_PART_SIZE GENMASK(15, 0)
686 #define FW_HDR_V1_W7_DYN_HDR BIT(16)
687 #define FW_HDR_V1_W7_IDMEM_SHARE_MODE GENMASK(21, 18)
688
689 enum rtw89_fw_mss_pool_rmp_tbl_type {
690 MSS_POOL_RMP_TBL_BITMASK = 0x0,
691 MSS_POOL_RMP_TBL_RECORD = 0x1,
692 };
693
694 #define FWDL_MSS_POOL_DEFKEYSETS_SIZE 8
695
696 struct rtw89_fw_mss_pool_hdr {
697 u8 signature[8]; /* equal to mss_signature[] */
698 __le32 rmp_tbl_offset;
699 __le32 key_raw_offset;
700 u8 defen;
701 u8 rsvd[3];
702 u8 rmpfmt; /* enum rtw89_fw_mss_pool_rmp_tbl_type */
703 u8 mssdev_max;
704 __le16 keypair_num;
705 __le16 msscust_max;
706 __le16 msskey_num_max;
707 __le32 rsvd3;
708 u8 rmp_tbl[];
709 } __packed;
710
711 union rtw89_fw_section_mssc_content {
712 struct {
713 u8 pad[0x20];
714 u8 bit_in_chip_list;
715 u8 ver;
716 } __packed blacklist;
717 struct {
718 u8 pad[58];
719 __le32 v;
720 } __packed sb_sel_ver;
721 struct {
722 u8 pad[60];
723 __le16 v;
724 } __packed key_sign_len;
725 } __packed;
726
727 struct rtw89_fw_blacklist {
728 u8 ver;
729 u8 list[32];
730 };
731
732 extern const struct rtw89_fw_blacklist rtw89_fw_blacklist_default;
733
SET_CTRL_INFO_MACID(void * table,u32 val)734 static inline void SET_CTRL_INFO_MACID(void *table, u32 val)
735 {
736 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
737 }
738
SET_CTRL_INFO_OPERATION(void * table,u32 val)739 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val)
740 {
741 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
742 }
743 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)
SET_CMC_TBL_DATARATE(void * table,u32 val)744 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val)
745 {
746 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0));
747 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE,
748 GENMASK(8, 0));
749 }
750 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
SET_CMC_TBL_FORCE_TXOP(void * table,u32 val)751 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val)
752 {
753 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9));
754 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP,
755 BIT(9));
756 }
757 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0)
SET_CMC_TBL_DATA_BW(void * table,u32 val)758 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val)
759 {
760 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10));
761 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW,
762 GENMASK(11, 10));
763 }
764 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0)
SET_CMC_TBL_DATA_GI_LTF(void * table,u32 val)765 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val)
766 {
767 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12));
768 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF,
769 GENMASK(14, 12));
770 }
771 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
SET_CMC_TBL_DARF_TC_INDEX(void * table,u32 val)772 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val)
773 {
774 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
775 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX,
776 BIT(15));
777 }
778 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0)
SET_CMC_TBL_ARFR_CTRL(void * table,u32 val)779 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val)
780 {
781 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16));
782 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL,
783 GENMASK(19, 16));
784 }
785 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
SET_CMC_TBL_ACQ_RPT_EN(void * table,u32 val)786 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val)
787 {
788 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20));
789 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN,
790 BIT(20));
791 }
792 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
SET_CMC_TBL_MGQ_RPT_EN(void * table,u32 val)793 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val)
794 {
795 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21));
796 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN,
797 BIT(21));
798 }
799 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
SET_CMC_TBL_ULQ_RPT_EN(void * table,u32 val)800 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val)
801 {
802 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22));
803 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN,
804 BIT(22));
805 }
806 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
SET_CMC_TBL_TWTQ_RPT_EN(void * table,u32 val)807 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val)
808 {
809 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23));
810 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN,
811 BIT(23));
812 }
813 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
SET_CMC_TBL_DISRTSFB(void * table,u32 val)814 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val)
815 {
816 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25));
817 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB,
818 BIT(25));
819 }
820 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
SET_CMC_TBL_DISDATAFB(void * table,u32 val)821 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val)
822 {
823 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26));
824 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB,
825 BIT(26));
826 }
827 #define SET_CMC_TBL_MASK_TRYRATE BIT(0)
SET_CMC_TBL_TRYRATE(void * table,u32 val)828 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val)
829 {
830 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27));
831 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE,
832 BIT(27));
833 }
834 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0)
SET_CMC_TBL_AMPDU_DENSITY(void * table,u32 val)835 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val)
836 {
837 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28));
838 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY,
839 GENMASK(31, 28));
840 }
841 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)
SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void * table,u32 val)842 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val)
843 {
844 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0));
845 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE,
846 GENMASK(8, 0));
847 }
848 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
SET_CMC_TBL_AMPDU_TIME_SEL(void * table,u32 val)849 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val)
850 {
851 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9));
852 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL,
853 BIT(9));
854 }
855 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
SET_CMC_TBL_AMPDU_LEN_SEL(void * table,u32 val)856 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val)
857 {
858 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10));
859 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL,
860 BIT(10));
861 }
862 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void * table,u32 val)863 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val)
864 {
865 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11));
866 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL,
867 BIT(11));
868 }
869 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0)
SET_CMC_TBL_RTS_TXCNT_LMT(void * table,u32 val)870 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val)
871 {
872 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12));
873 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT,
874 GENMASK(15, 12));
875 }
876 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)
SET_CMC_TBL_RTSRATE(void * table,u32 val)877 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val)
878 {
879 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16));
880 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE,
881 GENMASK(24, 16));
882 }
883 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
SET_CMC_TBL_VCS_STBC(void * table,u32 val)884 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val)
885 {
886 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27));
887 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC,
888 BIT(27));
889 }
890 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0)
SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void * table,u32 val)891 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val)
892 {
893 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28));
894 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE,
895 GENMASK(31, 28));
896 }
897 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0)
SET_CMC_TBL_DATA_TX_CNT_LMT(void * table,u32 val)898 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val)
899 {
900 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0));
901 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT,
902 GENMASK(5, 0));
903 }
904 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void * table,u32 val)905 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val)
906 {
907 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6));
908 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL,
909 BIT(6));
910 }
911 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
SET_CMC_TBL_MAX_AGG_NUM_SEL(void * table,u32 val)912 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val)
913 {
914 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7));
915 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL,
916 BIT(7));
917 }
918 #define SET_CMC_TBL_MASK_RTS_EN BIT(0)
SET_CMC_TBL_RTS_EN(void * table,u32 val)919 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val)
920 {
921 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8));
922 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN,
923 BIT(8));
924 }
925 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
SET_CMC_TBL_CTS2SELF_EN(void * table,u32 val)926 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val)
927 {
928 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9));
929 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN,
930 BIT(9));
931 }
932 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0)
SET_CMC_TBL_CCA_RTS(void * table,u32 val)933 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val)
934 {
935 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10));
936 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS,
937 GENMASK(11, 10));
938 }
939 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
SET_CMC_TBL_HW_RTS_EN(void * table,u32 val)940 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val)
941 {
942 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12));
943 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN,
944 BIT(12));
945 }
946 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0)
SET_CMC_TBL_RTS_DROP_DATA_MODE(void * table,u32 val)947 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val)
948 {
949 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13));
950 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE,
951 GENMASK(14, 13));
952 }
953 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0)
SET_CMC_TBL_AMPDU_MAX_LEN(void * table,u32 val)954 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val)
955 {
956 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16));
957 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN,
958 GENMASK(26, 16));
959 }
960 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
SET_CMC_TBL_UL_MU_DIS(void * table,u32 val)961 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val)
962 {
963 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
964 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS,
965 BIT(27));
966 }
967 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0)
SET_CMC_TBL_AMPDU_MAX_TIME(void * table,u32 val)968 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val)
969 {
970 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28));
971 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME,
972 GENMASK(31, 28));
973 }
974 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)
SET_CMC_TBL_MAX_AGG_NUM(void * table,u32 val)975 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val)
976 {
977 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0));
978 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM,
979 GENMASK(7, 0));
980 }
981 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0)
SET_CMC_TBL_BA_BMAP(void * table,u32 val)982 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val)
983 {
984 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8));
985 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP,
986 GENMASK(9, 8));
987 }
988 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_VO_LFTIME_SEL(void * table,u32 val)989 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val)
990 {
991 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16));
992 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL,
993 GENMASK(18, 16));
994 }
995 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_VI_LFTIME_SEL(void * table,u32 val)996 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val)
997 {
998 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19));
999 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL,
1000 GENMASK(21, 19));
1001 }
1002 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_BE_LFTIME_SEL(void * table,u32 val)1003 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val)
1004 {
1005 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22));
1006 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL,
1007 GENMASK(24, 22));
1008 }
1009 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_BK_LFTIME_SEL(void * table,u32 val)1010 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val)
1011 {
1012 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25));
1013 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL,
1014 GENMASK(27, 25));
1015 }
1016 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0)
SET_CMC_TBL_SECTYPE(void * table,u32 val)1017 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val)
1018 {
1019 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28));
1020 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE,
1021 GENMASK(31, 28));
1022 }
1023 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0)
SET_CMC_TBL_MULTI_PORT_ID(void * table,u32 val)1024 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val)
1025 {
1026 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0));
1027 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID,
1028 GENMASK(2, 0));
1029 }
1030 #define SET_CMC_TBL_MASK_BMC BIT(0)
SET_CMC_TBL_BMC(void * table,u32 val)1031 static inline void SET_CMC_TBL_BMC(void *table, u32 val)
1032 {
1033 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3));
1034 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC,
1035 BIT(3));
1036 }
1037 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0)
SET_CMC_TBL_MBSSID(void * table,u32 val)1038 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val)
1039 {
1040 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4));
1041 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID,
1042 GENMASK(7, 4));
1043 }
1044 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
SET_CMC_TBL_NAVUSEHDR(void * table,u32 val)1045 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val)
1046 {
1047 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
1048 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR,
1049 BIT(8));
1050 }
1051 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0)
SET_CMC_TBL_TXPWR_MODE(void * table,u32 val)1052 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val)
1053 {
1054 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9));
1055 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE,
1056 GENMASK(11, 9));
1057 }
1058 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
SET_CMC_TBL_DATA_DCM(void * table,u32 val)1059 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val)
1060 {
1061 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12));
1062 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM,
1063 BIT(12));
1064 }
1065 #define SET_CMC_TBL_MASK_DATA_ER BIT(0)
SET_CMC_TBL_DATA_ER(void * table,u32 val)1066 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val)
1067 {
1068 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13));
1069 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER,
1070 BIT(13));
1071 }
1072 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
SET_CMC_TBL_DATA_LDPC(void * table,u32 val)1073 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val)
1074 {
1075 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14));
1076 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC,
1077 BIT(14));
1078 }
1079 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
SET_CMC_TBL_DATA_STBC(void * table,u32 val)1080 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val)
1081 {
1082 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
1083 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC,
1084 BIT(15));
1085 }
1086 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
SET_CMC_TBL_A_CTRL_BQR(void * table,u32 val)1087 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val)
1088 {
1089 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16));
1090 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR,
1091 BIT(16));
1092 }
1093 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
SET_CMC_TBL_A_CTRL_UPH(void * table,u32 val)1094 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val)
1095 {
1096 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17));
1097 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH,
1098 BIT(17));
1099 }
1100 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
SET_CMC_TBL_A_CTRL_BSR(void * table,u32 val)1101 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val)
1102 {
1103 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18));
1104 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR,
1105 BIT(18));
1106 }
1107 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
SET_CMC_TBL_A_CTRL_CAS(void * table,u32 val)1108 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val)
1109 {
1110 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19));
1111 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS,
1112 BIT(19));
1113 }
1114 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
SET_CMC_TBL_DATA_BW_ER(void * table,u32 val)1115 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val)
1116 {
1117 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20));
1118 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER,
1119 BIT(20));
1120 }
1121 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
SET_CMC_TBL_LSIG_TXOP_EN(void * table,u32 val)1122 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val)
1123 {
1124 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21));
1125 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN,
1126 BIT(21));
1127 }
1128 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
SET_CMC_TBL_CTRL_CNT_VLD(void * table,u32 val)1129 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val)
1130 {
1131 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27));
1132 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD,
1133 BIT(27));
1134 }
1135 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0)
SET_CMC_TBL_CTRL_CNT(void * table,u32 val)1136 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val)
1137 {
1138 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28));
1139 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT,
1140 GENMASK(31, 28));
1141 }
1142 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)
SET_CMC_TBL_RESP_REF_RATE(void * table,u32 val)1143 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val)
1144 {
1145 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0));
1146 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE,
1147 GENMASK(8, 0));
1148 }
1149 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
SET_CMC_TBL_ALL_ACK_SUPPORT(void * table,u32 val)1150 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val)
1151 {
1152 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12));
1153 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT,
1154 BIT(12));
1155 }
1156 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void * table,u32 val)1157 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val)
1158 {
1159 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13));
1160 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT,
1161 BIT(13));
1162 }
1163 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0)
SET_CMC_TBL_NTX_PATH_EN(void * table,u32 val)1164 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val)
1165 {
1166 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16));
1167 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN,
1168 GENMASK(19, 16));
1169 }
1170 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_A(void * table,u32 val)1171 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val)
1172 {
1173 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20));
1174 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A,
1175 GENMASK(21, 20));
1176 }
1177 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_B(void * table,u32 val)1178 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val)
1179 {
1180 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22));
1181 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B,
1182 GENMASK(23, 22));
1183 }
1184 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_C(void * table,u32 val)1185 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val)
1186 {
1187 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24));
1188 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C,
1189 GENMASK(25, 24));
1190 }
1191 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_D(void * table,u32 val)1192 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val)
1193 {
1194 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26));
1195 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D,
1196 GENMASK(27, 26));
1197 }
1198 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
SET_CMC_TBL_ANTSEL_A(void * table,u32 val)1199 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val)
1200 {
1201 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28));
1202 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A,
1203 BIT(28));
1204 }
1205 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
SET_CMC_TBL_ANTSEL_B(void * table,u32 val)1206 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val)
1207 {
1208 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29));
1209 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B,
1210 BIT(29));
1211 }
1212 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
SET_CMC_TBL_ANTSEL_C(void * table,u32 val)1213 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val)
1214 {
1215 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30));
1216 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C,
1217 BIT(30));
1218 }
1219 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
SET_CMC_TBL_ANTSEL_D(void * table,u32 val)1220 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val)
1221 {
1222 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31));
1223 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D,
1224 BIT(31));
1225 }
1226
1227 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0)
SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void * table,u32 val)1228 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val)
1229 {
1230 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0));
1231 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1232 GENMASK(1, 0));
1233 }
1234
SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void * table,u32 val)1235 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val)
1236 {
1237 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2));
1238 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1239 GENMASK(3, 2));
1240 }
1241
SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void * table,u32 val)1242 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val)
1243 {
1244 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4));
1245 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1246 GENMASK(5, 4));
1247 }
1248
SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void * table,u32 val)1249 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val)
1250 {
1251 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6));
1252 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1253 GENMASK(7, 6));
1254 }
1255
1256 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)
SET_CMC_TBL_ADDR_CAM_INDEX(void * table,u32 val)1257 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val)
1258 {
1259 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1260 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX,
1261 GENMASK(7, 0));
1262 }
1263 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)
SET_CMC_TBL_PAID(void * table,u32 val)1264 static inline void SET_CMC_TBL_PAID(void *table, u32 val)
1265 {
1266 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8));
1267 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID,
1268 GENMASK(16, 8));
1269 }
1270 #define SET_CMC_TBL_MASK_ULDL BIT(0)
SET_CMC_TBL_ULDL(void * table,u32 val)1271 static inline void SET_CMC_TBL_ULDL(void *table, u32 val)
1272 {
1273 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17));
1274 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL,
1275 BIT(17));
1276 }
1277 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0)
SET_CMC_TBL_DOPPLER_CTRL(void * table,u32 val)1278 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val)
1279 {
1280 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18));
1281 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL,
1282 GENMASK(19, 18));
1283 }
SET_CMC_TBL_NOMINAL_PKT_PADDING(void * table,u32 val)1284 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val)
1285 {
1286 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20));
1287 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1288 GENMASK(21, 20));
1289 }
1290
SET_CMC_TBL_NOMINAL_PKT_PADDING40(void * table,u32 val)1291 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val)
1292 {
1293 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22));
1294 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1295 GENMASK(23, 22));
1296 }
1297 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0)
SET_CMC_TBL_TXPWR_TOLERENCE(void * table,u32 val)1298 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val)
1299 {
1300 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24));
1301 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE,
1302 GENMASK(27, 24));
1303 }
1304
SET_CMC_TBL_NOMINAL_PKT_PADDING80(void * table,u32 val)1305 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val)
1306 {
1307 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30));
1308 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1309 GENMASK(31, 30));
1310 }
1311 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0)
SET_CMC_TBL_NC(void * table,u32 val)1312 static inline void SET_CMC_TBL_NC(void *table, u32 val)
1313 {
1314 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0));
1315 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC,
1316 GENMASK(2, 0));
1317 }
1318 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0)
SET_CMC_TBL_NR(void * table,u32 val)1319 static inline void SET_CMC_TBL_NR(void *table, u32 val)
1320 {
1321 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3));
1322 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR,
1323 GENMASK(5, 3));
1324 }
1325 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0)
SET_CMC_TBL_NG(void * table,u32 val)1326 static inline void SET_CMC_TBL_NG(void *table, u32 val)
1327 {
1328 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6));
1329 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG,
1330 GENMASK(7, 6));
1331 }
1332 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0)
SET_CMC_TBL_CB(void * table,u32 val)1333 static inline void SET_CMC_TBL_CB(void *table, u32 val)
1334 {
1335 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8));
1336 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB,
1337 GENMASK(9, 8));
1338 }
1339 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0)
SET_CMC_TBL_CS(void * table,u32 val)1340 static inline void SET_CMC_TBL_CS(void *table, u32 val)
1341 {
1342 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10));
1343 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS,
1344 GENMASK(11, 10));
1345 }
1346 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
SET_CMC_TBL_CSI_TXBF_EN(void * table,u32 val)1347 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val)
1348 {
1349 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12));
1350 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN,
1351 BIT(12));
1352 }
1353 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
SET_CMC_TBL_CSI_STBC_EN(void * table,u32 val)1354 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val)
1355 {
1356 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13));
1357 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN,
1358 BIT(13));
1359 }
1360 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
SET_CMC_TBL_CSI_LDPC_EN(void * table,u32 val)1361 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val)
1362 {
1363 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14));
1364 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN,
1365 BIT(14));
1366 }
1367 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
SET_CMC_TBL_CSI_PARA_EN(void * table,u32 val)1368 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val)
1369 {
1370 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15));
1371 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN,
1372 BIT(15));
1373 }
1374 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)
SET_CMC_TBL_CSI_FIX_RATE(void * table,u32 val)1375 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val)
1376 {
1377 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16));
1378 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE,
1379 GENMASK(24, 16));
1380 }
1381 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0)
SET_CMC_TBL_CSI_GI_LTF(void * table,u32 val)1382 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val)
1383 {
1384 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25));
1385 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF,
1386 GENMASK(27, 25));
1387 }
1388
SET_CMC_TBL_NOMINAL_PKT_PADDING160(void * table,u32 val)1389 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val)
1390 {
1391 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28));
1392 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1393 GENMASK(29, 28));
1394 }
1395
1396 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0)
SET_CMC_TBL_CSI_BW(void * table,u32 val)1397 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val)
1398 {
1399 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30));
1400 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW,
1401 GENMASK(31, 30));
1402 }
1403
1404 struct rtw89_h2c_cctlinfo_ud_g7 {
1405 __le32 c0;
1406 __le32 w0;
1407 __le32 w1;
1408 __le32 w2;
1409 __le32 w3;
1410 __le32 w4;
1411 __le32 w5;
1412 __le32 w6;
1413 __le32 w7;
1414 __le32 w8;
1415 __le32 w9;
1416 __le32 w10;
1417 __le32 w11;
1418 __le32 w12;
1419 __le32 w13;
1420 __le32 w14;
1421 __le32 w15;
1422 __le32 m0;
1423 __le32 m1;
1424 __le32 m2;
1425 __le32 m3;
1426 __le32 m4;
1427 __le32 m5;
1428 __le32 m6;
1429 __le32 m7;
1430 __le32 m8;
1431 __le32 m9;
1432 __le32 m10;
1433 __le32 m11;
1434 __le32 m12;
1435 __le32 m13;
1436 __le32 m14;
1437 __le32 m15;
1438 } __packed;
1439
1440 #define CCTLINFO_G7_C0_MACID GENMASK(6, 0)
1441 #define CCTLINFO_G7_C0_OP BIT(7)
1442
1443 #define CCTLINFO_G7_W0_DATARATE GENMASK(11, 0)
1444 #define CCTLINFO_G7_W0_DATA_GI_LTF GENMASK(14, 12)
1445 #define CCTLINFO_G7_W0_TRYRATE BIT(15)
1446 #define CCTLINFO_G7_W0_ARFR_CTRL GENMASK(17, 16)
1447 #define CCTLINFO_G7_W0_DIS_HE1SS_STBC BIT(18)
1448 #define CCTLINFO_G7_W0_ACQ_RPT_EN BIT(20)
1449 #define CCTLINFO_G7_W0_MGQ_RPT_EN BIT(21)
1450 #define CCTLINFO_G7_W0_ULQ_RPT_EN BIT(22)
1451 #define CCTLINFO_G7_W0_TWTQ_RPT_EN BIT(23)
1452 #define CCTLINFO_G7_W0_FORCE_TXOP BIT(24)
1453 #define CCTLINFO_G7_W0_DISRTSFB BIT(25)
1454 #define CCTLINFO_G7_W0_DISDATAFB BIT(26)
1455 #define CCTLINFO_G7_W0_NSTR_EN BIT(27)
1456 #define CCTLINFO_G7_W0_AMPDU_DENSITY GENMASK(31, 28)
1457 #define CCTLINFO_G7_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0))
1458 #define CCTLINFO_G7_W1_DATA_RTY_LOWEST_RATE GENMASK(11, 0)
1459 #define CCTLINFO_G7_W1_RTS_TXCNT_LMT GENMASK(15, 12)
1460 #define CCTLINFO_G7_W1_RTSRATE GENMASK(27, 16)
1461 #define CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE GENMASK(31, 28)
1462 #define CCTLINFO_G7_W1_ALL GENMASK(31, 0)
1463 #define CCTLINFO_G7_W2_DATA_TX_CNT_LMT GENMASK(5, 0)
1464 #define CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL BIT(6)
1465 #define CCTLINFO_G7_W2_MAX_AGG_NUM_SEL BIT(7)
1466 #define CCTLINFO_G7_W2_RTS_EN BIT(8)
1467 #define CCTLINFO_G7_W2_CTS2SELF_EN BIT(9)
1468 #define CCTLINFO_G7_W2_CCA_RTS GENMASK(11, 10)
1469 #define CCTLINFO_G7_W2_HW_RTS_EN BIT(12)
1470 #define CCTLINFO_G7_W2_RTS_DROP_DATA_MODE GENMASK(14, 13)
1471 #define CCTLINFO_G7_W2_PRELD_EN BIT(15)
1472 #define CCTLINFO_G7_W2_AMPDU_MAX_LEN GENMASK(26, 16)
1473 #define CCTLINFO_G7_W2_UL_MU_DIS BIT(27)
1474 #define CCTLINFO_G7_W2_AMPDU_MAX_TIME GENMASK(31, 28)
1475 #define CCTLINFO_G7_W2_ALL GENMASK(31, 0)
1476 #define CCTLINFO_G7_W3_MAX_AGG_NUM GENMASK(7, 0)
1477 #define CCTLINFO_G7_W3_DATA_BW GENMASK(10, 8)
1478 #define CCTLINFO_G7_W3_DATA_BW_ER BIT(11)
1479 #define CCTLINFO_G7_W3_BA_BMAP GENMASK(14, 12)
1480 #define CCTLINFO_G7_W3_VCS_STBC BIT(15)
1481 #define CCTLINFO_G7_W3_VO_LFTIME_SEL GENMASK(18, 16)
1482 #define CCTLINFO_G7_W3_VI_LFTIME_SEL GENMASK(21, 19)
1483 #define CCTLINFO_G7_W3_BE_LFTIME_SEL GENMASK(24, 22)
1484 #define CCTLINFO_G7_W3_BK_LFTIME_SEL GENMASK(27, 25)
1485 #define CCTLINFO_G7_W3_AMPDU_TIME_SEL BIT(28)
1486 #define CCTLINFO_G7_W3_AMPDU_LEN_SEL BIT(29)
1487 #define CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL BIT(30)
1488 #define CCTLINFO_G7_W3_LSIG_TXOP_EN BIT(31)
1489 #define CCTLINFO_G7_W3_ALL GENMASK(31, 0)
1490 #define CCTLINFO_G7_W4_MULTI_PORT_ID GENMASK(2, 0)
1491 #define CCTLINFO_G7_W4_BYPASS_PUNC BIT(3)
1492 #define CCTLINFO_G7_W4_MBSSID GENMASK(7, 4)
1493 #define CCTLINFO_G7_W4_DATA_DCM BIT(8)
1494 #define CCTLINFO_G7_W4_DATA_ER BIT(9)
1495 #define CCTLINFO_G7_W4_DATA_LDPC BIT(10)
1496 #define CCTLINFO_G7_W4_DATA_STBC BIT(11)
1497 #define CCTLINFO_G7_W4_A_CTRL_BQR BIT(12)
1498 #define CCTLINFO_G7_W4_A_CTRL_BSR BIT(14)
1499 #define CCTLINFO_G7_W4_A_CTRL_CAS BIT(15)
1500 #define CCTLINFO_G7_W4_ACT_SUBCH_CBW GENMASK(31, 16)
1501 #define CCTLINFO_G7_W4_ALL (GENMASK(31, 14) | GENMASK(12, 0))
1502 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING0 GENMASK(1, 0)
1503 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING1 GENMASK(3, 2)
1504 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING2 GENMASK(5, 4)
1505 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING3 GENMASK(7, 6)
1506 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING4 GENMASK(9, 8)
1507 #define CCTLINFO_G7_W5_SR_RATE GENMASK(14, 10)
1508 #define CCTLINFO_G7_W5_TID_DISABLE GENMASK(23, 16)
1509 #define CCTLINFO_G7_W5_ADDR_CAM_INDEX GENMASK(31, 24)
1510 #define CCTLINFO_G7_W5_ALL (GENMASK(31, 16) | GENMASK(14, 0))
1511 #define CCTLINFO_G7_W6_AID12_PAID GENMASK(11, 0)
1512 #define CCTLINFO_G7_W6_RESP_REF_RATE GENMASK(23, 12)
1513 #define CCTLINFO_G7_W6_ULDL BIT(31)
1514 #define CCTLINFO_G7_W6_ALL (BIT(31) | GENMASK(23, 0))
1515 #define CCTLINFO_G7_W7_NC GENMASK(2, 0)
1516 #define CCTLINFO_G7_W7_NR GENMASK(5, 3)
1517 #define CCTLINFO_G7_W7_NG GENMASK(7, 6)
1518 #define CCTLINFO_G7_W7_CB GENMASK(9, 8)
1519 #define CCTLINFO_G7_W7_CS GENMASK(11, 10)
1520 #define CCTLINFO_G7_W7_CSI_STBC_EN BIT(13)
1521 #define CCTLINFO_G7_W7_CSI_LDPC_EN BIT(14)
1522 #define CCTLINFO_G7_W7_CSI_PARA_EN BIT(15)
1523 #define CCTLINFO_G7_W7_CSI_FIX_RATE GENMASK(27, 16)
1524 #define CCTLINFO_G7_W7_CSI_BW GENMASK(31, 29)
1525 #define CCTLINFO_G7_W7_ALL (GENMASK(31, 29) | GENMASK(27, 13) | GENMASK(11, 0))
1526 #define CCTLINFO_G7_W8_ALL_ACK_SUPPORT BIT(0)
1527 #define CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT BIT(1)
1528 #define CCTLINFO_G7_W8_BSR_OM_UPD_EN BIT(2)
1529 #define CCTLINFO_G7_W8_MACID_FWD_IDC BIT(3)
1530 #define CCTLINFO_G7_W8_AZ_SEC_EN BIT(4)
1531 #define CCTLINFO_G7_W8_CSI_SEC_EN BIT(5)
1532 #define CCTLINFO_G7_W8_FIX_UL_ADDRCAM_IDX BIT(6)
1533 #define CCTLINFO_G7_W8_CTRL_CNT_VLD BIT(7)
1534 #define CCTLINFO_G7_W8_CTRL_CNT GENMASK(11, 8)
1535 #define CCTLINFO_G7_W8_RESP_SEC_TYPE GENMASK(15, 12)
1536 #define CCTLINFO_G7_W8_ALL GENMASK(15, 0)
1537 /* W9~13 are reserved */
1538 #define CCTLINFO_G7_W14_VO_CURR_RATE GENMASK(11, 0)
1539 #define CCTLINFO_G7_W14_VI_CURR_RATE GENMASK(23, 12)
1540 #define CCTLINFO_G7_W14_BE_CURR_RATE_L GENMASK(31, 24)
1541 #define CCTLINFO_G7_W14_ALL GENMASK(31, 0)
1542 #define CCTLINFO_G7_W15_BE_CURR_RATE_H GENMASK(3, 0)
1543 #define CCTLINFO_G7_W15_BK_CURR_RATE GENMASK(15, 4)
1544 #define CCTLINFO_G7_W15_MGNT_CURR_RATE GENMASK(27, 16)
1545 #define CCTLINFO_G7_W15_ALL GENMASK(27, 0)
1546
1547 struct rtw89_h2c_cctlinfo_ud_be {
1548 __le32 c0;
1549 __le32 w0;
1550 __le32 w1;
1551 __le32 w2;
1552 __le32 w3;
1553 __le32 w4;
1554 __le32 w5;
1555 __le32 w6;
1556 __le32 w7;
1557 __le32 w8;
1558 __le32 w9;
1559 __le32 w10;
1560 __le32 w11;
1561 __le32 w12;
1562 __le32 w13;
1563 __le32 w14;
1564 __le32 w15;
1565 __le32 m0;
1566 __le32 m1;
1567 __le32 m2;
1568 __le32 m3;
1569 __le32 m4;
1570 __le32 m5;
1571 __le32 m6;
1572 __le32 m7;
1573 __le32 m8;
1574 __le32 m9;
1575 __le32 m10;
1576 __le32 m11;
1577 __le32 m12;
1578 __le32 m13;
1579 __le32 m14;
1580 __le32 m15;
1581 } __packed;
1582
1583 #define BE_CCTL_INFO_C0_V1_MACID GENMASK(9, 0)
1584 #define BE_CCTL_INFO_C0_V1_OP BIT(10)
1585
1586 #define BE_CCTL_INFO_W0_DATARATE GENMASK(11, 0)
1587 #define BE_CCTL_INFO_W0_DATA_GI_LTF GENMASK(14, 12)
1588 #define BE_CCTL_INFO_W0_TRYRATE BIT(15)
1589 #define BE_CCTL_INFO_W0_ARFR_CTRL GENMASK(17, 16)
1590 #define BE_CCTL_INFO_W0_DIS_HE1SS_STBC BIT(18)
1591 #define BE_CCTL_INFO_W0_ACQ_RPT_EN BIT(20)
1592 #define BE_CCTL_INFO_W0_MGQ_RPT_EN BIT(21)
1593 #define BE_CCTL_INFO_W0_ULQ_RPT_EN BIT(22)
1594 #define BE_CCTL_INFO_W0_TWTQ_RPT_EN BIT(23)
1595 #define BE_CCTL_INFO_W0_FORCE_TXOP BIT(24)
1596 #define BE_CCTL_INFO_W0_DISRTSFB BIT(25)
1597 #define BE_CCTL_INFO_W0_DISDATAFB BIT(26)
1598 #define BE_CCTL_INFO_W0_NSTR_EN BIT(27)
1599 #define BE_CCTL_INFO_W0_AMPDU_DENSITY GENMASK(31, 28)
1600 #define BE_CCTL_INFO_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0))
1601 #define BE_CCTL_INFO_W1_DATA_RTY_LOWEST_RATE GENMASK(11, 0)
1602 #define BE_CCTL_INFO_W1_RTS_TXCNT_LMT GENMASK(15, 12)
1603 #define BE_CCTL_INFO_W1_RTSRATE GENMASK(27, 16)
1604 #define BE_CCTL_INFO_W1_RTS_RTY_LOWEST_RATE GENMASK(31, 28)
1605 #define BE_CCTL_INFO_W1_ALL GENMASK(31, 0)
1606 #define BE_CCTL_INFO_W2_DATA_TX_CNT_LMT GENMASK(5, 0)
1607 #define BE_CCTL_INFO_W2_DATA_TXCNT_LMT_SEL BIT(6)
1608 #define BE_CCTL_INFO_W2_MAX_AGG_NUM_SEL BIT(7)
1609 #define BE_CCTL_INFO_W2_RTS_EN BIT(8)
1610 #define BE_CCTL_INFO_W2_CTS2SELF_EN BIT(9)
1611 #define BE_CCTL_INFO_W2_CCA_RTS GENMASK(11, 10)
1612 #define BE_CCTL_INFO_W2_HW_RTS_EN BIT(12)
1613 #define BE_CCTL_INFO_W2_RTS_DROP_DATA_MODE GENMASK(14, 13)
1614 #define BE_CCTL_INFO_W2_PRELOAD_ENABLE BIT(15)
1615 #define BE_CCTL_INFO_W2_AMPDU_MAX_LEN GENMASK(26, 16)
1616 #define BE_CCTL_INFO_W2_UL_MU_DIS BIT(27)
1617 #define BE_CCTL_INFO_W2_AMPDU_MAX_TIME GENMASK(31, 28)
1618 #define BE_CCTL_INFO_W2_ALL GENMASK(31, 0)
1619 #define BE_CCTL_INFO_W3_MAX_AGG_NUM GENMASK(7, 0)
1620 #define BE_CCTL_INFO_W3_DATA_BW GENMASK(10, 8)
1621 #define BE_CCTL_INFO_W3_DATA_BW_ER BIT(11)
1622 #define BE_CCTL_INFO_W3_BA_BMAP GENMASK(14, 12)
1623 #define BE_CCTL_INFO_W3_VCS_STBC BIT(15)
1624 #define BE_CCTL_INFO_W3_VO_LFTIME_SEL GENMASK(18, 16)
1625 #define BE_CCTL_INFO_W3_VI_LFTIME_SEL GENMASK(21, 19)
1626 #define BE_CCTL_INFO_W3_BE_LFTIME_SEL GENMASK(24, 22)
1627 #define BE_CCTL_INFO_W3_BK_LFTIME_SEL GENMASK(27, 25)
1628 #define BE_CCTL_INFO_W3_AMPDU_TIME_SEL BIT(28)
1629 #define BE_CCTL_INFO_W3_AMPDU_LEN_SEL BIT(29)
1630 #define BE_CCTL_INFO_W3_RTS_TXCNT_LMT_SEL BIT(30)
1631 #define BE_CCTL_INFO_W3_LSIG_TXOP_EN BIT(31)
1632 #define BE_CCTL_INFO_W3_ALL GENMASK(31, 0)
1633 #define BE_CCTL_INFO_W4_MULTI_PORT_ID GENMASK(2, 0)
1634 #define BE_CCTL_INFO_W4_BYPASS_PUNC BIT(3)
1635 #define BE_CCTL_INFO_W4_MBSSID GENMASK(7, 4)
1636 #define BE_CCTL_INFO_W4_TID_DISABLE_V1 GENMASK(15, 8)
1637 #define BE_CCTL_INFO_W4_ACT_SUBCH_CBW GENMASK(31, 16)
1638 #define BE_CCTL_INFO_W4_ALL GENMASK(31, 0)
1639 #define BE_CCTL_INFO_W5_ADDR_CAM_INDEX_V1 GENMASK(9, 0)
1640 #define BE_CCTL_INFO_W5_SR_MCS_SU GENMASK(14, 10)
1641 #define BE_CCTL_INFO_W5_A_CTRL_BQR_V1 BIT(15)
1642 #define BE_CCTL_INFO_W5_A_CTRL_BSR_V1 BIT(16)
1643 #define BE_CCTL_INFO_W5_A_CTRL_CAS_V1 BIT(17)
1644 #define BE_CCTL_INFO_W5_DATA_ER_V1 BIT(18)
1645 #define BE_CCTL_INFO_W5_DATA_DCM_V1 BIT(19)
1646 #define BE_CCTL_INFO_W5_DATA_LDPC_V1 BIT(20)
1647 #define BE_CCTL_INFO_W5_DATA_STBC_V1 BIT(21)
1648 #define BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING0_V1 GENMASK(23, 22)
1649 #define BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING1_V1 GENMASK(25, 24)
1650 #define BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING2_V1 GENMASK(27, 26)
1651 #define BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING3_V1 GENMASK(29, 28)
1652 #define BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING4_V1 GENMASK(31, 30)
1653 #define BE_CCTL_INFO_W5_ALL GENMASK(31, 0)
1654 #define BE_CCTL_INFO_W6_AID12_PAID GENMASK(11, 0)
1655 #define BE_CCTL_INFO_W6_RESP_REF_RATE GENMASK(23, 12)
1656 #define BE_CCTL_INFO_W6_ULDL BIT(31)
1657 #define BE_CCTL_INFO_W6_ALL (BIT(31) | GENMASK(23, 0))
1658 #define BE_CCTL_INFO_W7_NC GENMASK(2, 0)
1659 #define BE_CCTL_INFO_W7_NR GENMASK(5, 3)
1660 #define BE_CCTL_INFO_W7_NG GENMASK(7, 6)
1661 #define BE_CCTL_INFO_W7_CB GENMASK(9, 8)
1662 #define BE_CCTL_INFO_W7_CS GENMASK(11, 10)
1663 #define BE_CCTL_INFO_W7_CSI_STBC_EN BIT(13)
1664 #define BE_CCTL_INFO_W7_CSI_LDPC_EN BIT(14)
1665 #define BE_CCTL_INFO_W7_CSI_PARA_EN BIT(15)
1666 #define BE_CCTL_INFO_W7_CSI_FIX_RATE GENMASK(27, 16)
1667 #define BE_CCTL_INFO_W7_CSI_BW GENMASK(31, 29)
1668 #define BE_CCTL_INFO_W7_ALL GENMASK(31, 0)
1669 #define BE_CCTL_INFO_W8_ALL_ACK_SUPPORT_V1 BIT(0)
1670 #define BE_CCTL_INFO_W8_BSR_QUEUE_SIZE_FORMAT_V1 BIT(1)
1671 #define BE_CCTL_INFO_W8_BSR_OM_UPD_EN_V1 BIT(2)
1672 #define BE_CCTL_INFO_W8_MACID_FWD_IDC_V1 BIT(3)
1673 #define BE_CCTL_INFO_W8_AZ_SEC_EN BIT(4)
1674 #define BE_CCTL_INFO_W8_BF_SEC_EN BIT(5)
1675 #define BE_CCTL_INFO_W8_FIX_UL_ADDRCAM_IDX_V1 BIT(6)
1676 #define BE_CCTL_INFO_W8_CTRL_CNT_VLD_V1 BIT(7)
1677 #define BE_CCTL_INFO_W8_CTRL_CNT_V1 GENMASK(11, 8)
1678 #define BE_CCTL_INFO_W8_RESP_SEC_TYPE GENMASK(15, 12)
1679 #define BE_CCTL_INFO_W8_ALL GENMASK(15, 0)
1680 #define BE_CCTL_INFO_W9_EMLSR_TRANS_DLY GENMASK(2, 0)
1681 #define BE_CCTL_INFO_W9_ALL GENMASK(2, 0)
1682 #define BE_CCTL_INFO_W10_SW_EHT_NLTF GENMASK(1, 0)
1683 #define BE_CCTL_INFO_W10_TB_MLO_MODE BIT(2)
1684 #define BE_CCTL_INFO_W10_ALL GENMASK(2, 0)
1685 #define BE_CCTL_INFO_W14_VO_CURR_RATE GENMASK(11, 0)
1686 #define BE_CCTL_INFO_W14_VI_CURR_RATE GENMASK(23, 12)
1687 #define BE_CCTL_INFO_W14_BE_CURR_RATE_L GENMASK(31, 24)
1688 #define BE_CCTL_INFO_W14_ALL GENMASK(31, 0)
1689 #define BE_CCTL_INFO_W15_BE_CURR_RATE_H GENMASK(3, 0)
1690 #define BE_CCTL_INFO_W15_BK_CURR_RATE GENMASK(15, 4)
1691 #define BE_CCTL_INFO_W15_MGNT_CURR_RATE GENMASK(27, 16)
1692 #define BE_CCTL_INFO_W15_ALL GENMASK(27, 0)
1693
1694 struct rtw89_h2c_bcn_upd {
1695 __le32 w0;
1696 __le32 w1;
1697 __le32 w2;
1698 } __packed;
1699
1700 #define RTW89_H2C_BCN_UPD_W0_PORT GENMASK(7, 0)
1701 #define RTW89_H2C_BCN_UPD_W0_MBSSID GENMASK(15, 8)
1702 #define RTW89_H2C_BCN_UPD_W0_BAND GENMASK(23, 16)
1703 #define RTW89_H2C_BCN_UPD_W0_GRP_IE_OFST GENMASK(31, 24)
1704 #define RTW89_H2C_BCN_UPD_W1_MACID GENMASK(7, 0)
1705 #define RTW89_H2C_BCN_UPD_W1_SSN_SEL GENMASK(9, 8)
1706 #define RTW89_H2C_BCN_UPD_W1_SSN_MODE GENMASK(11, 10)
1707 #define RTW89_H2C_BCN_UPD_W1_RATE GENMASK(20, 12)
1708 #define RTW89_H2C_BCN_UPD_W1_TXPWR GENMASK(23, 21)
1709 #define RTW89_H2C_BCN_UPD_W2_TXINFO_CTRL_EN BIT(0)
1710 #define RTW89_H2C_BCN_UPD_W2_NTX_PATH_EN GENMASK(4, 1)
1711 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_A GENMASK(6, 5)
1712 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_B GENMASK(8, 7)
1713 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_C GENMASK(10, 9)
1714 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_D GENMASK(12, 11)
1715 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_A BIT(13)
1716 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_B BIT(14)
1717 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_C BIT(15)
1718 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_D BIT(16)
1719 #define RTW89_H2C_BCN_UPD_W2_CSA_OFST GENMASK(31, 17)
1720
1721 struct rtw89_h2c_bcn_upd_be {
1722 __le32 w0;
1723 __le32 w1;
1724 __le32 w2;
1725 __le32 w3;
1726 __le32 w4;
1727 __le32 w5;
1728 __le32 w6;
1729 __le32 w7;
1730 __le32 w8;
1731 __le32 w9;
1732 __le32 w10;
1733 __le32 w11;
1734 __le32 w12;
1735 __le32 w13;
1736 __le32 w14;
1737 __le32 w15;
1738 __le32 w16;
1739 __le32 w17;
1740 __le32 w18;
1741 __le32 w19;
1742 __le32 w20;
1743 __le32 w21;
1744 __le32 w22;
1745 __le32 w23;
1746 __le32 w24;
1747 __le32 w25;
1748 __le32 w26;
1749 __le32 w27;
1750 __le32 w28;
1751 __le32 w29;
1752 } __packed;
1753
1754 #define RTW89_H2C_BCN_UPD_BE_W0_PORT GENMASK(7, 0)
1755 #define RTW89_H2C_BCN_UPD_BE_W0_MBSSID GENMASK(15, 8)
1756 #define RTW89_H2C_BCN_UPD_BE_W0_BAND GENMASK(23, 16)
1757 #define RTW89_H2C_BCN_UPD_BE_W0_GRP_IE_OFST GENMASK(31, 24)
1758 #define RTW89_H2C_BCN_UPD_BE_W1_MACID GENMASK(7, 0)
1759 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_SEL GENMASK(9, 8)
1760 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_MODE GENMASK(11, 10)
1761 #define RTW89_H2C_BCN_UPD_BE_W1_RATE GENMASK(20, 12)
1762 #define RTW89_H2C_BCN_UPD_BE_W1_TXPWR GENMASK(23, 21)
1763 #define RTW89_H2C_BCN_UPD_BE_W1_MACID_EXT GENMASK(31, 24)
1764 #define RTW89_H2C_BCN_UPD_BE_W2_TXINFO_CTRL_EN BIT(0)
1765 #define RTW89_H2C_BCN_UPD_BE_W2_NTX_PATH_EN GENMASK(4, 1)
1766 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_A GENMASK(6, 5)
1767 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_B GENMASK(8, 7)
1768 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_C GENMASK(10, 9)
1769 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_D GENMASK(12, 11)
1770 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_A BIT(13)
1771 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_B BIT(14)
1772 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_C BIT(15)
1773 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_D BIT(16)
1774 #define RTW89_H2C_BCN_UPD_BE_W2_CSA_OFST GENMASK(31, 17)
1775 #define RTW89_H2C_BCN_UPD_BE_W3_MLIE_CSA_OFST GENMASK(15, 0)
1776 #define RTW89_H2C_BCN_UPD_BE_W3_CRITICAL_UPD_FLAG_OFST GENMASK(31, 16)
1777 #define RTW89_H2C_BCN_UPD_BE_W4_VAP1_DTIM_CNT_OFST GENMASK(15, 0)
1778 #define RTW89_H2C_BCN_UPD_BE_W4_VAP2_DTIM_CNT_OFST GENMASK(31, 16)
1779 #define RTW89_H2C_BCN_UPD_BE_W5_VAP3_DTIM_CNT_OFST GENMASK(15, 0)
1780 #define RTW89_H2C_BCN_UPD_BE_W5_VAP4_DTIM_CNT_OFST GENMASK(31, 16)
1781 #define RTW89_H2C_BCN_UPD_BE_W6_VAP5_DTIM_CNT_OFST GENMASK(15, 0)
1782 #define RTW89_H2C_BCN_UPD_BE_W6_VAP6_DTIM_CNT_OFST GENMASK(31, 16)
1783 #define RTW89_H2C_BCN_UPD_BE_W7_VAP7_DTIM_CNT_OFST GENMASK(15, 0)
1784 #define RTW89_H2C_BCN_UPD_BE_W7_ECSA_OFST GENMASK(30, 16)
1785 #define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID BIT(31)
1786
1787 struct rtw89_h2c_tbtt_tuning {
1788 __le32 w0;
1789 __le32 w1;
1790 } __packed;
1791
1792 #define RTW89_H2C_TBTT_TUNING_W0_BAND GENMASK(3, 0)
1793 #define RTW89_H2C_TBTT_TUNING_W0_PORT GENMASK(7, 4)
1794 #define RTW89_H2C_TBTT_TUNING_W1_SHIFT GENMASK(31, 0)
1795
1796 struct rtw89_h2c_pwr_lvl {
1797 __le32 w0;
1798 __le32 w1;
1799 } __packed;
1800
1801 #define RTW89_H2C_PWR_LVL_W0_MACID GENMASK(7, 0)
1802 #define RTW89_H2C_PWR_LVL_W0_BCN_TO_VAL GENMASK(15, 8)
1803 #define RTW89_H2C_PWR_LVL_W0_PS_LVL GENMASK(19, 16)
1804 #define RTW89_H2C_PWR_LVL_W0_TRX_LVL GENMASK(23, 20)
1805 #define RTW89_H2C_PWR_LVL_W0_BCN_TO_LVL GENMASK(27, 24)
1806 #define RTW89_H2C_PWR_LVL_W0_DTIM_TO_VAL GENMASK(31, 28)
1807 #define RTW89_H2C_PWR_LVL_W1_MACID_EXT GENMASK(7, 0)
1808
1809 struct rtw89_h2c_role_maintain {
1810 __le32 w0;
1811 };
1812
1813 #define RTW89_H2C_ROLE_MAINTAIN_W0_MACID GENMASK(7, 0)
1814 #define RTW89_H2C_ROLE_MAINTAIN_W0_SELF_ROLE GENMASK(9, 8)
1815 #define RTW89_H2C_ROLE_MAINTAIN_W0_UPD_MODE GENMASK(12, 10)
1816 #define RTW89_H2C_ROLE_MAINTAIN_W0_WIFI_ROLE GENMASK(16, 13)
1817 #define RTW89_H2C_ROLE_MAINTAIN_W0_BAND GENMASK(18, 17)
1818 #define RTW89_H2C_ROLE_MAINTAIN_W0_PORT GENMASK(21, 19)
1819 #define RTW89_H2C_ROLE_MAINTAIN_W0_MACID_EXT GENMASK(31, 24)
1820
1821 enum rtw89_fw_sta_type { /* value of RTW89_H2C_JOININFO_W1_STA_TYPE */
1822 RTW89_FW_N_AC_STA = 0,
1823 RTW89_FW_AX_STA = 1,
1824 RTW89_FW_BE_STA = 2,
1825 };
1826
1827 struct rtw89_h2c_join {
1828 __le32 w0;
1829 } __packed;
1830
1831 struct rtw89_h2c_join_v1 {
1832 __le32 w0;
1833 __le32 w1;
1834 __le32 w2;
1835 } __packed;
1836
1837 #define RTW89_H2C_JOININFO_W0_MACID GENMASK(7, 0)
1838 #define RTW89_H2C_JOININFO_W0_OP BIT(8)
1839 #define RTW89_H2C_JOININFO_W0_BAND BIT(9)
1840 #define RTW89_H2C_JOININFO_W0_WMM GENMASK(11, 10)
1841 #define RTW89_H2C_JOININFO_W0_TGR BIT(12)
1842 #define RTW89_H2C_JOININFO_W0_ISHESTA BIT(13)
1843 #define RTW89_H2C_JOININFO_W0_DLBW GENMASK(15, 14)
1844 #define RTW89_H2C_JOININFO_W0_TF_MAC_PAD GENMASK(17, 16)
1845 #define RTW89_H2C_JOININFO_W0_DL_T_PE GENMASK(20, 18)
1846 #define RTW89_H2C_JOININFO_W0_PORT_ID GENMASK(23, 21)
1847 #define RTW89_H2C_JOININFO_W0_NET_TYPE GENMASK(25, 24)
1848 #define RTW89_H2C_JOININFO_W0_WIFI_ROLE GENMASK(29, 26)
1849 #define RTW89_H2C_JOININFO_W0_SELF_ROLE GENMASK(31, 30)
1850 #define RTW89_H2C_JOININFO_W1_STA_TYPE GENMASK(2, 0)
1851 #define RTW89_H2C_JOININFO_W1_IS_MLD BIT(3)
1852 #define RTW89_H2C_JOININFO_W1_MAIN_MACID GENMASK(11, 4)
1853 #define RTW89_H2C_JOININFO_W1_MLO_MODE BIT(12)
1854 #define RTW89_H2C_JOININFO_MLO_MODE_MLMR 0
1855 #define RTW89_H2C_JOININFO_MLO_MODE_MLSR 1
1856 #define RTW89_H2C_JOININFO_W1_EMLSR_CAB BIT(13)
1857 #define RTW89_H2C_JOININFO_W1_NSTR_EN BIT(14)
1858 #define RTW89_H2C_JOININFO_W1_INIT_PWR_STATE BIT(15)
1859 #define RTW89_H2C_JOININFO_W1_EMLSR_PADDING GENMASK(18, 16)
1860 #define RTW89_H2C_JOININFO_W1_EMLSR_TRANS_DELAY GENMASK(21, 19)
1861 #define RTW89_H2C_JOININFO_W2_MACID_EXT GENMASK(7, 0)
1862 #define RTW89_H2C_JOININFO_W2_MAIN_MACID_EXT GENMASK(15, 8)
1863
1864 struct rtw89_h2c_notify_dbcc {
1865 __le32 w0;
1866 } __packed;
1867
1868 #define RTW89_H2C_NOTIFY_DBCC_EN BIT(0)
1869
SET_GENERAL_PKT_MACID(void * h2c,u32 val)1870 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val)
1871 {
1872 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1873 }
1874
SET_GENERAL_PKT_PROBRSP_ID(void * h2c,u32 val)1875 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val)
1876 {
1877 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1878 }
1879
SET_GENERAL_PKT_PSPOLL_ID(void * h2c,u32 val)1880 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val)
1881 {
1882 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1883 }
1884
SET_GENERAL_PKT_NULL_ID(void * h2c,u32 val)1885 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val)
1886 {
1887 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1888 }
1889
SET_GENERAL_PKT_QOS_NULL_ID(void * h2c,u32 val)1890 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val)
1891 {
1892 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1893 }
1894
SET_GENERAL_PKT_CTS2SELF_ID(void * h2c,u32 val)1895 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val)
1896 {
1897 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1898 }
1899
SET_LOG_CFG_LEVEL(void * h2c,u32 val)1900 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val)
1901 {
1902 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1903 }
1904
SET_LOG_CFG_PATH(void * h2c,u32 val)1905 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val)
1906 {
1907 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1908 }
1909
SET_LOG_CFG_COMP(void * h2c,u32 val)1910 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val)
1911 {
1912 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
1913 }
1914
SET_LOG_CFG_COMP_EXT(void * h2c,u32 val)1915 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val)
1916 {
1917 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0));
1918 }
1919
1920 struct rtw89_h2c_ba_cam {
1921 __le32 w0;
1922 __le32 w1;
1923 } __packed;
1924
1925 #define RTW89_H2C_BA_CAM_W0_VALID BIT(0)
1926 #define RTW89_H2C_BA_CAM_W0_INIT_REQ BIT(1)
1927 #define RTW89_H2C_BA_CAM_W0_ENTRY_IDX GENMASK(3, 2)
1928 #define RTW89_H2C_BA_CAM_W0_TID GENMASK(7, 4)
1929 #define RTW89_H2C_BA_CAM_W0_MACID GENMASK(15, 8)
1930 #define RTW89_H2C_BA_CAM_W0_BMAP_SIZE GENMASK(19, 16)
1931 #define RTW89_H2C_BA_CAM_W0_SSN GENMASK(31, 20)
1932 #define RTW89_H2C_BA_CAM_W1_UID GENMASK(7, 0)
1933 #define RTW89_H2C_BA_CAM_W1_STD_EN BIT(8)
1934 #define RTW89_H2C_BA_CAM_W1_BAND BIT(9)
1935 #define RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1 GENMASK(31, 28)
1936
1937 struct rtw89_h2c_ba_cam_v1 {
1938 __le32 w0;
1939 __le32 w1;
1940 } __packed;
1941
1942 #define RTW89_H2C_BA_CAM_V1_W0_VALID BIT(0)
1943 #define RTW89_H2C_BA_CAM_V1_W0_INIT_REQ BIT(1)
1944 #define RTW89_H2C_BA_CAM_V1_W0_TID_MASK GENMASK(7, 4)
1945 #define RTW89_H2C_BA_CAM_V1_W0_MACID_MASK GENMASK(15, 8)
1946 #define RTW89_H2C_BA_CAM_V1_W0_BMAP_SIZE_MASK GENMASK(19, 16)
1947 #define RTW89_H2C_BA_CAM_V1_W0_SSN_MASK GENMASK(31, 20)
1948 #define RTW89_H2C_BA_CAM_V1_W1_UID_VALUE_MASK GENMASK(7, 0)
1949 #define RTW89_H2C_BA_CAM_V1_W1_STD_ENTRY_EN BIT(8)
1950 #define RTW89_H2C_BA_CAM_V1_W1_BAND_SEL BIT(9)
1951 #define RTW89_H2C_BA_CAM_V1_W1_MLD_EN BIT(10)
1952 #define RTW89_H2C_BA_CAM_V1_W1_ENTRY_IDX_MASK GENMASK(31, 24)
1953
1954 struct rtw89_h2c_ba_cam_init {
1955 __le32 w0;
1956 } __packed;
1957
1958 #define RTW89_H2C_BA_CAM_INIT_USERS_MASK GENMASK(7, 0)
1959 #define RTW89_H2C_BA_CAM_INIT_OFFSET_MASK GENMASK(19, 12)
1960 #define RTW89_H2C_BA_CAM_INIT_BAND_SEL BIT(24)
1961
SET_LPS_PARM_MACID(void * h2c,u32 val)1962 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val)
1963 {
1964 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1965 }
1966
SET_LPS_PARM_PSMODE(void * h2c,u32 val)1967 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val)
1968 {
1969 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1970 }
1971
SET_LPS_PARM_RLBM(void * h2c,u32 val)1972 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val)
1973 {
1974 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1975 }
1976
SET_LPS_PARM_SMARTPS(void * h2c,u32 val)1977 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val)
1978 {
1979 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20));
1980 }
1981
SET_LPS_PARM_AWAKEINTERVAL(void * h2c,u32 val)1982 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val)
1983 {
1984 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1985 }
1986
SET_LPS_PARM_VOUAPSD(void * h2c,u32 val)1987 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val)
1988 {
1989 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0));
1990 }
1991
SET_LPS_PARM_VIUAPSD(void * h2c,u32 val)1992 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val)
1993 {
1994 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1));
1995 }
1996
SET_LPS_PARM_BEUAPSD(void * h2c,u32 val)1997 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val)
1998 {
1999 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2));
2000 }
2001
SET_LPS_PARM_BKUAPSD(void * h2c,u32 val)2002 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val)
2003 {
2004 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3));
2005 }
2006
SET_LPS_PARM_LASTRPWM(void * h2c,u32 val)2007 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val)
2008 {
2009 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
2010 }
2011
2012 struct rtw89_h2c_lps_ch_info {
2013 struct {
2014 u8 pri_ch;
2015 u8 central_ch;
2016 u8 bw;
2017 u8 band;
2018 } __packed info[2];
2019
2020 __le32 mlo_dbcc_mode_lps;
2021 } __packed;
2022
2023 struct rtw89_h2c_lps_ml_cmn_info {
2024 u8 fmt_id;
2025 u8 rfe_type;
2026 u8 rsvd0[2];
2027 __le32 mlo_dbcc_mode;
2028 u8 central_ch[RTW89_PHY_NUM];
2029 u8 pri_ch[RTW89_PHY_NUM];
2030 u8 bw[RTW89_PHY_NUM];
2031 u8 band[RTW89_PHY_NUM];
2032 u8 bcn_rate_type[RTW89_PHY_NUM];
2033 u8 rsvd1[2];
2034 __le16 tia_gain[RTW89_PHY_NUM][TIA_GAIN_NUM];
2035 u8 lna_gain[RTW89_PHY_NUM][LNA_GAIN_NUM];
2036 u8 rsvd2[2];
2037 u8 tia_lna_op1db[RTW89_PHY_NUM][LNA_GAIN_NUM + 1];
2038 u8 lna_op1db[RTW89_PHY_NUM][LNA_GAIN_NUM];
2039 u8 dup_bcn_ofst[RTW89_PHY_NUM];
2040 } __packed;
2041
2042 #define BB_RX_GAIN_TB_RSSI_COMP_NUM 3
2043 #define BB_RX_GAIN_CCK_RPL_BIAS_COMP_NUM 2
2044 #define BB_GT2_GS_IDX_NUM 11
2045 #define BB_GT2_WB_GIDX_ELNA_NUM 16
2046 #define BB_GT2_G_ELNA_NUM 2
2047
2048 enum rtw89_bb_link_rx_gain_table_type {
2049 RTW89_BB_PS_LINK_RX_GAIN_TAB_BCN_PATH_A = 0x00,
2050 RTW89_BB_PS_LINK_RX_GAIN_TAB_BCN_PATH_B = 0x01,
2051 RTW89_BB_PS_LINK_RX_GAIN_TAB_NOR_PATH_A = 0x02,
2052 RTW89_BB_PS_LINK_RX_GAIN_TAB_NOR_PATH_B = 0x03,
2053 RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX,
2054 };
2055
2056 #define RTW89_BB_PS_LINK_ID_SKIP 0xfe
2057
2058 enum rtw89_bb_ps_link_buf_id {
2059 RTW89_BB_PS_LINK_BUF_0 = 0x00,
2060 RTW89_BB_PS_LINK_BUF_1 = 0x01,
2061 RTW89_BB_PS_LINK_BUF_2 = 0x02,
2062 RTW89_BB_PS_LINK_BUF_MAX,
2063 };
2064
2065 struct rtw89_bb_link_info_rx_gain {
2066 u8 gain_ofst[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX];
2067 __le16 rpl_bias_comp[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX];
2068 u8 tb_rssi_m_bias_comp[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX]
2069 [BB_RX_GAIN_TB_RSSI_COMP_NUM];
2070 u8 cck_gain_ofst[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX];
2071 u8 cck_rpl_bias_comp[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX]
2072 [BB_RX_GAIN_CCK_RPL_BIAS_COMP_NUM];
2073 u8 gain_err_lna[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][LNA_GAIN_NUM];
2074 __le16 gain_err_tia[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][TIA_GAIN_NUM];
2075 u8 op1db_lna[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][LNA_GAIN_NUM];
2076 u8 op1db_tia[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][TIA_LNA_OP1DB_NUM];
2077 struct {
2078 u8 _20M[RTW89_BW20_SC_20M];
2079 u8 _40M[RTW89_BW20_SC_40M];
2080 u8 _80M[RTW89_BW20_SC_80M];
2081 u8 _160M[RTW89_BW20_SC_160M];
2082 } rpl_bias_comp_bw[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX];
2083 u8 wb_gs[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][BB_GT2_GS_IDX_NUM];
2084 u8 bypass_lna[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][LNA_GAIN_NUM];
2085 u8 wb_lna_tia[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][BB_GT2_WB_GIDX_ELNA_NUM];
2086 u8 wb_g_elna[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][BB_GT2_G_ELNA_NUM];
2087 } __packed;
2088
2089 struct rtw89_h2c_lps_ml_cmn_info_v1 {
2090 u8 fmt_id;
2091 u8 rfe_type;
2092 u8 rssi_main;
2093 u8 rsvd0;
2094 __le32 mlo_dbcc_mode;
2095 u8 link_id[RTW89_BB_PS_LINK_BUF_MAX];
2096 u8 central_ch[RTW89_BB_PS_LINK_BUF_MAX];
2097 u8 pri_ch[RTW89_BB_PS_LINK_BUF_MAX];
2098 u8 bw[RTW89_BB_PS_LINK_BUF_MAX];
2099 u8 band[RTW89_BB_PS_LINK_BUF_MAX];
2100 u8 dup_bcn_ofst[RTW89_BB_PS_LINK_BUF_MAX];
2101 struct rtw89_bb_link_info_rx_gain rx_gain[RTW89_BB_PS_LINK_BUF_MAX];
2102 } __packed;
2103
2104 struct rtw89_h2c_trig_cpu_except {
2105 __le32 w0;
2106 } __packed;
2107
2108 #define RTW89_H2C_CPU_EXCEPTION_TYPE GENMASK(31, 0)
2109
RTW89_SET_FWCMD_PKT_DROP_SEL(void * cmd,u32 val)2110 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val)
2111 {
2112 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2113 }
2114
RTW89_SET_FWCMD_PKT_DROP_MACID(void * cmd,u32 val)2115 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val)
2116 {
2117 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
2118 }
2119
RTW89_SET_FWCMD_PKT_DROP_BAND(void * cmd,u32 val)2120 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val)
2121 {
2122 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
2123 }
2124
RTW89_SET_FWCMD_PKT_DROP_PORT(void * cmd,u32 val)2125 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val)
2126 {
2127 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
2128 }
2129
RTW89_SET_FWCMD_PKT_DROP_MBSSID(void * cmd,u32 val)2130 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val)
2131 {
2132 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0));
2133 }
2134
RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void * cmd,u32 val)2135 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val)
2136 {
2137 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8));
2138 }
2139
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void * cmd,u32 val)2140 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val)
2141 {
2142 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
2143 }
2144
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void * cmd,u32 val)2145 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val)
2146 {
2147 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
2148 }
2149
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void * cmd,u32 val)2150 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val)
2151 {
2152 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
2153 }
2154
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void * cmd,u32 val)2155 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val)
2156 {
2157 le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0));
2158 }
2159
RTW89_SET_KEEP_ALIVE_ENABLE(void * h2c,u32 val)2160 static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val)
2161 {
2162 le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0));
2163 }
2164
RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void * h2c,u32 val)2165 static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val)
2166 {
2167 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
2168 }
2169
RTW89_SET_KEEP_ALIVE_PERIOD(void * h2c,u32 val)2170 static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val)
2171 {
2172 le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16));
2173 }
2174
RTW89_SET_KEEP_ALIVE_MACID(void * h2c,u32 val)2175 static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val)
2176 {
2177 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
2178 }
2179
RTW89_SET_DISCONNECT_DETECT_ENABLE(void * h2c,u32 val)2180 static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val)
2181 {
2182 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2183 }
2184
RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void * h2c,u32 val)2185 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val)
2186 {
2187 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
2188 }
2189
RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void * h2c,u32 val)2190 static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val)
2191 {
2192 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
2193 }
2194
RTW89_SET_DISCONNECT_DETECT_MAC_ID(void * h2c,u32 val)2195 static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val)
2196 {
2197 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
2198 }
2199
RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void * h2c,u32 val)2200 static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val)
2201 {
2202 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
2203 }
2204
RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void * h2c,u32 val)2205 static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val)
2206 {
2207 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
2208 }
2209
RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void * h2c,u32 val)2210 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val)
2211 {
2212 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
2213 }
2214
2215 struct rtw89_h2c_wow_global {
2216 __le32 w0;
2217 struct rtw89_wow_key_info key_info;
2218 } __packed;
2219
2220 #define RTW89_H2C_WOW_GLOBAL_W0_ENABLE BIT(0)
2221 #define RTW89_H2C_WOW_GLOBAL_W0_DROP_ALL_PKT BIT(1)
2222 #define RTW89_H2C_WOW_GLOBAL_W0_RX_PARSE_AFTER_WAKE BIT(2)
2223 #define RTW89_H2C_WOW_GLOBAL_W0_WAKE_BAR_PULLED BIT(3)
2224 #define RTW89_H2C_WOW_GLOBAL_W0_MAC_ID GENMASK(15, 8)
2225 #define RTW89_H2C_WOW_GLOBAL_W0_PAIRWISE_SEC_ALGO GENMASK(23, 16)
2226 #define RTW89_H2C_WOW_GLOBAL_W0_GROUP_SEC_ALGO GENMASK(31, 24)
2227
2228 #define RTW89_MAX_SUPPORT_NL_NUM 16
2229 struct rtw89_h2c_cfg_nlo {
2230 __le32 w0;
2231 u8 nlo_cnt;
2232 u8 rsvd[3];
2233 __le32 patterncheck;
2234 __le32 rsvd1;
2235 __le32 rsvd2;
2236 u8 ssid_len[RTW89_MAX_SUPPORT_NL_NUM];
2237 u8 chiper[RTW89_MAX_SUPPORT_NL_NUM];
2238 u8 rsvd3[24];
2239 u8 ssid[RTW89_MAX_SUPPORT_NL_NUM][IEEE80211_MAX_SSID_LEN];
2240 } __packed;
2241
2242 #define RTW89_H2C_NLO_W0_ENABLE BIT(0)
2243 #define RTW89_H2C_NLO_W0_IGNORE_CIPHER BIT(2)
2244 #define RTW89_H2C_NLO_W0_MACID GENMASK(31, 24)
2245
2246 struct rtw89_h2c_wow_wakeup_ctrl {
2247 __le32 w0;
2248 } __packed;
2249
2250 #define RTW89_H2C_WOW_WAKEUP_CTRL_W0_PATTERN_MATCH_ENABLE BIT(0)
2251 #define RTW89_H2C_WOW_WAKEUP_CTRL_W0_MAGIC_ENABLE BIT(1)
2252 #define RTW89_H2C_WOW_WAKEUP_CTRL_W0_HW_UNICAST_ENABLE BIT(2)
2253 #define RTW89_H2C_WOW_WAKEUP_CTRL_W0_FW_UNICAST_ENABLE BIT(3)
2254 #define RTW89_H2C_WOW_WAKEUP_CTRL_W0_DEAUTH_ENABLE BIT(4)
2255 #define RTW89_H2C_WOW_WAKEUP_CTRL_W0_REKEYP_ENABLE BIT(5)
2256 #define RTW89_H2C_WOW_WAKEUP_CTRL_W0_EAP_ENABLE BIT(6)
2257 #define RTW89_H2C_WOW_WAKEUP_CTRL_W0_ALL_DATA_ENABLE BIT(7)
2258 #define RTW89_H2C_WOW_WAKEUP_CTRL_W0_MAGIC_MLD_ENABLE BIT(8)
2259 #define RTW89_H2C_WOW_WAKEUP_CTRL_W0_MAC_ID_EXT GENMASK(23, 16)
2260 #define RTW89_H2C_WOW_WAKEUP_CTRL_W0_MAC_ID GENMASK(31, 24)
2261
2262 struct rtw89_h2c_wow_cam_update {
2263 __le32 w0;
2264 __le32 wkfm0;
2265 __le32 wkfm1;
2266 __le32 wkfm2;
2267 __le32 wkfm3;
2268 __le32 w5;
2269 } __packed;
2270
2271 #define RTW89_H2C_WOW_CAM_UPD_W0_R_W BIT(0)
2272 #define RTW89_H2C_WOW_CAM_UPD_W0_IDX GENMASK(7, 1)
2273 #define RTW89_H2C_WOW_CAM_UPD_WKFM0 GENMASK(31, 0)
2274 #define RTW89_H2C_WOW_CAM_UPD_WKFM1 GENMASK(31, 0)
2275 #define RTW89_H2C_WOW_CAM_UPD_WKFM2 GENMASK(31, 0)
2276 #define RTW89_H2C_WOW_CAM_UPD_WKFM3 GENMASK(31, 0)
2277 #define RTW89_H2C_WOW_CAM_UPD_W5_CRC GENMASK(15, 0)
2278 #define RTW89_H2C_WOW_CAM_UPD_W5_NEGATIVE_PATTERN_MATCH BIT(22)
2279 #define RTW89_H2C_WOW_CAM_UPD_W5_SKIP_MAC_HDR BIT(23)
2280 #define RTW89_H2C_WOW_CAM_UPD_W5_UC BIT(24)
2281 #define RTW89_H2C_WOW_CAM_UPD_W5_MC BIT(25)
2282 #define RTW89_H2C_WOW_CAM_UPD_W5_BC BIT(26)
2283 #define RTW89_H2C_WOW_CAM_UPD_W5_VALID BIT(31)
2284
2285 struct rtw89_h2c_wow_payload_cam_update {
2286 __le32 w0;
2287 __le32 wkfm0;
2288 __le32 wkfm1;
2289 __le32 wkfm2;
2290 __le32 wkfm3;
2291 __le32 w5;
2292 __le32 w6;
2293 __le32 w7;
2294 __le32 w8;
2295 } __packed;
2296
2297 #define RTW89_H2C_WOW_PLD_CAM_UPD_W0_R_W BIT(0)
2298 #define RTW89_H2C_WOW_PLD_CAM_UPD_W0_IDX GENMASK(7, 1)
2299 #define RTW89_H2C_WOW_PLD_CAM_UPD_WKFM0 GENMASK(31, 0)
2300 #define RTW89_H2C_WOW_PLD_CAM_UPD_WKFM1 GENMASK(31, 0)
2301 #define RTW89_H2C_WOW_PLD_CAM_UPD_WKFM2 GENMASK(31, 0)
2302 #define RTW89_H2C_WOW_PLD_CAM_UPD_WKFM3 GENMASK(31, 0)
2303 #define RTW89_H2C_WOW_PLD_CAM_UPD_W5_UC BIT(0)
2304 #define RTW89_H2C_WOW_PLD_CAM_UPD_W5_MC BIT(1)
2305 #define RTW89_H2C_WOW_PLD_CAM_UPD_W5_BC BIT(2)
2306 #define RTW89_H2C_WOW_PLD_CAM_UPD_W5_SKIP_MAC_HDR BIT(7)
2307 #define RTW89_H2C_WOW_PLD_CAM_UPD_W6_CRC GENMASK(15, 0)
2308 #define RTW89_H2C_WOW_PLD_CAM_UPD_W7_NEGATIVE_PATTERN_MATCH BIT(0)
2309 #define RTW89_H2C_WOW_PLD_CAM_UPD_W8_VALID BIT(0)
2310 #define RTW89_H2C_WOW_PLD_CAM_UPD_W8_WOW_PTR BIT(1)
2311
2312 struct rtw89_h2c_wow_gtk_ofld {
2313 __le32 w0;
2314 __le32 w1;
2315 struct rtw89_wow_gtk_info gtk_info;
2316 } __packed;
2317
2318 #define RTW89_H2C_WOW_GTK_OFLD_W0_EN BIT(0)
2319 #define RTW89_H2C_WOW_GTK_OFLD_W0_TKIP_EN BIT(1)
2320 #define RTW89_H2C_WOW_GTK_OFLD_W0_IEEE80211W_EN BIT(2)
2321 #define RTW89_H2C_WOW_GTK_OFLD_W0_PAIRWISE_WAKEUP BIT(3)
2322 #define RTW89_H2C_WOW_GTK_OFLD_W0_NOREKEY_WAKEUP BIT(4)
2323 #define RTW89_H2C_WOW_GTK_OFLD_W0_MAC_ID GENMASK(23, 16)
2324 #define RTW89_H2C_WOW_GTK_OFLD_W0_GTK_RSP_ID GENMASK(31, 24)
2325 #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_SA_QUERY_ID GENMASK(7, 0)
2326 #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_BIP_SEC_ALGO GENMASK(9, 8)
2327 #define RTW89_H2C_WOW_GTK_OFLD_W1_ALGO_AKM_SUIT GENMASK(17, 10)
2328
2329 struct rtw89_h2c_arp_offload {
2330 __le32 w0;
2331 __le32 w1;
2332 } __packed;
2333
2334 #define RTW89_H2C_ARP_OFFLOAD_W0_ENABLE BIT(0)
2335 #define RTW89_H2C_ARP_OFFLOAD_W0_ACTION BIT(1)
2336 #define RTW89_H2C_ARP_OFFLOAD_W0_MACID GENMASK(23, 16)
2337 #define RTW89_H2C_ARP_OFFLOAD_W0_PKT_ID GENMASK(31, 24)
2338 #define RTW89_H2C_ARP_OFFLOAD_W1_CONTENT GENMASK(31, 0)
2339
2340 #define BT_H2C_FUNC_BT2ND 0x80
2341 #define BT_C2H_FUNC_BT2ND 0x80
2342
2343 enum rtw89_btc_btf_h2c_class {
2344 BTFC_SET = 0x10,
2345 BTFC_GET = 0x11,
2346 BTFC_FW_EVENT = 0x12,
2347 };
2348
2349 enum rtw89_btc_btf_set {
2350 SET_REPORT_EN = 0x0,
2351 SET_SLOT_TABLE,
2352 SET_MREG_TABLE,
2353 SET_CX_POLICY,
2354 SET_GPIO_DBG,
2355 SET_DRV_INFO,
2356 SET_DRV_EVENT,
2357 SET_BT_WREG_ADDR,
2358 SET_BT_WREG_VAL,
2359 SET_BT_RREG_ADDR,
2360 SET_BT_WL_CH_INFO,
2361 SET_BT_INFO_REPORT,
2362 SET_BT_IGNORE_WLAN_ACT,
2363 SET_BT_TX_PWR,
2364 SET_BT_LNA_CONSTRAIN,
2365 SET_BT_QUERY_DEV_LIST,
2366 SET_BT_QUERY_DEV_INFO,
2367 SET_BT_PSD_REPORT,
2368 SET_H2C_TEST,
2369 SET_IOFLD_RF,
2370 SET_IOFLD_BB,
2371 SET_IOFLD_MAC,
2372 SET_IOFLD_SCBD,
2373 SET_H2C_MACRO,
2374 SET_MAX1,
2375 };
2376
2377 enum rtw89_btc_cxdrvinfo {
2378 CXDRVINFO_INIT = 0,
2379 CXDRVINFO_ROLE,
2380 CXDRVINFO_DBCC,
2381 CXDRVINFO_SMAP,
2382 CXDRVINFO_RFK,
2383 CXDRVINFO_RUN,
2384 CXDRVINFO_CTRL,
2385 CXDRVINFO_SCAN,
2386 CXDRVINFO_TRX, /* WL traffic to WL fw */
2387 CXDRVINFO_TXPWR,
2388 CXDRVINFO_FDDT,
2389 CXDRVINFO_MLO,
2390 CXDRVINFO_OSI,
2391 CXDRVINFO_MAX,
2392 };
2393
2394 enum rtw89_fbtc_gpio_type {
2395 CXDGPIO_EN_MAP = 0x0,
2396 CXDGPIO_MUX_MAP = 0x1,
2397 CXDGPIO_EXT_HPTA = 0x2,
2398 CXDGPIO_EXT_HMBX = 0x3,
2399 CXDGPIO_EXT_SWOUT = 0x4,
2400 CXDGPIO_EXT_SWIN = 0x5,
2401 CXDGPIO_MAX,
2402 };
2403
2404 enum rtw89_scan_mode {
2405 RTW89_SCAN_IMMEDIATE,
2406 RTW89_SCAN_DELAY,
2407 };
2408
2409 enum rtw89_scan_type {
2410 RTW89_SCAN_ONCE,
2411 RTW89_SCAN_NORMAL,
2412 RTW89_SCAN_NORMAL_SLOW,
2413 RTW89_SCAN_SEAMLESS,
2414 RTW89_SCAN_MAX,
2415 };
2416
RTW89_SET_FWCMD_CXHDR_TYPE(void * cmd,u8 val)2417 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val)
2418 {
2419 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0));
2420 }
2421
RTW89_SET_FWCMD_CXHDR_LEN(void * cmd,u8 val)2422 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val)
2423 {
2424 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0));
2425 }
2426
2427 struct rtw89_h2c_cxhdr {
2428 u8 type;
2429 u8 len;
2430 } __packed;
2431
2432 struct rtw89_h2c_cxhdr_v7 {
2433 u8 type;
2434 u8 ver;
2435 u8 len;
2436 } __packed;
2437
2438 struct rtw89_h2c_cxctrl_v7 {
2439 struct rtw89_h2c_cxhdr_v7 hdr;
2440 struct rtw89_btc_ctrl_v7 ctrl;
2441 } __packed;
2442
2443 struct rtw89_h2c_cxctrl_v9 {
2444 struct rtw89_h2c_cxhdr_v7 hdr;
2445 struct rtw89_btc_ctrl_v9 ctrl;
2446 } __packed;
2447
2448 #define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr)
2449 #define H2C_LEN_CXDRVHDR_V7 sizeof(struct rtw89_h2c_cxhdr_v7)
2450
2451 struct rtw89_h2c_cxrole_v7 {
2452 struct rtw89_h2c_cxhdr_v7 hdr;
2453 struct rtw89_btc_wl_role_info_v7 r;
2454 } __packed;
2455
2456 struct rtw89_h2c_cxrole_v8 {
2457 struct rtw89_h2c_cxhdr_v7 hdr;
2458 struct rtw89_btc_wl_role_info_v8 r;
2459 } __packed;
2460
2461 struct rtw89_h2c_cxrole_v10 {
2462 struct rtw89_h2c_cxhdr_v7 hdr;
2463 struct rtw89_btc_wl_role_info_v10 r;
2464 } __packed;
2465
2466 struct rtw89_h2c_cxmlo_v2 {
2467 struct rtw89_h2c_cxhdr_v7 hdr;
2468 struct rtw89_btc_wl_mlo_info_v2 mlo;
2469 } __packed;
2470
2471 struct rtw89_h2c_cxosi {
2472 struct rtw89_h2c_cxhdr_v7 hdr;
2473 struct rtw89_btc_fbtc_outsrc_set_info_v1 osi;
2474 } __packed;
2475
2476 struct rtw89_h2c_cxosi_v6 {
2477 struct rtw89_h2c_cxhdr_v7 hdr;
2478 struct rtw89_btc_fbtc_outsrc_set_info_v6 osi;
2479 } __packed;
2480
2481 struct rtw89_h2c_cxinit {
2482 struct rtw89_h2c_cxhdr hdr;
2483 u8 ant_type;
2484 u8 ant_num;
2485 u8 ant_iso;
2486 u8 ant_info;
2487 u8 mod_rfe;
2488 u8 mod_cv;
2489 u8 mod_info;
2490 u8 mod_adie_kt;
2491 u8 wl_gch;
2492 u8 info;
2493 u8 rsvd;
2494 u8 rsvd1;
2495 } __packed;
2496
2497 struct rtw89_btc_trx_info_u8 {
2498 u8 tx_lvl;
2499 u8 rx_lvl;
2500 u8 wl_rssi;
2501 u8 bt_rssi;
2502
2503 s8 wl_tx_power[RTW89_PHY_NUM]; /* absolute Tx power (dBm), 0xff-> no BTC control */
2504 s8 wl_rx_gain[RTW89_PHY_NUM]; /* rx gain table index (TBD.) */
2505 s8 bt_tx_power[BTC_ALL_BT]; /* decrease Tx power (dB) */
2506 s8 bt_rx_gain[BTC_ALL_BT]; /* LNA constrain level */
2507 s8 zb_tx_power[BTC_ALL_BT];
2508 s8 zb_rx_gain[BTC_ALL_BT];
2509
2510 u8 cn; /* condition_num */
2511 s8 nhm;
2512 u8 bt_profile;
2513 u8 rsvd2;
2514 } __packed;
2515
2516 struct rtw89_btc_trx_info_v7_u8 {
2517 u8 tx_lvl;
2518 u8 rx_lvl;
2519 u8 wl_rssi;
2520 u8 bt_rssi;
2521
2522 s8 wl_tx_power;
2523 s8 wl_rx_gain;
2524 s8 bt_tx_power;
2525 s8 bt_rx_gain;
2526 s8 zb_tx_power;
2527 s8 zb_rx_gain;
2528
2529 u8 cn;
2530 s8 nhm;
2531 u8 bt_profile;
2532 u8 rsvd2;
2533 } __packed;
2534
2535 struct rtw89_btc_trx_info_v107_u8 {
2536 u8 tx_lvl;
2537 u8 rx_lvl;
2538 u8 wl_rssi;
2539 u8 bt_rssi;
2540
2541 s8 wl_tx_power;
2542 s8 wl_rx_gain;
2543 s8 bt_tx_power;
2544 s8 bt_rx_gain;
2545
2546 u8 cn;
2547 s8 nhm;
2548 u8 bt_profile;
2549 u8 rsvd2;
2550 } __packed;
2551
2552 struct rtw89_btc_trx_info_le {
2553 __le16 tx_rate;
2554 __le16 rx_rate;
2555
2556 __le32 tx_tp;
2557 __le32 rx_tp;
2558 __le32 rx_err_ratio;
2559 } __packed;
2560
2561 struct rtw89_h2c_cxtrx_v9 {
2562 struct rtw89_h2c_cxhdr_v7 hdr;
2563 struct rtw89_btc_trx_info_u8 v9_u8;
2564 struct rtw89_btc_trx_info_le v9_le;
2565 } __packed;
2566
2567 struct rtw89_h2c_cxtrx_v7 {
2568 struct rtw89_h2c_cxhdr_v7 hdr;
2569 struct rtw89_btc_trx_info_v7_u8 v7_u8;
2570 struct rtw89_btc_trx_info_le v7_le;
2571 } __packed;
2572
2573 struct rtw89_h2c_cxtrx_v107 {
2574 struct rtw89_h2c_cxhdr_v7 hdr;
2575 struct rtw89_btc_trx_info_v107_u8 v107_u8;
2576 struct rtw89_btc_trx_info_le v7_le;
2577 } __packed;
2578
2579 struct rtw89_h2c_cxtxpwr_v7 {
2580 struct rtw89_h2c_cxhdr_v7 hdr;
2581 u8 pwr;
2582 } __packed;
2583
2584 struct rtw89_h2c_cxtxpwr_v9 {
2585 struct rtw89_h2c_cxhdr_v7 hdr;
2586 u8 pwr;
2587 u8 band;
2588 } __packed;
2589
2590 #define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0)
2591 #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1)
2592 #define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2)
2593 #define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4)
2594
2595 #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0)
2596 #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1)
2597 #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2)
2598 #define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3)
2599
2600 #define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0)
2601 #define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1)
2602 #define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2)
2603 #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3)
2604 #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4)
2605
2606 struct rtw89_h2c_cxinit_v7 {
2607 struct rtw89_h2c_cxhdr_v7 hdr;
2608 struct rtw89_btc_init_info_v7 init;
2609 } __packed;
2610
2611 struct rtw89_h2c_cxinit_v107 {
2612 struct rtw89_h2c_cxhdr_v7 hdr;
2613 struct rtw89_btc_init_info_v107 init;
2614 } __packed;
2615
2616 struct rtw89_h2c_cxinit_v10 {
2617 struct rtw89_h2c_cxhdr_v7 hdr;
2618 struct rtw89_btc_init_info_v10 init;
2619 } __packed;
2620
2621 struct rtw89_h2c_cxinit_v11 {
2622 struct rtw89_h2c_cxhdr_v7 hdr;
2623 struct rtw89_btc_init_info_v11 init;
2624 } __packed;
2625
2626 #define RTW89_H2C_CXROLE_V101_ROLE_STAT_CONNTECTED BIT(0)
2627 #define RTW89_H2C_CXROLE_V101_ROLE_STAT_PID GENMASK(3, 1)
2628 #define RTW89_H2C_CXROLE_V101_ROLE_STAT_PHY BIT(4)
2629 #define RTW89_H2C_CXROLE_V101_ROLE_STAT_NOA BIT(5)
2630 #define RTW89_H2C_CXROLE_V101_ROLE_STAT_BADN GENMASK(7, 6)
2631
2632 #define RTW89_H2C_CXROLE_V101_CLIPS_BW_CLIENTPS BIT(0)
2633 #define RTW89_H2C_CXROLE_V101_CLIPS_BW_BW GENMASK(7, 1)
2634
2635 #define RTW89_H2C_CXROLE_V101_DBCC_EN BIT(0)
2636 #define RTW89_H2C_CXROLE_V101_DBCC_CHG BIT(1)
2637 #define RTW89_H2C_CXROLE_V101_DBCC_2G_PHY GENMASK(3, 2)
2638 #define RTW89_H2C_CXROLE_V101_DBCC_LINKMODE_CHG BIT(4)
2639 #define RTW89_H2C_CXROLE_V101_DBCC_RSVD GENMASK(31, 5)
2640
2641 struct rtw89_btc_wl_active_role_v101 {
2642 u8 map_role_status;
2643 u8 map_clips_bw;
2644 u8 role;
2645 u8 ch;
2646 __le32 noa_duration;
2647 } __packed;
2648
2649 struct rtw89_h2c_cxrole_v101 {
2650 struct rtw89_h2c_cxhdr hdr;
2651 u8 connect_cnt;
2652 u8 link_mode;
2653 __le16 role_map;
2654 struct rtw89_btc_wl_active_role_v101 act_role[RTW89_PORT_NUM];
2655 __le32 mrole_type;
2656 __le32 mrole_noa_duration;
2657 __le32 map_dbcc_linkmode_chg;
2658 } __packed;
2659
RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void * cmd,u8 val)2660 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val)
2661 {
2662 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0));
2663 }
2664
RTW89_SET_FWCMD_CXROLE_LINK_MODE(void * cmd,u8 val)2665 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val)
2666 {
2667 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0));
2668 }
2669
RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void * cmd,u16 val)2670 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val)
2671 {
2672 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0));
2673 }
2674
RTW89_SET_FWCMD_CXROLE_ROLE_STA(void * cmd,u16 val)2675 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val)
2676 {
2677 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1));
2678 }
2679
RTW89_SET_FWCMD_CXROLE_ROLE_AP(void * cmd,u16 val)2680 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val)
2681 {
2682 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2));
2683 }
2684
RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void * cmd,u16 val)2685 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val)
2686 {
2687 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3));
2688 }
2689
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void * cmd,u16 val)2690 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val)
2691 {
2692 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4));
2693 }
2694
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void * cmd,u16 val)2695 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val)
2696 {
2697 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5));
2698 }
2699
RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void * cmd,u16 val)2700 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val)
2701 {
2702 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6));
2703 }
2704
RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void * cmd,u16 val)2705 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val)
2706 {
2707 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7));
2708 }
2709
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void * cmd,u16 val)2710 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val)
2711 {
2712 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8));
2713 }
2714
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void * cmd,u16 val)2715 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val)
2716 {
2717 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9));
2718 }
2719
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void * cmd,u16 val)2720 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val)
2721 {
2722 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10));
2723 }
2724
RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void * cmd,u16 val)2725 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val)
2726 {
2727 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11));
2728 }
2729
RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void * cmd,u8 val,int n,u8 offset)2730 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset)
2731 {
2732 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2733 }
2734
RTW89_SET_FWCMD_CXROLE_ACT_PID(void * cmd,u8 val,int n,u8 offset)2735 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset)
2736 {
2737 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2738 }
2739
RTW89_SET_FWCMD_CXROLE_ACT_PHY(void * cmd,u8 val,int n,u8 offset)2740 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset)
2741 {
2742 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2743 }
2744
RTW89_SET_FWCMD_CXROLE_ACT_NOA(void * cmd,u8 val,int n,u8 offset)2745 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset)
2746 {
2747 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2748 }
2749
RTW89_SET_FWCMD_CXROLE_ACT_BAND(void * cmd,u8 val,int n,u8 offset)2750 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset)
2751 {
2752 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2753 }
2754
RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void * cmd,u8 val,int n,u8 offset)2755 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset)
2756 {
2757 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2758 }
2759
RTW89_SET_FWCMD_CXROLE_ACT_BW(void * cmd,u8 val,int n,u8 offset)2760 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset)
2761 {
2762 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2763 }
2764
RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void * cmd,u8 val,int n,u8 offset)2765 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset)
2766 {
2767 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2768 }
2769
RTW89_SET_FWCMD_CXROLE_ACT_CH(void * cmd,u8 val,int n,u8 offset)2770 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset)
2771 {
2772 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2773 }
2774
RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void * cmd,u16 val,int n,u8 offset)2775 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset)
2776 {
2777 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0));
2778 }
2779
RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void * cmd,u16 val,int n,u8 offset)2780 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset)
2781 {
2782 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0));
2783 }
2784
RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void * cmd,u16 val,int n,u8 offset)2785 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset)
2786 {
2787 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0));
2788 }
2789
RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void * cmd,u16 val,int n,u8 offset)2790 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset)
2791 {
2792 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0));
2793 }
2794
RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void * cmd,u32 val,int n,u8 offset)2795 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset)
2796 {
2797 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0));
2798 }
2799
RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void * cmd,u8 val,int n,u8 offset)2800 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset)
2801 {
2802 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2803 }
2804
RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void * cmd,u8 val,int n,u8 offset)2805 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset)
2806 {
2807 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2808 }
2809
RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void * cmd,u8 val,int n,u8 offset)2810 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset)
2811 {
2812 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2813 }
2814
RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void * cmd,u8 val,int n,u8 offset)2815 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset)
2816 {
2817 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2818 }
2819
RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void * cmd,u8 val,int n,u8 offset)2820 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset)
2821 {
2822 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2823 }
2824
RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void * cmd,u8 val,int n,u8 offset)2825 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset)
2826 {
2827 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2828 }
2829
RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void * cmd,u8 val,int n,u8 offset)2830 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset)
2831 {
2832 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2833 }
2834
RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void * cmd,u8 val,int n,u8 offset)2835 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset)
2836 {
2837 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2838 }
2839
RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void * cmd,u8 val,int n,u8 offset)2840 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset)
2841 {
2842 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2843 }
2844
RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void * cmd,u32 val,int n,u8 offset)2845 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset)
2846 {
2847 le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0));
2848 }
2849
RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void * cmd,u32 val,u8 offset)2850 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset)
2851 {
2852 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0));
2853 }
2854
RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void * cmd,u32 val,u8 offset)2855 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset)
2856 {
2857 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0));
2858 }
2859
RTW89_SET_FWCMD_CXROLE_DBCC_EN(void * cmd,u32 val,u8 offset)2860 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset)
2861 {
2862 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0));
2863 }
2864
RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void * cmd,u32 val,u8 offset)2865 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset)
2866 {
2867 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1));
2868 }
2869
RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void * cmd,u32 val,u8 offset)2870 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset)
2871 {
2872 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2));
2873 }
2874
RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void * cmd,u32 val,u8 offset)2875 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset)
2876 {
2877 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4));
2878 }
2879
RTW89_SET_FWCMD_CXCTRL_MANUAL(void * cmd,u32 val)2880 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val)
2881 {
2882 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0));
2883 }
2884
RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void * cmd,u32 val)2885 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val)
2886 {
2887 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1));
2888 }
2889
RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void * cmd,u32 val)2890 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val)
2891 {
2892 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2));
2893 }
2894
RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void * cmd,u32 val)2895 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val)
2896 {
2897 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3));
2898 }
2899
RTW89_SET_FWCMD_CXRFK_STATE(void * cmd,u32 val)2900 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val)
2901 {
2902 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0));
2903 }
2904
RTW89_SET_FWCMD_CXRFK_PATH_MAP(void * cmd,u32 val)2905 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val)
2906 {
2907 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2));
2908 }
2909
RTW89_SET_FWCMD_CXRFK_PHY_MAP(void * cmd,u32 val)2910 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val)
2911 {
2912 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6));
2913 }
2914
RTW89_SET_FWCMD_CXRFK_BAND(void * cmd,u32 val)2915 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val)
2916 {
2917 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8));
2918 }
2919
RTW89_SET_FWCMD_CXRFK_TYPE(void * cmd,u32 val)2920 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val)
2921 {
2922 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10));
2923 }
2924
RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void * cmd,u32 val)2925 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val)
2926 {
2927 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2928 }
2929
RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void * cmd,u32 val)2930 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val)
2931 {
2932 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8));
2933 }
2934
RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void * cmd,u32 val)2935 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val)
2936 {
2937 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16));
2938 }
2939
2940 struct rtw89_h2c_chinfo_elem {
2941 __le32 w0;
2942 __le32 w1;
2943 __le32 w2;
2944 __le32 w3;
2945 __le32 w4;
2946 __le32 w5;
2947 __le32 w6;
2948 } __packed;
2949
2950 #define RTW89_H2C_CHINFO_W0_PERIOD GENMASK(7, 0)
2951 #define RTW89_H2C_CHINFO_W0_DWELL GENMASK(15, 8)
2952 #define RTW89_H2C_CHINFO_W0_CENTER_CH GENMASK(23, 16)
2953 #define RTW89_H2C_CHINFO_W0_PRI_CH GENMASK(31, 24)
2954 #define RTW89_H2C_CHINFO_W1_BW GENMASK(2, 0)
2955 #define RTW89_H2C_CHINFO_W1_ACTION GENMASK(7, 3)
2956 #define RTW89_H2C_CHINFO_W1_NUM_PKT GENMASK(11, 8)
2957 #define RTW89_H2C_CHINFO_W1_TX BIT(12)
2958 #define RTW89_H2C_CHINFO_W1_PAUSE_DATA BIT(13)
2959 #define RTW89_H2C_CHINFO_W1_BAND GENMASK(15, 14)
2960 #define RTW89_H2C_CHINFO_W1_PKT_ID GENMASK(23, 16)
2961 #define RTW89_H2C_CHINFO_W1_DFS BIT(24)
2962 #define RTW89_H2C_CHINFO_W1_TX_NULL BIT(25)
2963 #define RTW89_H2C_CHINFO_W1_RANDOM BIT(26)
2964 #define RTW89_H2C_CHINFO_W1_CFG_TX BIT(27)
2965 #define RTW89_H2C_CHINFO_W1_MACID_TX BIT(29)
2966 #define RTW89_H2C_CHINFO_W2_PKT0 GENMASK(7, 0)
2967 #define RTW89_H2C_CHINFO_W2_PKT1 GENMASK(15, 8)
2968 #define RTW89_H2C_CHINFO_W2_PKT2 GENMASK(23, 16)
2969 #define RTW89_H2C_CHINFO_W2_PKT3 GENMASK(31, 24)
2970 #define RTW89_H2C_CHINFO_W3_PKT4 GENMASK(7, 0)
2971 #define RTW89_H2C_CHINFO_W3_PKT5 GENMASK(15, 8)
2972 #define RTW89_H2C_CHINFO_W3_PKT6 GENMASK(23, 16)
2973 #define RTW89_H2C_CHINFO_W3_PKT7 GENMASK(31, 24)
2974 #define RTW89_H2C_CHINFO_W4_POWER_IDX GENMASK(15, 0)
2975
2976 struct rtw89_h2c_chinfo_elem_be {
2977 __le32 w0;
2978 __le32 w1;
2979 __le32 w2;
2980 __le32 w3;
2981 __le32 w4;
2982 __le32 w5;
2983 __le32 w6;
2984 __le32 w7;
2985 } __packed;
2986
2987 #define RTW89_H2C_CHINFO_BE_W0_PERIOD GENMASK(7, 0)
2988 #define RTW89_H2C_CHINFO_BE_W0_DWELL GENMASK(15, 8)
2989 #define RTW89_H2C_CHINFO_BE_W0_CENTER_CH GENMASK(23, 16)
2990 #define RTW89_H2C_CHINFO_BE_W0_PRI_CH GENMASK(31, 24)
2991 #define RTW89_H2C_CHINFO_BE_W1_BW GENMASK(2, 0)
2992 #define RTW89_H2C_CHINFO_BE_W1_CH_BAND GENMASK(4, 3)
2993 #define RTW89_H2C_CHINFO_BE_W1_DFS BIT(5)
2994 #define RTW89_H2C_CHINFO_BE_W1_PAUSE_DATA BIT(6)
2995 #define RTW89_H2C_CHINFO_BE_W1_TX_NULL BIT(7)
2996 #define RTW89_H2C_CHINFO_BE_W1_RANDOM BIT(8)
2997 #define RTW89_H2C_CHINFO_BE_W1_NOTIFY GENMASK(13, 9)
2998 #define RTW89_H2C_CHINFO_BE_W1_PROBE BIT(14)
2999 #define RTW89_H2C_CHINFO_BE_W1_EARLY_LEAVE_CRIT GENMASK(17, 15)
3000 #define RTW89_H2C_CHINFO_BE_W1_CHKPT_TIMER GENMASK(31, 24)
3001 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TIME GENMASK(7, 0)
3002 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TH GENMASK(15, 8)
3003 #define RTW89_H2C_CHINFO_BE_W2_TX_PKT_CTRL GENMASK(31, 16)
3004 #define RTW89_H2C_CHINFO_BE_W3_PKT0 GENMASK(7, 0)
3005 #define RTW89_H2C_CHINFO_BE_W3_PKT1 GENMASK(15, 8)
3006 #define RTW89_H2C_CHINFO_BE_W3_PKT2 GENMASK(23, 16)
3007 #define RTW89_H2C_CHINFO_BE_W3_PKT3 GENMASK(31, 24)
3008 #define RTW89_H2C_CHINFO_BE_W4_PKT4 GENMASK(7, 0)
3009 #define RTW89_H2C_CHINFO_BE_W4_PKT5 GENMASK(15, 8)
3010 #define RTW89_H2C_CHINFO_BE_W4_PKT6 GENMASK(23, 16)
3011 #define RTW89_H2C_CHINFO_BE_W4_PKT7 GENMASK(31, 24)
3012 #define RTW89_H2C_CHINFO_BE_W5_SW_DEF GENMASK(7, 0)
3013 #define RTW89_H2C_CHINFO_BE_W5_FW_PROBE0_SSIDS GENMASK(31, 16)
3014 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_SHORTSSIDS GENMASK(15, 0)
3015 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_BSSIDS GENMASK(31, 16)
3016 #define RTW89_H2C_CHINFO_BE_W7_PERIOD_V1 GENMASK(15, 0)
3017
3018 struct rtw89_h2c_chinfo {
3019 u8 ch_num;
3020 u8 elem_size;
3021 u8 arg;
3022 u8 rsvd0;
3023 struct rtw89_h2c_chinfo_elem elem[] __counted_by(ch_num);
3024 } __packed;
3025
3026 struct rtw89_h2c_chinfo_be {
3027 u8 ch_num;
3028 u8 elem_size;
3029 u8 arg;
3030 u8 rsvd0;
3031 struct rtw89_h2c_chinfo_elem_be elem[] __counted_by(ch_num);
3032 } __packed;
3033
3034 #define RTW89_H2C_CHINFO_ARG_MAC_IDX_MASK BIT(0)
3035 #define RTW89_H2C_CHINFO_ARG_APPEND_MASK BIT(1)
3036
3037 struct rtw89_h2c_scanofld {
3038 __le32 w0;
3039 __le32 w1;
3040 __le32 w2;
3041 __le32 tsf_high;
3042 __le32 tsf_low;
3043 __le32 w5;
3044 __le32 w6;
3045 } __packed;
3046
3047 #define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0)
3048 #define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8)
3049 #define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16)
3050 #define RTW89_H2C_SCANOFLD_W0_BAND BIT(19)
3051 #define RTW89_H2C_SCANOFLD_W0_OPERATION GENMASK(21, 20)
3052 #define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND GENMASK(23, 22)
3053 #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0)
3054 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1)
3055 #define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2)
3056 #define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE GENMASK(4, 3)
3057 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5)
3058 #define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8)
3059 #define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16)
3060 #define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24)
3061 #define RTW89_H2C_SCANOFLD_W2_NORM_PD GENMASK(15, 0)
3062 #define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16)
3063 #define RTW89_H2C_SCANOFLD_W3_TSF_HIGH GENMASK(31, 0)
3064 #define RTW89_H2C_SCANOFLD_W4_TSF_LOW GENMASK(31, 0)
3065 #define RTW89_H2C_SCANOFLD_W6_SECOND_MACID GENMASK(31, 24)
3066
3067 struct rtw89_h2c_scanofld_be_macc_role {
3068 __le32 w0;
3069 } __packed;
3070
3071 #define RTW89_MAX_OP_NUM_BE 2
3072 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_BAND GENMASK(1, 0)
3073 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_PORT GENMASK(4, 2)
3074 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_MACID GENMASK(23, 8)
3075 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_OPCH_END GENMASK(31, 24)
3076
3077 struct rtw89_h2c_scanofld_be_opch {
3078 __le32 w0;
3079 __le32 w1;
3080 __le32 w2;
3081 __le32 w3;
3082 __le32 w4;
3083 } __packed;
3084
3085 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_MACID GENMASK(15, 0)
3086 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_BAND GENMASK(17, 16)
3087 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_PORT GENMASK(20, 18)
3088 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY GENMASK(22, 21)
3089 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_TXNULL BIT(23)
3090 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY_VAL GENMASK(31, 24)
3091 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_DURATION GENMASK(7, 0)
3092 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CH_BAND GENMASK(9, 8)
3093 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_BW GENMASK(12, 10)
3094 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_NOTIFY GENMASK(14, 13)
3095 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_PRI_CH GENMASK(23, 16)
3096 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CENTRAL_CH GENMASK(31, 24)
3097 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_PKTS_CTRL GENMASK(7, 0)
3098 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SW_DEF GENMASK(15, 8)
3099 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SS GENMASK(18, 16)
3100 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_TXBCN BIT(19)
3101 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT0 GENMASK(7, 0)
3102 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT1 GENMASK(15, 8)
3103 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT2 GENMASK(23, 16)
3104 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT3 GENMASK(31, 24)
3105 #define RTW89_H2C_SCANOFLD_BE_OPCH_W4_DURATION_V1 GENMASK(15, 0)
3106
3107 struct rtw89_h2c_scanofld_be {
3108 __le32 w0;
3109 __le32 w1;
3110 __le32 w2;
3111 __le32 w3;
3112 __le32 w4;
3113 __le32 w5;
3114 __le32 w6;
3115 __le32 w7;
3116 __le32 w8;
3117 __le32 w9; /* Added after SCAN_OFFLOAD_BE_V1 */
3118 __le32 w10; /* Added after SCAN_OFFLOAD_BE_V2 */
3119 __le32 w11; /* Added after SCAN_OFFLOAD_BE_V2 */
3120 /* struct rtw89_h2c_scanofld_be_macc_role (flexible number) */
3121 /* struct rtw89_h2c_scanofld_be_opch (flexible number) */
3122 /* probe SSID list (flexible number); Added after SCAN_OFFLOAD_BE_V3 */
3123 } __packed;
3124
3125 #define RTW89_H2C_SCANOFLD_BE_W0_OP GENMASK(1, 0)
3126 #define RTW89_H2C_SCANOFLD_BE_W0_SCAN_MODE GENMASK(3, 2)
3127 #define RTW89_H2C_SCANOFLD_BE_W0_REPEAT GENMASK(5, 4)
3128 #define RTW89_H2C_SCANOFLD_BE_W0_NOTIFY_END BIT(6)
3129 #define RTW89_H2C_SCANOFLD_BE_W0_LEARN_CH BIT(7)
3130 #define RTW89_H2C_SCANOFLD_BE_W0_MACID GENMASK(23, 8)
3131 #define RTW89_H2C_SCANOFLD_BE_W0_PORT GENMASK(26, 24)
3132 #define RTW89_H2C_SCANOFLD_BE_W0_BAND GENMASK(28, 27)
3133 #define RTW89_H2C_SCANOFLD_BE_W0_PROBE_WITH_RATE BIT(29)
3134 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_MACC_ROLE GENMASK(7, 0)
3135 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_OP GENMASK(15, 8)
3136 #define RTW89_H2C_SCANOFLD_BE_W1_NORM_PD GENMASK(31, 16)
3137 #define RTW89_H2C_SCANOFLD_BE_W2_SLOW_PD GENMASK(15, 0)
3138 #define RTW89_H2C_SCANOFLD_BE_W2_NORM_CY GENMASK(23, 16)
3139 #define RTW89_H2C_SCANOFLD_BE_W2_OPCH_END GENMASK(31, 24)
3140 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SSID GENMASK(7, 0)
3141 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SHORT_SSID GENMASK(15, 8)
3142 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_BSSID GENMASK(23, 16)
3143 #define RTW89_H2C_SCANOFLD_BE_W3_PROBEID GENMASK(31, 24)
3144 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_5G GENMASK(7, 0)
3145 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_6G GENMASK(15, 8)
3146 #define RTW89_H2C_SCANOFLD_BE_W4_DELAY_START GENMASK(31, 16)
3147 #define RTW89_H2C_SCANOFLD_BE_W5_MLO_MODE GENMASK(31, 0)
3148 #define RTW89_H2C_SCANOFLD_BE_W6_CHAN_PROHIB_LOW GENMASK(31, 0)
3149 #define RTW89_H2C_SCANOFLD_BE_W7_CHAN_PROHIB_HIGH GENMASK(31, 0)
3150 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_2GHZ GENMASK(7, 0)
3151 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_5GHZ GENMASK(15, 8)
3152 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_6GHZ GENMASK(23, 16)
3153 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_CFG GENMASK(7, 0)
3154 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_MACC GENMASK(15, 8)
3155 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_OP GENMASK(23, 16)
3156
3157 struct rtw89_h2c_trx_protect {
3158 __le32 c0;
3159 __le32 c1;
3160 __le32 w0;
3161 __le32 m0;
3162 __le32 w1;
3163 __le32 m1;
3164 } __packed;
3165
3166 #define RTW89_H2C_TRX_PROTECT_C0_BAND_BITMAP GENMASK(2, 0)
3167 #define RTW89_H2C_TRX_PROTECT_C0_OP_MODE GENMASK(4, 3)
3168 #define RTW89_H2C_TRX_PROTECT_C1_RX_IN BIT(0)
3169 #define RTW89_H2C_TRX_PROTECT_C1_PPDU_STS BIT(4)
3170 #define RTW89_H2C_TRX_PROTECT_C1_MSK_RX_IN BIT(16)
3171 #define RTW89_H2C_TRX_PROTECT_C1_MSK_PPDU_STS BIT(20)
3172 #define RTW89_H2C_TRX_PROTECT_W0_TXEN_BE0 BIT(0)
3173 #define RTW89_H2C_TRX_PROTECT_W0_TXEN_BK0 BIT(1)
3174 #define RTW89_H2C_TRX_PROTECT_W0_TXEN_VI0 BIT(2)
3175 #define RTW89_H2C_TRX_PROTECT_W0_TXEN_VO0 BIT(3)
3176 #define RTW89_H2C_TRX_PROTECT_W0_TXEN_BE1 BIT(4)
3177 #define RTW89_H2C_TRX_PROTECT_W0_TXEN_BK1 BIT(5)
3178 #define RTW89_H2C_TRX_PROTECT_W0_TXEN_VI1 BIT(6)
3179 #define RTW89_H2C_TRX_PROTECT_W0_TXEN_VO1 BIT(7)
3180 #define RTW89_H2C_TRX_PROTECT_W0_TXEN_MG0 BIT(8)
3181 #define RTW89_H2C_TRX_PROTECT_W0_TXEN_MG1 BIT(9)
3182 #define RTW89_H2C_TRX_PROTECT_W0_TXEN_MG2 BIT(10)
3183 #define RTW89_H2C_TRX_PROTECT_W0_TXEN_HI BIT(11)
3184 #define RTW89_H2C_TRX_PROTECT_W0_TXEN_BCN BIT(12)
3185 #define RTW89_H2C_TRX_PROTECT_W0_TXEN_UL BIT(13)
3186 #define RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT0 BIT(14)
3187 #define RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT1 BIT(15)
3188 #define RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT2 BIT(16)
3189 #define RTW89_H2C_TRX_PROTECT_W0_TXEN_TWT3 BIT(17)
3190 #define RTW89_H2C_TRX_PROTECT_W0_TXEN_SPEQ0 BIT(18)
3191 #define RTW89_H2C_TRX_PROTECT_W0_TXEN_SPEQ1 BIT(19)
3192 #define RTW89_H2C_TRX_PROTECT_W1_CHINFO_EN BIT(0)
3193 #define RTW89_H2C_TRX_PROTECT_W1_DFS_EN BIT(1)
3194
3195 enum rtw89_fw_cmd_ofld_arg_src {
3196 RTW89_FW_CMD_OFLD_SRC_BB,
3197 RTW89_FW_CMD_OFLD_SRC_RF,
3198 RTW89_FW_CMD_OFLD_SRC_MAC,
3199 RTW89_FW_CMD_OFLD_SRC_RF_DDIE,
3200 };
3201
3202 enum rtw89_fw_cmd_ofld_arg_type {
3203 RTW89_FW_CMD_OFLD_WRITE,
3204 RTW89_FW_CMD_OFLD_COMPARE,
3205 RTW89_FW_CMD_OFLD_DELAY,
3206 RTW89_FW_CMD_OFLD_MOVE,
3207 };
3208
3209 struct rtw89_fw_cmd_ofld_arg {
3210 enum rtw89_fw_cmd_ofld_arg_src src;
3211 enum rtw89_fw_cmd_ofld_arg_type type;
3212 enum rtw89_rf_path rf_path;
3213 u32 value;
3214 u32 mask;
3215 u32 offset;
3216 u16 id;
3217 };
3218
3219 struct rtw89_h2c_cmd_ofld {
3220 __le32 w0;
3221 __le32 w1;
3222 __le32 w2;
3223 __le32 w3;
3224 } __packed;
3225
3226 #define RTW89_H2C_CMD_OFLD_W0_SRC GENMASK(1, 0)
3227 #define RTW89_H2C_CMD_OFLD_W0_TYPE GENMASK(3, 2)
3228 #define RTW89_H2C_CMD_OFLD_W0_LC BIT(4)
3229 #define RTW89_H2C_CMD_OFLD_W0_PATH GENMASK(6, 5)
3230 #define RTW89_H2C_CMD_OFLD_W0_CMD_NUM GENMASK(14, 8)
3231 #define RTW89_H2C_CMD_OFLD_W0_OFFSET GENMASK(31, 16)
3232 #define RTW89_H2C_CMD_OFLD_W1_ID GENMASK(15, 0)
3233 #define RTW89_H2C_CMD_OFLD_W1_BASE_OFFSET GENMASK(31, 16)
3234 #define RTW89_H2C_CMD_OFLD_W2_VALUE GENMASK(31, 0)
3235 #define RTW89_H2C_CMD_OFLD_W3_MASK GENMASK(31, 0)
3236 #define RTW89_W8_MASK_OF_ALIGNED_ADDR(offset) (0xff << (((offset) & 0x3) << 3))
3237 #define RTW89_W16_MASK_OF_ALIGNED_ADDR(offset) (0xffff << (((offset) & 0x2) * 8))
3238
3239 #define RTW89_FW_CMD_OFLD_NR 125
3240 struct rtw89_fw_cmd_ofld_info {
3241 unsigned int pack_level;
3242 u32 cnt;
3243 u32 accu_delay;
3244 struct rtw89_h2c_cmd_ofld cmds[RTW89_FW_CMD_OFLD_NR];
3245 };
3246
3247 struct rtw89_h2c_fwips {
3248 __le32 w0;
3249 } __packed;
3250
3251 #define RTW89_H2C_FW_IPS_W0_MACID GENMASK(7, 0)
3252 #define RTW89_H2C_FW_IPS_W0_ENABLE BIT(8)
3253
3254 struct rtw89_h2c_mlo_link_cfg {
3255 __le32 w0;
3256 };
3257
3258 #define RTW89_H2C_MLO_LINK_CFG_W0_MACID GENMASK(15, 0)
3259 #define RTW89_H2C_MLO_LINK_CFG_W0_OPTION GENMASK(19, 16)
3260
RTW89_SET_FWCMD_P2P_MACID(void * cmd,u32 val)3261 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val)
3262 {
3263 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
3264 }
3265
RTW89_SET_FWCMD_P2P_P2PID(void * cmd,u32 val)3266 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val)
3267 {
3268 le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8));
3269 }
3270
RTW89_SET_FWCMD_P2P_NOAID(void * cmd,u32 val)3271 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val)
3272 {
3273 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12));
3274 }
3275
RTW89_SET_FWCMD_P2P_ACT(void * cmd,u32 val)3276 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val)
3277 {
3278 le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16));
3279 }
3280
RTW89_SET_FWCMD_P2P_TYPE(void * cmd,u32 val)3281 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val)
3282 {
3283 le32p_replace_bits((__le32 *)cmd, val, BIT(20));
3284 }
3285
RTW89_SET_FWCMD_P2P_ALL_SLEP(void * cmd,u32 val)3286 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val)
3287 {
3288 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
3289 }
3290
RTW89_SET_FWCMD_NOA_START_TIME(void * cmd,__le32 val)3291 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val)
3292 {
3293 *((__le32 *)cmd + 1) = val;
3294 }
3295
RTW89_SET_FWCMD_NOA_INTERVAL(void * cmd,__le32 val)3296 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val)
3297 {
3298 *((__le32 *)cmd + 2) = val;
3299 }
3300
RTW89_SET_FWCMD_NOA_DURATION(void * cmd,__le32 val)3301 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val)
3302 {
3303 *((__le32 *)cmd + 3) = val;
3304 }
3305
RTW89_SET_FWCMD_NOA_COUNT(void * cmd,u32 val)3306 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val)
3307 {
3308 le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0));
3309 }
3310
RTW89_SET_FWCMD_NOA_CTWINDOW(void * cmd,u32 val)3311 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val)
3312 {
3313 u8 ctwnd;
3314
3315 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT))
3316 return;
3317 ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val);
3318 le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8));
3319 }
3320
RTW89_SET_FWCMD_TSF32_TOGL_BAND(void * cmd,u32 val)3321 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val)
3322 {
3323 le32p_replace_bits((__le32 *)cmd, val, BIT(0));
3324 }
3325
RTW89_SET_FWCMD_TSF32_TOGL_EN(void * cmd,u32 val)3326 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val)
3327 {
3328 le32p_replace_bits((__le32 *)cmd, val, BIT(1));
3329 }
3330
RTW89_SET_FWCMD_TSF32_TOGL_PORT(void * cmd,u32 val)3331 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val)
3332 {
3333 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2));
3334 }
3335
RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void * cmd,u32 val)3336 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val)
3337 {
3338 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16));
3339 }
3340
3341 enum rtw89_fw_mcc_c2h_rpt_cfg {
3342 RTW89_FW_MCC_C2H_RPT_OFF = 0,
3343 RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1,
3344 RTW89_FW_MCC_C2H_RPT_ALL = 2,
3345 };
3346
3347 struct rtw89_fw_mcc_add_req {
3348 u8 macid;
3349 u8 central_ch_seg0;
3350 u8 central_ch_seg1;
3351 u8 primary_ch;
3352 enum rtw89_bandwidth bandwidth: 4;
3353 u32 group: 2;
3354 u32 c2h_rpt: 2;
3355 u32 dis_tx_null: 1;
3356 u32 dis_sw_retry: 1;
3357 u32 in_curr_ch: 1;
3358 u32 sw_retry_count: 3;
3359 u32 tx_null_early: 4;
3360 u32 btc_in_2g: 1;
3361 u32 pta_en: 1;
3362 u32 rfk_by_pass: 1;
3363 u32 ch_band_type: 2;
3364 u32 rsvd0: 9;
3365 u32 duration;
3366 u8 courtesy_en;
3367 u8 courtesy_num;
3368 u8 courtesy_target;
3369 u8 rsvd1;
3370 };
3371
RTW89_SET_FWCMD_ADD_MCC_MACID(void * cmd,u32 val)3372 static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val)
3373 {
3374 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
3375 }
3376
RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void * cmd,u32 val)3377 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val)
3378 {
3379 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3380 }
3381
RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void * cmd,u32 val)3382 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val)
3383 {
3384 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3385 }
3386
RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void * cmd,u32 val)3387 static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val)
3388 {
3389 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3390 }
3391
RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void * cmd,u32 val)3392 static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val)
3393 {
3394 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0));
3395 }
3396
RTW89_SET_FWCMD_ADD_MCC_GROUP(void * cmd,u32 val)3397 static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val)
3398 {
3399 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4));
3400 }
3401
RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void * cmd,u32 val)3402 static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val)
3403 {
3404 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6));
3405 }
3406
RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void * cmd,u32 val)3407 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val)
3408 {
3409 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8));
3410 }
3411
RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void * cmd,u32 val)3412 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val)
3413 {
3414 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9));
3415 }
3416
RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void * cmd,u32 val)3417 static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val)
3418 {
3419 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10));
3420 }
3421
RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void * cmd,u32 val)3422 static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val)
3423 {
3424 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11));
3425 }
3426
RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void * cmd,u32 val)3427 static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val)
3428 {
3429 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14));
3430 }
3431
RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void * cmd,u32 val)3432 static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val)
3433 {
3434 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18));
3435 }
3436
RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void * cmd,u32 val)3437 static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val)
3438 {
3439 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19));
3440 }
3441
RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void * cmd,u32 val)3442 static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val)
3443 {
3444 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20));
3445 }
3446
RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void * cmd,u32 val)3447 static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val)
3448 {
3449 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21));
3450 }
3451
RTW89_SET_FWCMD_ADD_MCC_DURATION(void * cmd,u32 val)3452 static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val)
3453 {
3454 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3455 }
3456
RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void * cmd,u32 val)3457 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val)
3458 {
3459 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0));
3460 }
3461
RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void * cmd,u32 val)3462 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val)
3463 {
3464 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8));
3465 }
3466
RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void * cmd,u32 val)3467 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val)
3468 {
3469 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16));
3470 }
3471
3472 enum rtw89_fw_mcc_old_group_actions {
3473 RTW89_FW_MCC_OLD_GROUP_ACT_NONE = 0,
3474 RTW89_FW_MCC_OLD_GROUP_ACT_REPLACE = 1,
3475 };
3476
3477 struct rtw89_fw_mcc_start_req {
3478 u32 group: 2;
3479 u32 btc_in_group: 1;
3480 u32 old_group_action: 2;
3481 u32 old_group: 2;
3482 u32 rsvd0: 9;
3483 u32 notify_cnt: 3;
3484 u32 rsvd1: 2;
3485 u32 notify_rxdbg_en: 1;
3486 u32 rsvd2: 2;
3487 u32 macid: 8;
3488 u32 tsf_low;
3489 u32 tsf_high;
3490 };
3491
RTW89_SET_FWCMD_START_MCC_GROUP(void * cmd,u32 val)3492 static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val)
3493 {
3494 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3495 }
3496
RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void * cmd,u32 val)3497 static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val)
3498 {
3499 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3500 }
3501
RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void * cmd,u32 val)3502 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val)
3503 {
3504 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3));
3505 }
3506
RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void * cmd,u32 val)3507 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val)
3508 {
3509 le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5));
3510 }
3511
RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void * cmd,u32 val)3512 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val)
3513 {
3514 le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16));
3515 }
3516
RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void * cmd,u32 val)3517 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val)
3518 {
3519 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
3520 }
3521
RTW89_SET_FWCMD_START_MCC_MACID(void * cmd,u32 val)3522 static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val)
3523 {
3524 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3525 }
3526
RTW89_SET_FWCMD_START_MCC_TSF_LOW(void * cmd,u32 val)3527 static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val)
3528 {
3529 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3530 }
3531
RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void * cmd,u32 val)3532 static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val)
3533 {
3534 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3535 }
3536
RTW89_SET_FWCMD_STOP_MCC_MACID(void * cmd,u32 val)3537 static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val)
3538 {
3539 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
3540 }
3541
RTW89_SET_FWCMD_STOP_MCC_GROUP(void * cmd,u32 val)3542 static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val)
3543 {
3544 le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8));
3545 }
3546
RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void * cmd,u32 val)3547 static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val)
3548 {
3549 le32p_replace_bits((__le32 *)cmd, val, BIT(10));
3550 }
3551
RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void * cmd,u32 val)3552 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val)
3553 {
3554 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3555 }
3556
RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void * cmd,u32 val)3557 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val)
3558 {
3559 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3560 }
3561
RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void * cmd,u32 val)3562 static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val)
3563 {
3564 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3565 }
3566
3567 struct rtw89_fw_mcc_tsf_req {
3568 u8 group: 2;
3569 u8 rsvd0: 6;
3570 u8 macid_x;
3571 u8 macid_y;
3572 u8 rsvd1;
3573 };
3574
RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void * cmd,u32 val)3575 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val)
3576 {
3577 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3578 }
3579
RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void * cmd,u32 val)3580 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val)
3581 {
3582 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3583 }
3584
RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void * cmd,u32 val)3585 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val)
3586 {
3587 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3588 }
3589
RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void * cmd,u32 val)3590 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val)
3591 {
3592 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3593 }
3594
RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void * cmd,u32 val)3595 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val)
3596 {
3597 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3598 }
3599
RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void * cmd,u32 val)3600 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val)
3601 {
3602 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3603 }
3604
RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void * cmd,u8 * bitmap,u8 len)3605 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd,
3606 u8 *bitmap, u8 len)
3607 {
3608 memcpy((__le32 *)cmd + 1, bitmap, len);
3609 }
3610
RTW89_SET_FWCMD_MCC_SYNC_GROUP(void * cmd,u32 val)3611 static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val)
3612 {
3613 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3614 }
3615
RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void * cmd,u32 val)3616 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val)
3617 {
3618 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3619 }
3620
RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void * cmd,u32 val)3621 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val)
3622 {
3623 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3624 }
3625
RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void * cmd,u32 val)3626 static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val)
3627 {
3628 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3629 }
3630
3631 struct rtw89_fw_mcc_duration {
3632 u32 group: 2;
3633 u32 btc_in_group: 1;
3634 u32 rsvd0: 5;
3635 u32 start_macid: 8;
3636 u32 macid_x: 8;
3637 u32 macid_y: 8;
3638 u32 start_tsf_low;
3639 u32 start_tsf_high;
3640 u32 duration_x;
3641 u32 duration_y;
3642 };
3643
RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void * cmd,u32 val)3644 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val)
3645 {
3646 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3647 }
3648
3649 static
RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void * cmd,u32 val)3650 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val)
3651 {
3652 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3653 }
3654
3655 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void * cmd,u32 val)3656 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val)
3657 {
3658 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3659 }
3660
RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void * cmd,u32 val)3661 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val)
3662 {
3663 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3664 }
3665
RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void * cmd,u32 val)3666 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val)
3667 {
3668 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3669 }
3670
3671 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void * cmd,u32 val)3672 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val)
3673 {
3674 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3675 }
3676
3677 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void * cmd,u32 val)3678 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val)
3679 {
3680 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3681 }
3682
3683 static
RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void * cmd,u32 val)3684 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val)
3685 {
3686 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
3687 }
3688
3689 static
RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void * cmd,u32 val)3690 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val)
3691 {
3692 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
3693 }
3694
3695 enum rtw89_h2c_mrc_sch_types {
3696 RTW89_H2C_MRC_SCH_BAND0_ONLY = 0,
3697 RTW89_H2C_MRC_SCH_BAND1_ONLY = 1,
3698 RTW89_H2C_MRC_SCH_DUAL_BAND = 2,
3699 };
3700
3701 enum rtw89_h2c_mrc_role_types {
3702 RTW89_H2C_MRC_ROLE_WIFI = 0,
3703 RTW89_H2C_MRC_ROLE_BT = 1,
3704 RTW89_H2C_MRC_ROLE_EMPTY = 2,
3705 };
3706
3707 #define RTW89_MAC_MRC_MAX_ADD_SLOT_NUM 3
3708 #define RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT 1 /* before MLO */
3709
3710 struct rtw89_fw_mrc_add_slot_arg {
3711 u16 duration; /* unit: TU */
3712 bool courtesy_en;
3713 u8 courtesy_period;
3714 u8 courtesy_target; /* slot idx */
3715
3716 unsigned int role_num;
3717 struct {
3718 enum rtw89_h2c_mrc_role_types role_type;
3719 bool is_master;
3720 bool en_tx_null;
3721 enum rtw89_band band;
3722 enum rtw89_bandwidth bw;
3723 u8 macid;
3724 u8 central_ch;
3725 u8 primary_ch;
3726 u8 null_early; /* unit: TU */
3727
3728 /* if MLD, for macid: [0, chip::support_mld_num)
3729 * otherwise, for macid: [0, 32)
3730 */
3731 u32 macid_main_bitmap;
3732 /* for MLD, bit X maps to macid: X + chip::support_mld_num */
3733 u32 macid_paired_bitmap;
3734 } roles[RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT];
3735 };
3736
3737 struct rtw89_fw_mrc_add_arg {
3738 u8 sch_idx;
3739 enum rtw89_h2c_mrc_sch_types sch_type;
3740 bool btc_in_sch;
3741
3742 unsigned int slot_num;
3743 struct rtw89_fw_mrc_add_slot_arg slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3744 };
3745
3746 struct rtw89_h2c_mrc_add_role {
3747 __le32 w0;
3748 __le32 w1;
3749 __le32 w2;
3750 __le32 macid_main_bitmap;
3751 __le32 macid_paired_bitmap;
3752 } __packed;
3753
3754 #define RTW89_H2C_MRC_ADD_ROLE_W0_MACID GENMASK(15, 0)
3755 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_TYPE GENMASK(23, 16)
3756 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_MASTER BIT(24)
3757 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_ALT_ROLE BIT(25)
3758 #define RTW89_H2C_MRC_ADD_ROLE_W0_TX_NULL_EN BIT(26)
3759 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_ALT_EN BIT(27)
3760 #define RTW89_H2C_MRC_ADD_ROLE_W1_CENTRAL_CH_SEG GENMASK(7, 0)
3761 #define RTW89_H2C_MRC_ADD_ROLE_W1_PRI_CH GENMASK(15, 8)
3762 #define RTW89_H2C_MRC_ADD_ROLE_W1_BW GENMASK(19, 16)
3763 #define RTW89_H2C_MRC_ADD_ROLE_W1_CH_BAND_TYPE GENMASK(21, 20)
3764 #define RTW89_H2C_MRC_ADD_ROLE_W1_RFK_BY_PASS BIT(22)
3765 #define RTW89_H2C_MRC_ADD_ROLE_W1_CAN_BTC BIT(23)
3766 #define RTW89_H2C_MRC_ADD_ROLE_W1_NULL_EARLY GENMASK(31, 24)
3767 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_PERIOD GENMASK(7, 0)
3768 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_TYPE GENMASK(15, 8)
3769 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_MACID GENMASK(23, 16)
3770
3771 struct rtw89_h2c_mrc_add_slot {
3772 __le32 w0;
3773 __le32 w1;
3774 struct rtw89_h2c_mrc_add_role roles[];
3775 } __packed;
3776
3777 #define RTW89_H2C_MRC_ADD_SLOT_W0_DURATION GENMASK(15, 0)
3778 #define RTW89_H2C_MRC_ADD_SLOT_W0_COURTESY_EN BIT(17)
3779 #define RTW89_H2C_MRC_ADD_SLOT_W0_ROLE_NUM GENMASK(31, 24)
3780 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_PERIOD GENMASK(7, 0)
3781 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_TARGET GENMASK(15, 8)
3782
3783 struct rtw89_h2c_mrc_add {
3784 __le32 w0;
3785 /* Logically append flexible struct rtw89_h2c_mrc_add_slot, but there
3786 * are other flexible array inside it. We cannot access them correctly
3787 * through this struct. So, in case misusing, we don't really declare
3788 * it here.
3789 */
3790 } __packed;
3791
3792 #define RTW89_H2C_MRC_ADD_W0_SCH_IDX GENMASK(3, 0)
3793 #define RTW89_H2C_MRC_ADD_W0_SCH_TYPE GENMASK(7, 4)
3794 #define RTW89_H2C_MRC_ADD_W0_SLOT_NUM GENMASK(15, 8)
3795 #define RTW89_H2C_MRC_ADD_W0_BTC_IN_SCH BIT(16)
3796
3797 enum rtw89_h2c_mrc_start_actions {
3798 RTW89_H2C_MRC_START_ACTION_START_NEW = 0,
3799 RTW89_H2C_MRC_START_ACTION_REPLACE_OLD = 1,
3800 };
3801
3802 struct rtw89_fw_mrc_start_arg {
3803 u8 sch_idx;
3804 u8 old_sch_idx;
3805 u64 start_tsf;
3806 enum rtw89_h2c_mrc_start_actions action;
3807 };
3808
3809 struct rtw89_h2c_mrc_start {
3810 __le32 w0;
3811 __le32 start_tsf_low;
3812 __le32 start_tsf_high;
3813 } __packed;
3814
3815 #define RTW89_H2C_MRC_START_W0_SCH_IDX GENMASK(3, 0)
3816 #define RTW89_H2C_MRC_START_W0_OLD_SCH_IDX GENMASK(7, 4)
3817 #define RTW89_H2C_MRC_START_W0_ACTION GENMASK(15, 8)
3818
3819 struct rtw89_h2c_mrc_del {
3820 __le32 w0;
3821 } __packed;
3822
3823 #define RTW89_H2C_MRC_DEL_W0_SCH_IDX GENMASK(3, 0)
3824 #define RTW89_H2C_MRC_DEL_W0_DEL_ALL BIT(4)
3825 #define RTW89_H2C_MRC_DEL_W0_STOP_ONLY BIT(5)
3826 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_EN BIT(6)
3827 #define RTW89_H2C_MRC_DEL_W0_STOP_SLOT_IDX GENMASK(15, 8)
3828 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_MACID GENMASK(31, 16)
3829
3830 #define RTW89_MAC_MRC_MAX_REQ_TSF_NUM 2
3831
3832 struct rtw89_fw_mrc_req_tsf_arg {
3833 unsigned int num;
3834 struct {
3835 u8 band;
3836 u8 port;
3837 } infos[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
3838 };
3839
3840 struct rtw89_h2c_mrc_req_tsf {
3841 u8 req_tsf_num;
3842 u8 infos[] __counted_by(req_tsf_num);
3843 } __packed;
3844
3845 #define RTW89_H2C_MRC_REQ_TSF_INFO_BAND GENMASK(3, 0)
3846 #define RTW89_H2C_MRC_REQ_TSF_INFO_PORT GENMASK(7, 4)
3847
3848 enum rtw89_h2c_mrc_upd_bitmap_actions {
3849 RTW89_H2C_MRC_UPD_BITMAP_ACTION_DEL = 0,
3850 RTW89_H2C_MRC_UPD_BITMAP_ACTION_ADD = 1,
3851 };
3852
3853 struct rtw89_fw_mrc_upd_bitmap_arg {
3854 u8 sch_idx;
3855 u8 macid;
3856 u8 client_macid;
3857 enum rtw89_h2c_mrc_upd_bitmap_actions action;
3858 };
3859
3860 struct rtw89_h2c_mrc_upd_bitmap {
3861 __le32 w0;
3862 __le32 w1;
3863 } __packed;
3864
3865 #define RTW89_H2C_MRC_UPD_BITMAP_W0_SCH_IDX GENMASK(3, 0)
3866 #define RTW89_H2C_MRC_UPD_BITMAP_W0_ACTION BIT(4)
3867 #define RTW89_H2C_MRC_UPD_BITMAP_W0_MACID GENMASK(31, 16)
3868 #define RTW89_H2C_MRC_UPD_BITMAP_W1_CLIENT_MACID GENMASK(15, 0)
3869
3870 struct rtw89_fw_mrc_sync_arg {
3871 u8 offset; /* unit: TU */
3872 struct {
3873 u8 band;
3874 u8 port;
3875 } src, dest;
3876 };
3877
3878 struct rtw89_h2c_mrc_sync {
3879 __le32 w0;
3880 __le32 w1;
3881 } __packed;
3882
3883 #define RTW89_H2C_MRC_SYNC_W0_SYNC_EN BIT(0)
3884 #define RTW89_H2C_MRC_SYNC_W0_SRC_PORT GENMASK(11, 8)
3885 #define RTW89_H2C_MRC_SYNC_W0_SRC_BAND GENMASK(15, 12)
3886 #define RTW89_H2C_MRC_SYNC_W0_DEST_PORT GENMASK(19, 16)
3887 #define RTW89_H2C_MRC_SYNC_W0_DEST_BAND GENMASK(23, 20)
3888 #define RTW89_H2C_MRC_SYNC_W1_OFFSET GENMASK(15, 0)
3889
3890 struct rtw89_fw_mrc_upd_duration_arg {
3891 u8 sch_idx;
3892 u64 start_tsf;
3893
3894 unsigned int slot_num;
3895 struct {
3896 u8 slot_idx;
3897 u16 duration; /* unit: TU */
3898 } slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3899 };
3900
3901 struct rtw89_h2c_mrc_upd_duration {
3902 __le32 w0;
3903 __le32 start_tsf_low;
3904 __le32 start_tsf_high;
3905 __le32 slots[];
3906 } __packed;
3907
3908 #define RTW89_H2C_MRC_UPD_DURATION_W0_SCH_IDX GENMASK(3, 0)
3909 #define RTW89_H2C_MRC_UPD_DURATION_W0_SLOT_NUM GENMASK(15, 8)
3910 #define RTW89_H2C_MRC_UPD_DURATION_W0_BTC_IN_SCH BIT(16)
3911 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_SLOT_IDX GENMASK(7, 0)
3912 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_DURATION GENMASK(31, 16)
3913
3914 struct rtw89_h2c_wow_aoac {
3915 __le32 w0;
3916 } __packed;
3917
3918 struct rtw89_h2c_ap_info {
3919 __le32 w0;
3920 } __packed;
3921
3922 #define RTW89_H2C_AP_INFO_W0_PWR_INT_EN BIT(0)
3923
3924 #define RTW89_C2H_HEADER_LEN 8
3925
3926 struct rtw89_c2h_hdr {
3927 __le32 w0;
3928 __le32 w1;
3929 } __packed;
3930
3931 #define RTW89_C2H_HDR_W0_CATEGORY GENMASK(1, 0)
3932 #define RTW89_C2H_HDR_W0_CLASS GENMASK(7, 2)
3933 #define RTW89_C2H_HDR_W0_FUNC GENMASK(15, 8)
3934 #define RTW89_C2H_HDR_W1_LEN GENMASK(13, 0)
3935
3936 struct rtw89_fw_c2h_attr {
3937 u8 category;
3938 u8 class;
3939 u8 func;
3940 u16 len;
3941 u8 is_scan_event: 1;
3942 u8 scan_seq: 2;
3943 };
3944
RTW89_SKB_C2H_CB(struct sk_buff * skb)3945 static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb)
3946 {
3947 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
3948
3949 return (struct rtw89_fw_c2h_attr *)skb->cb;
3950 }
3951
3952 struct rtw89_c2h_done_ack {
3953 __le32 w0;
3954 __le32 w1;
3955 __le32 w2;
3956 } __packed;
3957
3958 #define RTW89_C2H_DONE_ACK_W2_CAT GENMASK(1, 0)
3959 #define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2)
3960 #define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8)
3961 #define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16)
3962 #define RTW89_C2H_SCAN_DONE_ACK_RETURN GENMASK(5, 0)
3963 #define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24)
3964
3965 struct rtw89_c2h_rev_ack {
3966 __le32 w0;
3967 __le32 w1;
3968 __le32 w2;
3969 } __packed;
3970
3971 #define RTW89_C2H_REV_ACK_W2_CAT GENMASK(1, 0)
3972 #define RTW89_C2H_REV_ACK_W2_CLASS GENMASK(7, 2)
3973 #define RTW89_C2H_REV_ACK_W2_FUNC GENMASK(15, 8)
3974 #define RTW89_C2H_REV_ACK_W2_H2C_SEQ GENMASK(23, 16)
3975
3976 struct rtw89_fw_c2h_log_fmt {
3977 __le16 signature;
3978 u8 feature;
3979 u8 syntax;
3980 __le32 fmt_id;
3981 u8 file_num;
3982 __le16 line_num;
3983 u8 argc;
3984 union {
3985 DECLARE_FLEX_ARRAY(u8, raw);
3986 DECLARE_FLEX_ARRAY(__le32, argv);
3987 } __packed u;
3988 } __packed;
3989
3990 #define RTW89_C2H_FW_FORMATTED_LOG_MIN_LEN 11
3991 #define RTW89_C2H_FW_LOG_FEATURE_PARA_INT BIT(2)
3992 #define RTW89_C2H_FW_LOG_MAX_PARA_NUM 16
3993 #define RTW89_C2H_FW_LOG_SIGNATURE 0xA5A5
3994 #define RTW89_C2H_FW_LOG_STR_BUF_SIZE 512
3995
3996 struct rtw89_c2h_bcn_upd_done {
3997 struct rtw89_c2h_hdr hdr;
3998 __le32 w2;
3999 } __packed;
4000
4001 #define RTW89_C2H_BCN_UPD_DONE_W2_PORT GENMASK(2, 0)
4002 #define RTW89_C2H_BCN_UPD_DONE_W2_MBSSID GENMASK(6, 3)
4003 #define RTW89_C2H_BCN_UPD_DONE_W2_BAND_IDX BIT(7)
4004
4005 struct rtw89_c2h_mac_bcnfltr_rpt {
4006 __le32 w0;
4007 __le32 w1;
4008 __le32 w2;
4009 } __packed;
4010
4011 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0)
4012 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8)
4013 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10)
4014 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16)
4015
4016 struct rtw89_c2h_ra_rpt {
4017 struct rtw89_c2h_hdr hdr;
4018 __le32 w2;
4019 __le32 w3;
4020 } __packed;
4021
4022 #define RTW89_C2H_RA_RPT_W2_MACID GENMASK(15, 0)
4023 #define RTW89_C2H_RA_RPT_W2_RETRY_RATIO GENMASK(23, 16)
4024 #define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31)
4025 #define RTW89_C2H_RA_RPT_W3_MCSNSS GENMASK(6, 0)
4026 #define RTW89_C2H_RA_RPT_W3_MD_SEL GENMASK(9, 8)
4027 #define RTW89_C2H_RA_RPT_W3_GILTF GENMASK(12, 10)
4028 #define RTW89_C2H_RA_RPT_W3_BW GENMASK(14, 13)
4029 #define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15)
4030 #define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16)
4031
4032 struct rtw89_c2h_lps_rpt {
4033 struct rtw89_c2h_hdr hdr;
4034 u8 type;
4035 u8 cnt_bbcr;
4036 u8 cnt_bbmcucr;
4037 u8 cnt_rfcr;
4038 u8 data[];
4039 /*
4040 * The layout of data:
4041 * u8 info[][4], size = total_len - size of below fields
4042 * __le16 bbcr_addr[], size = cnt_bbcr
4043 * __le32 bbcr_data[], size = cnt_bbcr
4044 * __le16 bbmcucr_addr[], size = cnt_bbmcucr
4045 * __le32 bbmcucr_data[], size = cnt_bbmcucr
4046 * __le16 rfcr_addr[], size = cnt_rfcr
4047 * __le32 rfcr_data_a[], size = cnt_rfcr
4048 * __le32 rfcr_data_b[], size = cnt_rfcr
4049 */
4050 } __packed;
4051
4052 struct rtw89_c2h_ra_tx_history {
4053 struct rtw89_c2h_hdr hdr;
4054 __le32 ra_tbtt_cnt;
4055 __le32 tx_rate_tot_cnt_hist[RTW89_TX_RATE_NR];
4056 __le32 tx_cat_cnt[3];
4057 } __packed;
4058
4059 struct rtw89_c2h_fw_scan_rpt {
4060 struct rtw89_c2h_hdr hdr;
4061 u8 phy_idx;
4062 u8 band;
4063 u8 center_ch;
4064 u8 ofdm_pd_idx; /* in unit of 2 dBm */
4065 #define PD_LOWER_BOUND_BASE 102
4066 s8 cck_pd_idx;
4067 u8 rsvd0;
4068 u8 rsvd1;
4069 u8 rsvd2;
4070 } __packed;
4071
4072 /* For WiFi 6 chips:
4073 * VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
4074 * HT-new: [6:5]: NA, [4:0]: MCS
4075 * For WiFi 7 chips (V1):
4076 * HT, VHT, HE, EHT: [7:5]: NSS, [4:0]: MCS
4077 */
4078 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
4079 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
4080 #define RTW89_RA_RATE_MASK_NSS_V1 GENMASK(7, 5)
4081 #define RTW89_RA_RATE_MASK_MCS_V1 GENMASK(4, 0)
4082 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
4083 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
4084 FIELD_PREP(GENMASK(2, 0), mcs))
4085
4086 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \
4087 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
4088 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \
4089 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))
4090 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \
4091 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))
4092
4093 struct rtw89_c2h_scanofld {
4094 __le32 w0;
4095 __le32 w1;
4096 __le32 w2;
4097 __le32 w3;
4098 __le32 w4;
4099 __le32 w5;
4100 __le32 w6;
4101 __le32 w7;
4102 __le32 w8;
4103 } __packed;
4104
4105 #define RTW89_C2H_SCANOFLD_W2_PRI_CH GENMASK(7, 0)
4106 #define RTW89_C2H_SCANOFLD_W2_RSN GENMASK(19, 16)
4107 #define RTW89_C2H_SCANOFLD_W2_STATUS GENMASK(23, 20)
4108 #define RTW89_C2H_SCANOFLD_W2_PERIOD GENMASK(31, 24)
4109 #define RTW89_C2H_SCANOFLD_W5_TX_FAIL GENMASK(3, 0)
4110 #define RTW89_C2H_SCANOFLD_W5_AIR_DENSITY GENMASK(7, 4)
4111 #define RTW89_C2H_SCANOFLD_W5_BAND GENMASK(25, 24)
4112 #define RTW89_C2H_SCANOFLD_W5_MAC_IDX BIT(26)
4113 #define RTW89_C2H_SCANOFLD_W6_SW_DEF GENMASK(7, 0)
4114 #define RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD GENMASK(15, 8)
4115 #define RTW89_C2H_SCANOFLD_W6_FW_DEF GENMASK(23, 16)
4116 #define RTW89_C2H_SCANOFLD_W7_REPORT_TSF GENMASK(31, 0)
4117 #define RTW89_C2H_SCANOFLD_W8_PERIOD_V1 GENMASK(15, 0)
4118 #define RTW89_C2H_SCANOFLD_W8_EXPECT_PERIOD_V1 GENMASK(31, 16)
4119
4120 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \
4121 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
4122 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \
4123 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
4124
4125 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \
4126 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
4127 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \
4128 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
4129 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \
4130 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
4131
4132 struct rtw89_c2h_mac_tx_rpt {
4133 struct rtw89_c2h_hdr hdr;
4134 __le32 w2;
4135 __le32 w3;
4136 __le32 w4;
4137 __le32 w5;
4138 __le32 w6;
4139 __le32 w7;
4140 } __packed;
4141
4142 #define RTW89_C2H_MAC_TX_RPT_W2_TX_STATE GENMASK(7, 6)
4143 #define RTW89_C2H_MAC_TX_RPT_W2_SW_DEFINE GENMASK(11, 8)
4144 #define RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT GENMASK(13, 8)
4145 #define RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT_V1 GENMASK(15, 10)
4146
4147 struct rtw89_c2h_mac_tx_rpt_v2 {
4148 struct rtw89_c2h_hdr hdr;
4149 __le32 w2;
4150 __le32 w3;
4151 __le32 w4;
4152 __le32 w5;
4153 __le32 w6;
4154 __le32 w7;
4155 __le32 w8;
4156 __le32 w9;
4157 __le32 w10;
4158 __le32 w11;
4159 __le32 w12;
4160 __le32 w13;
4161 __le32 w14;
4162 __le32 w15;
4163 __le32 w16;
4164 __le32 w17;
4165 __le32 w18;
4166 __le32 w19;
4167 } __packed;
4168
4169 #define RTW89_C2H_MAC_TX_RPT_W12_TX_STATE_V2 GENMASK(9, 8)
4170 #define RTW89_C2H_MAC_TX_RPT_W12_SW_DEFINE_V2 GENMASK(15, 12)
4171 #define RTW89_C2H_MAC_TX_RPT_W14_DATA_TX_CNT_V2 GENMASK(15, 10)
4172
4173 struct rtw89_mac_mcc_tsf_rpt {
4174 u32 macid_x;
4175 u32 macid_y;
4176 u32 tsf_x_low;
4177 u32 tsf_x_high;
4178 u32 tsf_y_low;
4179 u32 tsf_y_high;
4180 };
4181
4182 static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
4183
4184 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \
4185 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
4186 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \
4187 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
4188 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \
4189 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16))
4190 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \
4191 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
4192 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \
4193 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
4194 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \
4195 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0))
4196 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \
4197 le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0))
4198
4199 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \
4200 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0))
4201 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \
4202 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6))
4203 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \
4204 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
4205 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \
4206 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
4207 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \
4208 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
4209
4210 struct rtw89_c2h_mlo_link_cfg_rpt {
4211 struct rtw89_c2h_hdr hdr;
4212 __le32 w2;
4213 } __packed;
4214
4215 #define RTW89_C2H_MLO_LINK_CFG_RPT_W2_MACID GENMASK(15, 0)
4216 #define RTW89_C2H_MLO_LINK_CFG_RPT_W2_STATUS GENMASK(19, 16)
4217
4218 enum rtw89_c2h_mlo_link_status {
4219 RTW89_C2H_MLO_LINK_CFG_IDLE = 0,
4220 RTW89_C2H_MLO_LINK_CFG_DONE = 1,
4221 RTW89_C2H_MLO_LINK_CFG_ISSUE_NULL_FAIL = 2,
4222 RTW89_C2H_MLO_LINK_CFG_TX_NULL_FAIL = 3,
4223 RTW89_C2H_MLO_LINK_CFG_ROLE_NOT_EXIST = 4,
4224 RTW89_C2H_MLO_LINK_CFG_NULL_1_TIMEOUT = 5,
4225 RTW89_C2H_MLO_LINK_CFG_NULL_0_TIMEOUT = 6,
4226 RTW89_C2H_MLO_LINK_CFG_RUNNING = 0xff,
4227 };
4228
4229 struct rtw89_mac_mrc_tsf_rpt {
4230 unsigned int num;
4231 u64 tsfs[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
4232 };
4233
4234 static_assert(sizeof(struct rtw89_mac_mrc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
4235
4236 struct rtw89_c2h_mrc_tsf_rpt_info {
4237 __le32 tsf_low;
4238 __le32 tsf_high;
4239 } __packed;
4240
4241 struct rtw89_c2h_mrc_tsf_rpt {
4242 struct rtw89_c2h_hdr hdr;
4243 __le32 w2;
4244 struct rtw89_c2h_mrc_tsf_rpt_info infos[];
4245 } __packed;
4246
4247 #define RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM GENMASK(7, 0)
4248
4249 struct rtw89_c2h_mrc_status_rpt {
4250 struct rtw89_c2h_hdr hdr;
4251 __le32 w2;
4252 __le32 tsf_low;
4253 __le32 tsf_high;
4254 } __packed;
4255
4256 #define RTW89_C2H_MRC_STATUS_RPT_W2_STATUS GENMASK(5, 0)
4257 #define RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX GENMASK(7, 6)
4258
4259 struct rtw89_c2h_pkt_ofld_rsp {
4260 __le32 w0;
4261 __le32 w1;
4262 __le32 w2;
4263 } __packed;
4264
4265 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0)
4266 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8)
4267 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16)
4268
4269 struct rtw89_c2h_tx_duty_rpt {
4270 struct rtw89_c2h_hdr c2h_hdr;
4271 __le32 w2;
4272 } __packed;
4273
4274 #define RTW89_C2H_TX_DUTY_RPT_W2_TIMER_ERR GENMASK(2, 0)
4275
4276 struct rtw89_c2h_wow_aoac_report {
4277 struct rtw89_c2h_hdr c2h_hdr;
4278 u8 rpt_ver;
4279 u8 sec_type;
4280 u8 key_idx;
4281 u8 pattern_idx;
4282 u8 rekey_ok;
4283 u8 rsvd1[3];
4284 u8 ptk_tx_iv[8];
4285 u8 eapol_key_replay_count[8];
4286 u8 gtk[32];
4287 u8 ptk_rx_iv[8];
4288 u8 gtk_rx_iv[4][8];
4289 __le64 igtk_key_id;
4290 __le64 igtk_ipn;
4291 u8 igtk[32];
4292 u8 csa_pri_ch;
4293 u8 csa_bw_ch_offset;
4294 u8 csa_ch_band_chsw_failed;
4295 u8 csa_rsvd1;
4296 } __packed;
4297
4298 #define RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX BIT(0)
4299
4300 struct rtw89_c2h_pwr_int_notify {
4301 struct rtw89_c2h_hdr hdr;
4302 __le32 w2;
4303 } __packed;
4304
4305 #define RTW89_C2H_PWR_INT_NOTIFY_W2_MACID GENMASK(15, 0)
4306 #define RTW89_C2H_PWR_INT_NOTIFY_W2_PWR_STATUS BIT(16)
4307
4308 struct rtw89_h2c_tx_duty {
4309 __le32 w0;
4310 __le32 w1;
4311 } __packed;
4312
4313 #define RTW89_H2C_TX_DUTY_W0_PAUSE_INTVL_MASK GENMASK(15, 0)
4314 #define RTW89_H2C_TX_DUTY_W0_TX_INTVL_MASK GENMASK(31, 16)
4315 #define RTW89_H2C_TX_DUTY_W1_STOP BIT(0)
4316
4317 struct rtw89_h2c_bcnfltr {
4318 __le32 w0;
4319 } __packed;
4320
4321 #define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0)
4322 #define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1)
4323 #define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2)
4324 #define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3)
4325 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT_H3 GENMASK(7, 5)
4326 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT_L4 GENMASK(11, 8)
4327 #define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12)
4328 #define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16)
4329 #define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24)
4330
4331 struct rtw89_h2c_ofld_rssi {
4332 __le32 w0;
4333 __le32 w1;
4334 } __packed;
4335
4336 #define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0)
4337 #define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8)
4338 #define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0)
4339
4340 struct rtw89_h2c_ofld {
4341 __le32 w0;
4342 } __packed;
4343
4344 #define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0)
4345 #define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8)
4346 #define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18)
4347
4348 #define RTW89_MFW_SIG 0xFF
4349
4350 struct rtw89_mfw_info {
4351 u8 cv;
4352 u8 type; /* enum rtw89_fw_type */
4353 u8 mp;
4354 u8 rsvd;
4355 __le32 shift;
4356 __le32 size;
4357 u8 rsvd2[4];
4358 } __packed;
4359
4360 struct rtw89_mfw_hdr {
4361 u8 sig; /* RTW89_MFW_SIG */
4362 u8 fw_nr;
4363 u8 rsvd0[2];
4364 struct {
4365 u8 major;
4366 u8 minor;
4367 u8 sub;
4368 u8 idx;
4369 } ver;
4370 u8 rsvd1[8];
4371 struct rtw89_mfw_info info[];
4372 } __packed;
4373
4374 struct rtw89_fw_logsuit_hdr {
4375 __le32 rsvd;
4376 __le32 count;
4377 __le32 ids[];
4378 } __packed;
4379
4380 #define RTW89_FW_ELEMENT_ALIGN 16
4381
4382 enum rtw89_fw_element_id {
4383 RTW89_FW_ELEMENT_ID_BBMCU0 = 0,
4384 RTW89_FW_ELEMENT_ID_BBMCU1 = 1,
4385 RTW89_FW_ELEMENT_ID_BB_REG = 2,
4386 RTW89_FW_ELEMENT_ID_BB_GAIN = 3,
4387 RTW89_FW_ELEMENT_ID_RADIO_A = 4,
4388 RTW89_FW_ELEMENT_ID_RADIO_B = 5,
4389 RTW89_FW_ELEMENT_ID_RADIO_C = 6,
4390 RTW89_FW_ELEMENT_ID_RADIO_D = 7,
4391 RTW89_FW_ELEMENT_ID_RF_NCTL = 8,
4392 RTW89_FW_ELEMENT_ID_TXPWR_BYRATE = 9,
4393 RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ = 10,
4394 RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ = 11,
4395 RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ = 12,
4396 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ = 13,
4397 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ = 14,
4398 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ = 15,
4399 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT = 16,
4400 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU = 17,
4401 RTW89_FW_ELEMENT_ID_TXPWR_TRK = 18,
4402 RTW89_FW_ELEMENT_ID_RFKLOG_FMT = 19,
4403 RTW89_FW_ELEMENT_ID_REGD = 20,
4404 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_2GHZ = 21,
4405 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_5GHZ = 22,
4406 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_6GHZ = 23,
4407 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_2GHZ = 24,
4408 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_5GHZ = 25,
4409 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_6GHZ = 26,
4410 RTW89_FW_ELEMENT_ID_AFE_PWR_SEQ = 27,
4411 RTW89_FW_ELEMENT_ID_DIAG_MAC = 28,
4412 RTW89_FW_ELEMENT_ID_TX_COMP = 29,
4413
4414 __RTW89_FW_ELEMENT_ID_INTL_TRANSITION,
4415 RTW89_FW_ELEMENT_ID_NUM,
4416 };
4417
4418 #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS_TX_SHAPE \
4419 (BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT) | \
4420 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU))
4421
4422 #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ \
4423 (BIT(RTW89_FW_ELEMENT_ID_TXPWR_BYRATE) | \
4424 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ) | \
4425 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ) | \
4426 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ) | \
4427 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ) | \
4428 BITS_OF_RTW89_TXPWR_FW_ELEMENTS_TX_SHAPE)
4429
4430 #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS \
4431 (BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ | \
4432 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ) | \
4433 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ))
4434
4435 #define RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_BASE \
4436 (BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
4437 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
4438 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
4439 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
4440 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK))
4441
4442 #define RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_NO_6GHZ \
4443 (RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_BASE | \
4444 BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ)
4445
4446 #define RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS \
4447 (RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_BASE | \
4448 BITS_OF_RTW89_TXPWR_FW_ELEMENTS)
4449
4450 #define RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_RTL8852A \
4451 (RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_NO_6GHZ & \
4452 ~BITS_OF_RTW89_TXPWR_FW_ELEMENTS_TX_SHAPE)
4453
4454 #define RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_RTL8851B \
4455 (RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_NO_6GHZ & \
4456 ~BIT(RTW89_FW_ELEMENT_ID_RADIO_B))
4457
4458 #define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS_BASE \
4459 (BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
4460 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
4461 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
4462 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
4463 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
4464 BITS_OF_RTW89_TXPWR_FW_ELEMENTS)
4465
4466 #define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS \
4467 (RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS_BASE | \
4468 BIT(RTW89_FW_ELEMENT_ID_BBMCU0))
4469
4470 #define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS_V1 \
4471 (RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS_BASE | \
4472 BIT(RTW89_FW_ELEMENT_ID_AFE_PWR_SEQ) | \
4473 BIT(RTW89_FW_ELEMENT_ID_TX_COMP))
4474
4475 struct __rtw89_fw_txpwr_element {
4476 u8 rsvd0;
4477 u8 rsvd1;
4478 u8 rfe_type;
4479 u8 ent_sz;
4480 __le32 num_ents;
4481 u8 content[];
4482 } __packed;
4483
4484 struct __rtw89_fw_regd_element {
4485 u8 rsvd0;
4486 u8 rsvd1;
4487 u8 rsvd2;
4488 u8 ent_sz;
4489 __le32 num_ents;
4490 u8 content[];
4491 } __packed;
4492
4493 enum rtw89_fw_txpwr_trk_type {
4494 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_START = 0,
4495 RTW89_FW_TXPWR_TRK_TYPE_6GB_N = 0,
4496 RTW89_FW_TXPWR_TRK_TYPE_6GB_P = 1,
4497 RTW89_FW_TXPWR_TRK_TYPE_6GA_N = 2,
4498 RTW89_FW_TXPWR_TRK_TYPE_6GA_P = 3,
4499 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_MAX = 3,
4500
4501 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_START = 4,
4502 RTW89_FW_TXPWR_TRK_TYPE_5GB_N = 4,
4503 RTW89_FW_TXPWR_TRK_TYPE_5GB_P = 5,
4504 RTW89_FW_TXPWR_TRK_TYPE_5GA_N = 6,
4505 RTW89_FW_TXPWR_TRK_TYPE_5GA_P = 7,
4506 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_MAX = 7,
4507
4508 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_START = 8,
4509 RTW89_FW_TXPWR_TRK_TYPE_2GB_N = 8,
4510 RTW89_FW_TXPWR_TRK_TYPE_2GB_P = 9,
4511 RTW89_FW_TXPWR_TRK_TYPE_2GA_N = 10,
4512 RTW89_FW_TXPWR_TRK_TYPE_2GA_P = 11,
4513 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N = 12,
4514 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P = 13,
4515 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N = 14,
4516 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P = 15,
4517 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_MAX = 15,
4518
4519 RTW89_FW_TXPWR_TRK_TYPE_NR,
4520 };
4521
4522 struct rtw89_fw_txpwr_track_cfg {
4523 const s8 (*delta[RTW89_FW_TXPWR_TRK_TYPE_NR])[DELTA_SWINGIDX_SIZE];
4524 };
4525
4526 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_6GHZ \
4527 (BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_N) | \
4528 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_P) | \
4529 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_N) | \
4530 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_P))
4531 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_5GHZ \
4532 (BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_N) | \
4533 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_P) | \
4534 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_N) | \
4535 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_P))
4536 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_2GHZ \
4537 (BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_N) | \
4538 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_P) | \
4539 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_N) | \
4540 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_P) | \
4541 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N) | \
4542 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P) | \
4543 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N) | \
4544 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P))
4545
4546 enum rtw89_fw_afe_action {
4547 RTW89_FW_AFE_ACTION_WRITE = 0,
4548 RTW89_FW_AFE_ACTION_DELAY = 1,
4549 RTW89_FW_AFE_ACTION_POLL = 2,
4550 };
4551
4552 enum rtw89_fw_afe_cat {
4553 RTW89_FW_AFE_CAT_BB = 0,
4554 RTW89_FW_AFE_CAT_BB1 = 1,
4555 RTW89_FW_AFE_CAT_MAC = 2,
4556 RTW89_FW_AFE_CAT_MAC1 = 3,
4557 RTW89_FW_AFE_CAT_AFEDIG = 4,
4558 RTW89_FW_AFE_CAT_AFEDIG1 = 5,
4559 };
4560
4561 enum rtw89_fw_afe_class {
4562 RTW89_FW_AFE_CLASS_P0 = 0,
4563 RTW89_FW_AFE_CLASS_P1 = 1,
4564 RTW89_FW_AFE_CLASS_P2 = 2,
4565 RTW89_FW_AFE_CLASS_P3 = 3,
4566 RTW89_FW_AFE_CLASS_P4 = 4,
4567 RTW89_FW_AFE_CLASS_CMN = 5,
4568 };
4569
4570 struct rtw89_fw_element_hdr {
4571 __le32 id; /* enum rtw89_fw_element_id */
4572 __le32 size; /* exclude header size */
4573 u8 ver[4];
4574 __le16 aid; /* should match rtw89_hal::aid */
4575 __le16 rsvd0;
4576 __le32 rsvd1;
4577 __le32 rsvd2;
4578 union {
4579 struct {
4580 u8 priv[8];
4581 u8 contents[];
4582 } __packed common;
4583 struct {
4584 u8 idx;
4585 u8 rsvd[7];
4586 struct {
4587 __le32 addr;
4588 __le32 data;
4589 } __packed regs[];
4590 } __packed reg2;
4591 struct {
4592 u8 cv;
4593 u8 priv[7];
4594 u8 contents[];
4595 } __packed bbmcu;
4596 struct {
4597 __le32 bitmap; /* bitmap of enum rtw89_fw_txpwr_trk_type */
4598 __le32 rsvd;
4599 s8 contents[][DELTA_SWINGIDX_SIZE];
4600 } __packed txpwr_trk;
4601 struct {
4602 u8 nr;
4603 u8 rsvd[3];
4604 u8 rfk_id; /* enum rtw89_phy_c2h_rfk_log_func */
4605 u8 rsvd1[3];
4606 __le16 offset[];
4607 } __packed rfk_log_fmt;
4608 struct {
4609 u8 rsvd[8];
4610 struct rtw89_phy_afe_info {
4611 __le32 action; /* enum rtw89_fw_afe_action */
4612 __le32 cat; /* enum rtw89_fw_afe_cat */
4613 __le32 class; /* enum rtw89_fw_afe_class */
4614 __le32 addr;
4615 __le32 mask;
4616 __le32 val;
4617 } __packed infos[];
4618 } __packed afe;
4619 struct {
4620 __le32 rule_size;
4621 u8 rsvd[4];
4622 u8 rules_and_msgs[];
4623 } __packed diag_mac;
4624 struct {
4625 u8 rfe_type;
4626 u8 priv[7];
4627 u8 contents[];
4628 } __packed tx_comp;
4629 struct __rtw89_fw_txpwr_element txpwr;
4630 struct __rtw89_fw_regd_element regd;
4631 } __packed u;
4632 } __packed;
4633
4634 struct fwcmd_hdr {
4635 __le32 hdr0;
4636 __le32 hdr1;
4637 };
4638
4639 union rtw89_compat_fw_hdr {
4640 struct rtw89_mfw_hdr mfw_hdr;
4641 struct rtw89_fw_hdr fw_hdr;
4642 };
4643
rtw89_compat_fw_hdr_ver_code(const void * fw_buf)4644 static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf)
4645 {
4646 const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf;
4647
4648 if (compat->mfw_hdr.sig == RTW89_MFW_SIG)
4649 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr);
4650 else
4651 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr);
4652 }
4653
rtw89_fw_get_filename(char * buf,size_t size,const char * fw_basename,int fw_format)4654 static inline void rtw89_fw_get_filename(char *buf, size_t size,
4655 const char *fw_basename, int fw_format)
4656 {
4657 if (fw_format <= 0)
4658 snprintf(buf, size, "%s.bin", fw_basename);
4659 else
4660 snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format);
4661 }
4662
4663 #define RTW89_H2C_RF_PAGE_SIZE 500
4664 #define RTW89_H2C_RF_PAGE_NUM 3
4665 struct rtw89_fw_h2c_rf_reg_info {
4666 enum rtw89_rf_path rf_path;
4667 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE];
4668 u16 curr_idx;
4669 };
4670
4671 #define H2C_SEC_CAM_LEN 24
4672
4673 #define H2C_HEADER_LEN 8
4674 #define H2C_HDR_CAT GENMASK(1, 0)
4675 #define H2C_HDR_CLASS GENMASK(7, 2)
4676 #define H2C_HDR_FUNC GENMASK(15, 8)
4677 #define H2C_HDR_DEL_TYPE GENMASK(19, 16)
4678 #define H2C_HDR_H2C_SEQ GENMASK(31, 24)
4679 #define H2C_HDR_TOTAL_LEN GENMASK(13, 0)
4680 #define H2C_HDR_REC_ACK BIT(14)
4681 #define H2C_HDR_DONE_ACK BIT(15)
4682
4683 #define FWCMD_TYPE_H2C 0
4684
4685 #define H2C_CAT_TEST 0x0
4686
4687 /* CLASS 5 - FW STATUS TEST */
4688 #define H2C_CL_FW_STATUS_TEST 0x5
4689 #define H2C_FUNC_CPU_EXCEPTION 0x1
4690
4691 #define H2C_CAT_MAC 0x1
4692
4693 /* CLASS 0 - FW INFO */
4694 #define H2C_CL_FW_INFO 0x0
4695 #define H2C_FUNC_LOG_CFG 0x0
4696 #define H2C_FUNC_MAC_GENERAL_PKT 0x1
4697
4698 /* CLASS 1 - WOW */
4699 #define H2C_CL_MAC_WOW 0x1
4700 enum rtw89_wow_h2c_func {
4701 H2C_FUNC_KEEP_ALIVE = 0x0,
4702 H2C_FUNC_DISCONNECT_DETECT = 0x1,
4703 H2C_FUNC_WOW_GLOBAL = 0x2,
4704 H2C_FUNC_GTK_OFLD = 0x3,
4705 H2C_FUNC_ARP_OFLD = 0x4,
4706 H2C_FUNC_NLO = 0x7,
4707 H2C_FUNC_WAKEUP_CTRL = 0x8,
4708 H2C_FUNC_WOW_CAM_UPD = 0xC,
4709 H2C_FUNC_AOAC_REPORT_REQ = 0xD,
4710 H2C_FUNC_WOW_PLD_CAM_UPD = 0x12,
4711
4712 NUM_OF_RTW89_WOW_H2C_FUNC,
4713 };
4714
4715 #define RTW89_WOW_WAIT_COND(tag, func) \
4716 ((tag) * NUM_OF_RTW89_WOW_H2C_FUNC + (func))
4717
4718 #define RTW89_WOW_WAIT_COND_AOAC \
4719 RTW89_WOW_WAIT_COND(0 /* don't care */, H2C_FUNC_AOAC_REPORT_REQ)
4720
4721 /* CLASS 2 - PS */
4722 #define H2C_CL_MAC_PS 0x2
4723 enum rtw89_ps_h2c_func {
4724 H2C_FUNC_MAC_LPS_PARM = 0x0,
4725 H2C_FUNC_P2P_ACT = 0x1,
4726 H2C_FUNC_IPS_CFG = 0x3,
4727 H2C_FUNC_PS_POWER_LEVEL = 0x7,
4728 H2C_FUNC_TBTT_TUNING = 0xA,
4729
4730 NUM_OF_RTW89_PS_H2C_FUNC,
4731 };
4732
4733 #define RTW89_PS_WAIT_COND(tag, func) \
4734 ((tag) * NUM_OF_RTW89_PS_H2C_FUNC + (func))
4735
4736 #define RTW89_PS_WAIT_COND_IPS_CFG \
4737 RTW89_PS_WAIT_COND(0 /* don't care */, H2C_FUNC_IPS_CFG)
4738
4739 /* CLASS 3 - FW download */
4740 #define H2C_CL_MAC_FWDL 0x3
4741 #define H2C_FUNC_MAC_FWHDR_DL 0x0
4742
4743 /* CLASS 5 - Frame Exchange */
4744 #define H2C_CL_MAC_FR_EXCHG 0x5
4745 #define H2C_FUNC_MAC_CCTLINFO_UD 0x2
4746 #define H2C_FUNC_MAC_BCN_UPD 0x5
4747 #define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9
4748 #define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa
4749 #define H2C_FUNC_MAC_DCTLINFO_UD_V2 0xc
4750 #define H2C_FUNC_MAC_BCN_UPD_BE 0xd
4751 #define H2C_FUNC_MAC_DCTLINFO_UD_V3 0x10
4752 #define H2C_FUNC_MAC_CCTLINFO_UD_G7 0x11
4753
4754 /* CLASS 6 - Address CAM */
4755 #define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6
4756 #define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0
4757
4758 /* CLASS 8 - Media Status Report */
4759 #define H2C_CL_MAC_MEDIA_RPT 0x8
4760 #define H2C_FUNC_MAC_JOININFO 0x0
4761 #define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4
4762 #define H2C_FUNC_NOTIFY_DBCC 0x5
4763
4764 /* CLASS 9 - FW offload */
4765 #define H2C_CL_MAC_FW_OFLD 0x9
4766 enum rtw89_fw_ofld_h2c_func {
4767 H2C_FUNC_PACKET_OFLD = 0x1,
4768 H2C_FUNC_MAC_MACID_PAUSE = 0x8,
4769 H2C_FUNC_USR_EDCA = 0xF,
4770 H2C_FUNC_TSF32_TOGL = 0x10,
4771 H2C_FUNC_CMD_OFLD_PKT = 0x13,
4772 H2C_FUNC_OFLD_CFG = 0x14,
4773 H2C_FUNC_ADD_SCANOFLD_CH = 0x16,
4774 H2C_FUNC_SCANOFLD = 0x17,
4775 H2C_FUNC_TX_DUTY = 0x18,
4776 H2C_FUNC_PKT_DROP = 0x1b,
4777 H2C_FUNC_CFG_BCNFLTR = 0x1e,
4778 H2C_FUNC_OFLD_RSSI = 0x1f,
4779 H2C_FUNC_OFLD_TP = 0x20,
4780 H2C_FUNC_MAC_MACID_PAUSE_SLEEP = 0x28,
4781 H2C_FUNC_SCANOFLD_BE = 0x2c,
4782 H2C_FUNC_TRX_PROTECT = 0x34,
4783
4784 NUM_OF_RTW89_FW_OFLD_H2C_FUNC,
4785 };
4786
4787 #define RTW89_FW_OFLD_WAIT_COND(tag, func) \
4788 ((tag) * NUM_OF_RTW89_FW_OFLD_H2C_FUNC + (func))
4789
4790 #define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \
4791 RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \
4792 H2C_FUNC_PACKET_OFLD)
4793 #define RTW89_FW_OFLD_WAIT_COND_TRX_PROTECT RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_TRX_PROTECT)
4794
4795 #define RTW89_SCANOFLD_WAIT_COND_ADD_CH RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_ADD_SCANOFLD_CH)
4796
4797 #define RTW89_SCANOFLD_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD)
4798 #define RTW89_SCANOFLD_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD)
4799 #define RTW89_SCANOFLD_BE_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD_BE)
4800 #define RTW89_SCANOFLD_BE_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD_BE)
4801
4802
4803 /* CLASS 10 - Security CAM */
4804 #define H2C_CL_MAC_SEC_CAM 0xa
4805 #define H2C_FUNC_MAC_SEC_UPD 0x1
4806
4807 /* CLASS 12 - BA CAM */
4808 #define H2C_CL_BA_CAM 0xc
4809 #define H2C_FUNC_MAC_BA_CAM 0x0
4810 #define H2C_FUNC_MAC_BA_CAM_V1 0x1
4811 #define H2C_FUNC_MAC_BA_CAM_INIT 0x2
4812
4813 /* CLASS 14 - MCC */
4814 #define H2C_CL_MCC 0xe
4815 enum rtw89_mcc_h2c_func {
4816 H2C_FUNC_ADD_MCC = 0x0,
4817 H2C_FUNC_START_MCC = 0x1,
4818 H2C_FUNC_STOP_MCC = 0x2,
4819 H2C_FUNC_DEL_MCC_GROUP = 0x3,
4820 H2C_FUNC_RESET_MCC_GROUP = 0x4,
4821 H2C_FUNC_MCC_REQ_TSF = 0x5,
4822 H2C_FUNC_MCC_MACID_BITMAP = 0x6,
4823 H2C_FUNC_MCC_SYNC = 0x7,
4824 H2C_FUNC_MCC_SET_DURATION = 0x8,
4825
4826 NUM_OF_RTW89_MCC_H2C_FUNC,
4827 };
4828
4829 #define RTW89_MCC_WAIT_COND(group, func) \
4830 ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func))
4831
4832 /* CLASS 20 - MLO */
4833 #define H2C_CL_MLO 0x14
4834 enum rtw89_mlo_h2c_func {
4835 H2C_FUNC_MLO_TBL_CFG = 0x0,
4836 H2C_FUNC_MLO_STA_CFG = 0x1,
4837 H2C_FUNC_MLO_TTLM = 0x2,
4838 H2C_FUNC_MLO_DM_CFG = 0x3,
4839 H2C_FUNC_MLO_EMLSR_STA_CFG = 0x4,
4840 H2C_FUNC_MLO_MCMLO_RELINK_DROP = 0x5,
4841 H2C_FUNC_MLO_MCMLO_SN_SYNC = 0x6,
4842 H2C_FUNC_MLO_RELINK = 0x7,
4843 H2C_FUNC_MLO_LINK_CFG = 0x8,
4844 H2C_FUNC_MLO_DM_DBG = 0x9,
4845
4846 NUM_OF_RTW89_MLO_H2C_FUNC,
4847 };
4848
4849 #define RTW89_MLO_WAIT_COND(macid, func) \
4850 ((macid) * NUM_OF_RTW89_MLO_H2C_FUNC + (func))
4851
4852 /* CLASS 24 - MRC */
4853 #define H2C_CL_MRC 0x18
4854 enum rtw89_mrc_h2c_func {
4855 H2C_FUNC_MRC_REQ_TSF = 0x0,
4856 H2C_FUNC_ADD_MRC = 0x1,
4857 H2C_FUNC_START_MRC = 0x2,
4858 H2C_FUNC_DEL_MRC = 0x3,
4859 H2C_FUNC_MRC_SYNC = 0x4,
4860 H2C_FUNC_MRC_UPD_DURATION = 0x5,
4861 H2C_FUNC_MRC_UPD_BITMAP = 0x6,
4862
4863 NUM_OF_RTW89_MRC_H2C_FUNC,
4864 };
4865
4866 /* can consider MRC's sch_idx as MCC's group */
4867 #define RTW89_MRC_WAIT_COND(sch_idx, func) \
4868 ((sch_idx) * NUM_OF_RTW89_MRC_H2C_FUNC + (func))
4869
4870 #define RTW89_MRC_WAIT_COND_REQ_TSF \
4871 RTW89_MRC_WAIT_COND(0 /* don't care */, H2C_FUNC_MRC_REQ_TSF)
4872
4873 /* CLASS 36 - AP */
4874 #define H2C_CL_AP 0x24
4875 #define H2C_FUNC_AP_INFO 0x0
4876
4877 #define H2C_CAT_OUTSRC 0x2
4878
4879 #define H2C_CL_OUTSRC_RA 0x1
4880 #define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0
4881 #define H2C_FUNC_OUTSRC_RA_TX_HISTORY 0x9
4882 #define H2C_FUNC_OUTSRC_RA_PHY_CH_RPT 0xe
4883 #define H2C_FUNC_OUTSRC_RA_DRV_CTRL_FW 0xf
4884
4885 #define H2C_CL_OUTSRC_DM 0x2
4886 #define H2C_FUNC_FW_MCC_DIG 0x6
4887 #define H2C_FUNC_FW_LPS_CH_INFO 0xb
4888 #define H2C_FUNC_FW_LPS_ML_CMN_INFO 0xe
4889
4890 #define H2C_CL_OUTSRC_RF_REG_A 0x8
4891 #define H2C_CL_OUTSRC_RF_REG_B 0x9
4892 #define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa
4893 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2
4894 #define H2C_FUNC_OUTSRC_RF_MCC_INFO 0xf
4895 #define H2C_FUNC_OUTSRC_RF_PS_INFO 0x10
4896 #define H2C_CL_OUTSRC_RF_FW_RFK 0xb
4897
4898 enum rtw89_rfk_offload_h2c_func {
4899 H2C_FUNC_RFK_TSSI_OFFLOAD = 0x0,
4900 H2C_FUNC_RFK_IQK_OFFLOAD = 0x1,
4901 H2C_FUNC_RFK_DPK_OFFLOAD = 0x3,
4902 H2C_FUNC_RFK_TXGAPK_OFFLOAD = 0x4,
4903 H2C_FUNC_RFK_DACK_OFFLOAD = 0x5,
4904 H2C_FUNC_RFK_RXDCK_OFFLOAD = 0x6,
4905 H2C_FUNC_RFK_PRE_NOTIFY = 0x8,
4906 H2C_FUNC_RFK_TAS_OFFLOAD = 0x9,
4907 H2C_FUNC_RFK_TXIQK_OFFOAD = 0xc,
4908 H2C_FUNC_RFK_CIM3K_OFFOAD = 0xe,
4909 };
4910
4911 struct rtw89_fw_h2c_rf_get_mccch {
4912 __le32 ch_0_0;
4913 __le32 ch_0_1;
4914 __le32 ch_1_0;
4915 __le32 ch_1_1;
4916 __le32 current_channel;
4917 } __packed;
4918
4919 struct rtw89_fw_h2c_rf_get_mccch_v0 {
4920 __le32 ch_0;
4921 __le32 ch_1;
4922 __le32 band_0;
4923 __le32 band_1;
4924 __le32 current_channel;
4925 __le32 current_band_type;
4926 } __packed;
4927
4928 struct rtw89_h2c_mcc_dig {
4929 __le32 w0;
4930 __le32 w1;
4931 __le32 w2;
4932 } __packed;
4933
4934 #define RTW89_H2C_MCC_DIG_W0_REG_CNT GENMASK(7, 0)
4935 #define RTW89_H2C_MCC_DIG_W0_DM_EN BIT(8)
4936 #define RTW89_H2C_MCC_DIG_W0_IDX GENMASK(10, 9)
4937 #define RTW89_H2C_MCC_DIG_W0_SET BIT(11)
4938 #define RTW89_H2C_MCC_DIG_W0_PHY0_EN BIT(12)
4939 #define RTW89_H2C_MCC_DIG_W0_PHY1_EN BIT(13)
4940 #define RTW89_H2C_MCC_DIG_W0_CENTER_CH GENMASK(23, 16)
4941 #define RTW89_H2C_MCC_DIG_W0_BAND_TYPE GENMASK(31, 24)
4942 #define RTW89_H2C_MCC_DIG_W1_ADDR_LSB GENMASK(7, 0)
4943 #define RTW89_H2C_MCC_DIG_W1_ADDR_MSB GENMASK(15, 8)
4944 #define RTW89_H2C_MCC_DIG_W1_BMASK_LSB GENMASK(23, 16)
4945 #define RTW89_H2C_MCC_DIG_W1_BMASK_MSB GENMASK(31, 24)
4946 #define RTW89_H2C_MCC_DIG_W2_VAL_LSB GENMASK(7, 0)
4947 #define RTW89_H2C_MCC_DIG_W2_VAL_MSB GENMASK(15, 8)
4948
4949 #define NUM_OF_RTW89_FW_RFK_PATH 2
4950 #define NUM_OF_RTW89_FW_RFK_TBL 3
4951
4952 struct rtw89_h2c_rf_ps_info {
4953 __le32 rf18[NUM_OF_RTW89_FW_RFK_PATH];
4954 __le32 mlo_mode;
4955 u8 pri_ch[NUM_OF_RTW89_FW_RFK_PATH];
4956 } __packed;
4957
4958 struct rtw89_fw_h2c_rfk_pre_info_common {
4959 struct {
4960 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4961 __le32 band[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4962 } __packed dbcc;
4963
4964 __le32 mlo_mode;
4965 struct {
4966 __le32 cur_ch[NUM_OF_RTW89_FW_RFK_PATH];
4967 __le32 cur_band[NUM_OF_RTW89_FW_RFK_PATH];
4968 } __packed tbl;
4969
4970 __le32 phy_idx;
4971 } __packed;
4972
4973 struct rtw89_fw_h2c_rfk_pre_info_v0 {
4974 struct rtw89_fw_h2c_rfk_pre_info_common common;
4975
4976 __le32 cur_band;
4977 __le32 cur_bw;
4978 __le32 cur_center_ch;
4979
4980 __le32 ktbl_sel0;
4981 __le32 ktbl_sel1;
4982 __le32 rfmod0;
4983 __le32 rfmod1;
4984
4985 __le32 mlo_1_1;
4986 __le32 rfe_type;
4987 __le32 drv_mode;
4988
4989 struct {
4990 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH];
4991 __le32 band[NUM_OF_RTW89_FW_RFK_PATH];
4992 } __packed mlo;
4993 } __packed;
4994
4995 struct rtw89_fw_h2c_rfk_pre_info_v1 {
4996 struct rtw89_fw_h2c_rfk_pre_info_common common;
4997 __le32 mlo_1_1;
4998 } __packed;
4999
5000 struct rtw89_fw_h2c_rfk_pre_info_v2 {
5001 struct rtw89_fw_h2c_rfk_pre_info_v1 base_v1;
5002 __le32 cur_bandwidth[NUM_OF_RTW89_FW_RFK_PATH];
5003 } __packed;
5004
5005 struct rtw89_fw_h2c_rfk_pre_info {
5006 __le32 mlo_mode;
5007 __le32 phy_idx;
5008 __le32 mlo_1_1;
5009 } __packed;
5010
5011 struct rtw89_fw_h2c_rfk_pre_info_mcc_v0 {
5012 __le32 tbl_18[NUM_OF_RTW89_FW_RFK_TBL][NUM_OF_RTW89_FW_RFK_PATH];
5013 __le32 cur_18[NUM_OF_RTW89_FW_RFK_PATH];
5014 __le32 mlo_mode;
5015 } __packed;
5016
5017 struct rtw89_fw_h2c_rfk_pre_info_mcc_v1 {
5018 __le32 tbl_18[NUM_OF_RTW89_FW_RFK_TBL];
5019 __le32 cur_18[NUM_OF_RTW89_FW_RFK_PATH];
5020 __le32 mlo_mode;
5021 __le32 mlo_1_1;
5022 u8 phy_idx;
5023 u8 tbl_idx;
5024 } __packed;
5025
5026 struct rtw89_fw_h2c_rfk_pre_info_mcc {
5027 struct rtw89_fw_h2c_rfk_pre_info_mcc_v1 base;
5028 u8 rsvd[2];
5029 __le32 aid;
5030 u8 acv;
5031 u8 rsvd2[3];
5032 } __packed;
5033
5034 struct rtw89_h2c_rf_tssi {
5035 __le16 len;
5036 u8 phy;
5037 u8 ch;
5038 u8 bw;
5039 u8 band;
5040 u8 hwtx_en;
5041 u8 cv;
5042 s8 curr_tssi_cck_de[2];
5043 s8 curr_tssi_cck_de_20m[2];
5044 s8 curr_tssi_cck_de_40m[2];
5045 s8 curr_tssi_efuse_cck_de[2];
5046 s8 curr_tssi_ofdm_de[2];
5047 s8 curr_tssi_ofdm_de_20m[2];
5048 s8 curr_tssi_ofdm_de_40m[2];
5049 s8 curr_tssi_ofdm_de_80m[2];
5050 s8 curr_tssi_ofdm_de_160m[2];
5051 s8 curr_tssi_ofdm_de_320m[2];
5052 s8 curr_tssi_efuse_ofdm_de[2];
5053 s8 curr_tssi_ofdm_de_diff_20m[2];
5054 s8 curr_tssi_ofdm_de_diff_80m[2];
5055 s8 curr_tssi_ofdm_de_diff_160m[2];
5056 s8 curr_tssi_ofdm_de_diff_320m[2];
5057 s8 curr_tssi_trim_de[2];
5058 u8 pg_thermal[2];
5059 u8 ftable[2][128];
5060 u8 tssi_mode;
5061 u8 rfe_type;
5062 } __packed;
5063
5064 struct rtw89_h2c_rf_iqk_v0 {
5065 __le32 phy_idx;
5066 __le32 dbcc;
5067 } __packed;
5068
5069 struct rtw89_h2c_rf_iqk {
5070 u8 len;
5071 u8 ktype;
5072 u8 phy;
5073 u8 kpath;
5074 u8 band;
5075 u8 bw;
5076 u8 ch;
5077 u8 cv;
5078 } __packed;
5079
5080 struct rtw89_h2c_rf_dpk {
5081 u8 len;
5082 u8 phy;
5083 u8 dpk_enable;
5084 u8 kpath;
5085 u8 cur_band;
5086 u8 cur_bw;
5087 u8 cur_ch;
5088 u8 dpk_dbg_en;
5089 } __packed;
5090
5091 struct rtw89_h2c_rf_txgapk {
5092 u8 len;
5093 u8 ktype;
5094 u8 phy;
5095 u8 kpath;
5096 u8 band;
5097 u8 bw;
5098 u8 ch;
5099 u8 cv;
5100 } __packed;
5101
5102 struct rtw89_h2c_rf_dack {
5103 u8 len;
5104 u8 phy;
5105 u8 type;
5106 } __packed;
5107
5108 struct rtw89_h2c_rf_rxdck_v0 {
5109 u8 len;
5110 u8 phy;
5111 u8 is_afe;
5112 u8 kpath;
5113 u8 cur_band;
5114 u8 cur_bw;
5115 u8 cur_ch;
5116 u8 rxdck_dbg_en;
5117 } __packed;
5118
5119 struct rtw89_h2c_rf_tas {
5120 __le32 enable;
5121 } __packed;
5122
5123 struct rtw89_h2c_rf_rxdck {
5124 struct rtw89_h2c_rf_rxdck_v0 v0;
5125 u8 is_chl_k;
5126 } __packed;
5127
5128 struct rtw89_h2c_rf_txiqk_v0 {
5129 u8 len;
5130 u8 phy;
5131 u8 txiqk_enable;
5132 u8 is_wb_txiqk;
5133 u8 kpath;
5134 u8 cur_band;
5135 u8 cur_bw;
5136 u8 cur_ch;
5137 u8 txiqk_dbg_en;
5138 } __packed;
5139
5140 struct rtw89_h2c_rf_txiqk {
5141 struct rtw89_h2c_rf_txiqk_v0 v0;
5142 u8 is_ther_rek;
5143 } __packed;
5144
5145 struct rtw89_h2c_rf_cim3k {
5146 u8 len;
5147 u8 phy;
5148 u8 su_cim3k_enable[2];
5149 u8 ru_cim3k_enable[2];
5150 u8 kpath;
5151 u8 cur_band;
5152 u8 cur_bw;
5153 u8 cur_ch;
5154 u8 cim3k_dbg_en;
5155 } __packed;
5156
5157 enum rtw89_rf_log_type {
5158 RTW89_RF_RUN_LOG = 0,
5159 RTW89_RF_RPT_LOG = 1,
5160 };
5161
5162 struct rtw89_c2h_rf_log_hdr {
5163 u8 type; /* enum rtw89_rf_log_type */
5164 __le16 len;
5165 u8 content[];
5166 } __packed;
5167
5168 struct rtw89_c2h_rf_run_log {
5169 __le32 fmt_idx;
5170 __le32 arg[4];
5171 } __packed;
5172
5173 struct rtw89_c2h_rf_iqk_rpt_log {
5174 bool iqk_tx_fail[2];
5175 bool iqk_rx_fail[2];
5176 bool is_iqk_init;
5177 bool is_reload;
5178 bool is_wb_txiqk[2];
5179 bool is_wb_rxiqk[2];
5180 bool is_nbiqk;
5181 bool txiqk_en;
5182 bool rxiqk_en;
5183 bool lok_en;
5184 bool iqk_xym_en;
5185 bool iqk_sram_en;
5186 bool iqk_fft_en;
5187 bool is_fw_iqk;
5188 bool is_iqk_enable;
5189 bool iqk_cfir_en;
5190 bool thermal_rek_en;
5191 u8 iqk_band[2];
5192 u8 iqk_ch[2];
5193 u8 iqk_bw[2];
5194 u8 iqk_times;
5195 u8 version;
5196 u8 phy;
5197 u8 fwk_status;
5198 u8 rsvd;
5199 __le32 reload_cnt;
5200 __le32 iqk_fail_cnt;
5201 __le32 rf_0x18[2];
5202 __le32 lok_idac[2];
5203 __le32 lok_vbuf[2];
5204 __le32 rftxgain[2][6];
5205 __le32 rfrxgain[2][6];
5206 __le32 tx_xym[2][6];
5207 __le32 rx_xym[2][6];
5208 __le32 rx_wb_xym[2][32];
5209 bool is_radar;
5210 u8 rsvd1[3];
5211 } __packed;
5212
5213 struct rtw89_c2h_rf_dpk_rpt_log {
5214 u8 ver;
5215 u8 idx[2];
5216 u8 band[2];
5217 u8 bw[2];
5218 u8 ch[2];
5219 u8 path_ok[2];
5220 u8 txagc[2];
5221 u8 ther[2];
5222 u8 gs[2];
5223 u8 dc_i[4];
5224 u8 dc_q[4];
5225 u8 corr_val[2];
5226 u8 corr_idx[2];
5227 u8 is_timeout[2];
5228 u8 rxbb_ov[2];
5229 u8 rsvd;
5230 } __packed;
5231
5232 struct rtw89_c2h_rf_dack_rpt_log {
5233 u8 fwdack_ver;
5234 u8 fwdack_info_ver;
5235 u8 msbk_d[2][2][16];
5236 u8 dadck_d[2][2];
5237 u8 cdack_d[2][2][2];
5238 u8 addck2_hd[2][2][2];
5239 u8 addck2_ld[2][2][2];
5240 u8 adgaink_d[2][2];
5241 u8 biask_hd[2][2];
5242 u8 biask_ld[2][2];
5243 u8 addck_timeout;
5244 u8 cdack_timeout;
5245 u8 dadck_timeout;
5246 u8 msbk_timeout;
5247 u8 adgaink_timeout;
5248 u8 wbadcdck_timeout;
5249 u8 drck_timeout;
5250 u8 dack_fail;
5251 u8 wbdck_d[2];
5252 u8 rck_d;
5253 u8 adgaink_ex_d;
5254 } __packed;
5255
5256 struct rtw89_c2h_rf_rxdck_rpt_log {
5257 u8 ver;
5258 u8 band[2];
5259 u8 bw[2];
5260 u8 ch[2];
5261 u8 timeout[2];
5262 } __packed;
5263
5264 struct rtw89_c2h_rf_tssi_rpt_log {
5265 s8 alignment_power[2][2][4];
5266 u8 alignment_power_cw_h[2][2][4];
5267 u8 alignment_power_cw_l[2][2][4];
5268 u8 tssi_alimk_state[2][2];
5269 u8 default_txagc_offset[2][2];
5270 } __packed;
5271
5272 struct rtw89_c2h_rf_txgapk_rpt_log {
5273 __le32 r0x8010[2];
5274 __le32 chk_cnt;
5275 u8 track_d[2][17];
5276 u8 power_d[2][17];
5277 u8 is_txgapk_ok;
5278 u8 chk_id;
5279 u8 ver;
5280 u8 d_bnd_ok;
5281 __le32 stage[2];
5282 __le16 failcode[2];
5283 u8 rsvd[4];
5284 } __packed;
5285
5286 struct rtw89_c2h_rf_txiqk_rpt_log {
5287 u8 fw_txiqk_ver;
5288 u8 iqk_band[2];
5289 u8 iqk_ch[2];
5290 u8 iqk_bw[2];
5291 bool tx_iqk_fail[2];
5292 bool is_iqk_init;
5293 bool txiqk_en;
5294 bool lok_en;
5295 bool lok_fail[2];
5296 u8 rsvd[2];
5297 __le32 iqk_times;
5298 bool txiqk_nctldone[2];
5299 u8 rsvd2[2];
5300 __le32 txgain[2][6];
5301 __le32 tx_iqc[2][6];
5302 __le32 tx_xym[2][6][14];
5303 __le32 kidx[2];
5304 } __packed;
5305
5306 struct rtw89_c2h_rf_cim3k_rpt_log {
5307 u8 cim3k_band[2];
5308 u8 cim3k_ch[2];
5309 u8 cim3k_bw[2];
5310 u8 su_path_ok[2];
5311 u8 ru_path_ok[2];
5312 u8 txagc_cim3k[2];
5313 u8 ther_cim3k[2];
5314 u8 cim3k_gs[2];
5315 __le16 cim3k_pwsf[2];
5316 bool cim3k_nctldone[2];
5317 u8 rsvd[2];
5318 __le32 cim3k_rxiqc[2];
5319 __le32 cim3k_su_coef[2][3];
5320 __le16 dc_i[2];
5321 __le16 dc_q[2];
5322 u8 corr_val[2];
5323 u8 corr_idx[2];
5324 u8 rxbb_ov[2];
5325 u8 cim3k_txiqc[2];
5326 u8 kidx[2];
5327 u8 fw_cim3k_ver;
5328 bool su_cim3k_en[2];
5329 bool ru_cim3k_en[2];
5330 u8 rsvd1;
5331 } __packed;
5332
5333 struct rtw89_c2h_rfk_report {
5334 struct rtw89_c2h_hdr hdr;
5335 u8 state; /* enum rtw89_rfk_report_state */
5336 u8 version;
5337 } __packed;
5338
5339 struct rtw89_c2h_rf_tas_rpt_log {
5340 __le32 cur_idx;
5341 __le16 txpwr_history[20];
5342 } __packed;
5343
5344 struct rtw89_c2h_rf_tas_info {
5345 struct rtw89_c2h_hdr hdr;
5346 struct rtw89_c2h_rf_tas_rpt_log content;
5347 } __packed;
5348
5349 #define RTW89_FW_RSVD_PLE_SIZE 0x800
5350
5351 #define RTW89_FW_BACKTRACE_INFO_SIZE 8
5352 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \
5353 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0)
5354
5355 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */
5356 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE
5357
5358 #define FWDL_WAIT_CNT 400000
5359 #define FWDL_WAIT_CNT_USB 3200
5360
5361 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);
5362 int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
5363 int rtw89_fw_recognize_elements(struct rtw89_dev *rtwdev);
5364 const struct firmware *
5365 rtw89_early_fw_feature_recognize(struct device *device,
5366 const struct rtw89_chip_info *chip,
5367 const struct rtw89_chip_variant *variant,
5368 struct rtw89_fw_info *early_fw,
5369 int *used_fw_format);
5370 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
5371 bool include_bb);
5372 void rtw89_load_firmware_work(struct work_struct *work);
5373 void rtw89_unload_firmware(struct rtw89_dev *rtwdev);
5374 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev);
5375 int rtw89_fw_log_prepare(struct rtw89_dev *rtwdev);
5376 void rtw89_fw_log_dump(struct rtw89_dev *rtwdev, u8 *buf, u32 len);
5377 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb,
5378 u8 type, u8 cat, u8 class, u8 func,
5379 bool rack, bool dack, u32 len);
5380 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
5381 struct rtw89_vif_link *rtwvif_link,
5382 struct rtw89_sta_link *rtwsta_link);
5383 int rtw89_fw_h2c_default_cmac_tbl_g7(struct rtw89_dev *rtwdev,
5384 struct rtw89_vif_link *rtwvif_link,
5385 struct rtw89_sta_link *rtwsta_link);
5386 int rtw89_fw_h2c_default_cmac_tbl_be(struct rtw89_dev *rtwdev,
5387 struct rtw89_vif_link *rtwvif_link,
5388 struct rtw89_sta_link *rtwsta_link);
5389 int rtw89_fw_h2c_default_dmac_tbl_v2(struct rtw89_dev *rtwdev,
5390 struct rtw89_vif_link *rtwvif_link,
5391 struct rtw89_sta_link *rtwsta_link);
5392 int rtw89_fw_h2c_default_dmac_tbl_v3(struct rtw89_dev *rtwdev,
5393 struct rtw89_vif_link *rtwvif_link,
5394 struct rtw89_sta_link *rtwsta_link);
5395 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
5396 struct rtw89_vif_link *rtwvif_link,
5397 struct rtw89_sta_link *rtwsta_link);
5398 int rtw89_fw_h2c_assoc_cmac_tbl_g7(struct rtw89_dev *rtwdev,
5399 struct rtw89_vif_link *rtwvif_link,
5400 struct rtw89_sta_link *rtwsta_link);
5401 int rtw89_fw_h2c_assoc_cmac_tbl_be(struct rtw89_dev *rtwdev,
5402 struct rtw89_vif_link *rtwvif_link,
5403 struct rtw89_sta_link *rtwsta_link);
5404 int rtw89_fw_h2c_ampdu_cmac_tbl_g7(struct rtw89_dev *rtwdev,
5405 struct rtw89_vif_link *rtwvif_link,
5406 struct rtw89_sta_link *rtwsta_link);
5407 int rtw89_fw_h2c_ampdu_cmac_tbl_be(struct rtw89_dev *rtwdev,
5408 struct rtw89_vif_link *rtwvif_link,
5409 struct rtw89_sta_link *rtwsta_link);
5410 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
5411 struct rtw89_sta_link *rtwsta_link);
5412 int rtw89_fw_h2c_txtime_cmac_tbl_g7(struct rtw89_dev *rtwdev,
5413 struct rtw89_sta_link *rtwsta_link);
5414 int rtw89_fw_h2c_txtime_cmac_tbl_be(struct rtw89_dev *rtwdev,
5415 struct rtw89_sta_link *rtwsta_link);
5416 int rtw89_fw_h2c_punctured_cmac_tbl_g7(struct rtw89_dev *rtwdev,
5417 struct rtw89_vif_link *rtwvif_link,
5418 u16 punctured);
5419 int rtw89_fw_h2c_punctured_cmac_tbl_be(struct rtw89_dev *rtwdev,
5420 struct rtw89_vif_link *rtwvif_link,
5421 u16 punctured);
5422 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev,
5423 struct rtw89_sta_link *rtwsta_link);
5424 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev,
5425 struct rtw89_vif_link *rtwvif_link);
5426 int rtw89_fw_h2c_update_beacon_be(struct rtw89_dev *rtwdev,
5427 struct rtw89_vif_link *rtwvif_link);
5428 int rtw89_fw_h2c_tbtt_tuning(struct rtw89_dev *rtwdev,
5429 struct rtw89_vif_link *rtwvif_link, u32 offset);
5430 int rtw89_fw_h2c_pwr_lvl(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
5431 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif,
5432 struct rtw89_sta_link *rtwsta_link, const u8 *scan_mac_addr,
5433 enum rtw89_upd_mode upd_mode);
5434 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev,
5435 struct rtw89_vif_link *rtwvif_link,
5436 struct rtw89_sta_link *rtwsta_link);
5437 int rtw89_fw_h2c_dctl_sec_cam_v2(struct rtw89_dev *rtwdev,
5438 struct rtw89_vif_link *rtwvif_link,
5439 struct rtw89_sta_link *rtwsta_link);
5440 int rtw89_fw_h2c_dctl_sec_cam_v3(struct rtw89_dev *rtwdev,
5441 struct rtw89_vif_link *rtwvif_link,
5442 struct rtw89_sta_link *rtwsta_link);
5443 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h);
5444 void rtw89_fw_c2h_work(struct wiphy *wiphy, struct wiphy_work *work);
5445 void rtw89_fw_c2h_purge_obsoleted_scan_events(struct rtw89_dev *rtwdev);
5446 void rtw89_fw_c2h_dummy_handler(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len);
5447 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev,
5448 struct rtw89_vif_link *rtwvif_link,
5449 struct rtw89_sta_link *rtwsta_link,
5450 enum rtw89_upd_mode upd_mode);
5451 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5452 struct rtw89_sta_link *rtwsta_link, bool dis_conn);
5453 int rtw89_fw_h2c_notify_dbcc(struct rtw89_dev *rtwdev, bool en);
5454 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp,
5455 bool pause);
5456 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5457 u8 ac, u32 val);
5458 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev);
5459 int rtw89_fw_h2c_tx_duty(struct rtw89_dev *rtwdev, u8 lv);
5460 int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev,
5461 struct rtw89_vif_link *rtwvif_link,
5462 bool connect);
5463 int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev,
5464 struct rtw89_rx_phy_ppdu *phy_ppdu);
5465 int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
5466 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi);
5467 int rtw89_fw_h2c_phy_ch_rpt(struct rtw89_dev *rtwdev);
5468 int rtw89_fw_h2c_tx_history(struct rtw89_dev *rtwdev, u16 mac_id);
5469 int rtw89_fw_h2c_drv_ctrl_fw(struct rtw89_dev *rtwdev);
5470 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev, u8 type);
5471 int rtw89_fw_h2c_cxdrv_init_v7(struct rtw89_dev *rtwdev, u8 type);
5472 int rtw89_fw_h2c_cxdrv_init_v10(struct rtw89_dev *rtwdev, u8 type);
5473 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev, u8 type);
5474 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev, u8 type);
5475 int rtw89_fw_h2c_cxdrv_role_v101(struct rtw89_dev *rtwdev, u8 type);
5476 int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev, u8 type);
5477 int rtw89_fw_h2c_cxdrv_role_v7(struct rtw89_dev *rtwdev, u8 type);
5478 int rtw89_fw_h2c_cxdrv_role_v8(struct rtw89_dev *rtwdev, u8 type);
5479 int rtw89_fw_h2c_cxdrv_role_v10(struct rtw89_dev *rtwdev, u8 type);
5480 int rtw89_fw_h2c_cxdrv_init_v11(struct rtw89_dev *rtwdev, u8 type);
5481 int rtw89_fw_h2c_cxdrv_mlo_v2(struct rtw89_dev *rtwdev, u8 type);
5482 int rtw89_fw_h2c_cxdrv_osi_info(struct rtw89_dev *rtwdev, u8 type);
5483 int rtw89_fw_h2c_cxdrv_osi_info_v6(struct rtw89_dev *rtwdev, u8 type);
5484 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev, u8 type);
5485 int rtw89_fw_h2c_cxdrv_ctrl_v7(struct rtw89_dev *rtwdev, u8 type);
5486 int rtw89_fw_h2c_cxdrv_ctrl_v9(struct rtw89_dev *rtwdev, u8 type);
5487 int rtw89_fw_h2c_cxdrv_trx_v7(struct rtw89_dev *rtwdev, u8 type);
5488 int rtw89_fw_h2c_cxdrv_trx_v9(struct rtw89_dev *rtwdev, u8 type);
5489 int rtw89_fw_h2c_cxdrv_trx_v107(struct rtw89_dev *rtwdev, u8 type);
5490 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev, u8 type);
5491 int rtw89_fw_h2c_cxtxpwr_v7(struct rtw89_dev *rtwdev, u8 type);
5492 int rtw89_fw_h2c_cxtxpwr_v9(struct rtw89_dev *rtwdev, u8 type);
5493 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id);
5494 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
5495 struct sk_buff *skb_ofld);
5496 int rtw89_fw_h2c_scan_offload_ax(struct rtw89_dev *rtwdev,
5497 struct rtw89_scan_option *opt,
5498 struct rtw89_vif_link *vif,
5499 bool wowlan);
5500 int rtw89_fw_h2c_scan_offload_be(struct rtw89_dev *rtwdev,
5501 struct rtw89_scan_option *opt,
5502 struct rtw89_vif_link *vif,
5503 bool wowlan);
5504 int rtw89_fw_h2c_trx_protect(struct rtw89_dev *rtwdev,
5505 enum rtw89_phy_idx phy_idx, bool enable);
5506 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
5507 struct rtw89_fw_h2c_rf_reg_info *info,
5508 u16 len, u8 page);
5509 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev);
5510 int rtw89_fw_h2c_rf_ps_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
5511 int rtw89_fw_h2c_rf_pre_ntfy(struct rtw89_dev *rtwdev,
5512 enum rtw89_phy_idx phy_idx);
5513 int rtw89_fw_h2c_rf_pre_ntfy_mcc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
5514 int rtw89_fw_h2c_mcc_dig(struct rtw89_dev *rtwdev,
5515 enum rtw89_chanctx_idx chanctx_idx,
5516 u8 mcc_role_idx, u8 pd_val, bool en);
5517 int rtw89_fw_h2c_rf_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
5518 const struct rtw89_chan *chan, enum rtw89_tssi_mode tssi_mode);
5519 int rtw89_fw_h2c_rf_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
5520 const struct rtw89_chan *chan);
5521 int rtw89_fw_h2c_rf_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
5522 const struct rtw89_chan *chan);
5523 int rtw89_fw_h2c_rf_txgapk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
5524 const struct rtw89_chan *chan);
5525 int rtw89_fw_h2c_rf_dack(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
5526 const struct rtw89_chan *chan);
5527 int rtw89_fw_h2c_rf_rxdck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
5528 const struct rtw89_chan *chan, bool is_chl_k);
5529 int rtw89_fw_h2c_rf_tas_trigger(struct rtw89_dev *rtwdev, bool enable);
5530 int rtw89_fw_h2c_rf_txiqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
5531 const struct rtw89_chan *chan);
5532 int rtw89_fw_h2c_rf_cim3k(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
5533 const struct rtw89_chan *chan);
5534 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
5535 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
5536 bool rack, bool dack);
5537 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len);
5538 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev);
5539 void __rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
5540 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
5541 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5542 u8 macid);
5543 void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev,
5544 struct rtw89_vif_link *rtwvif_link,
5545 bool notify_fw);
5546 void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw);
5547 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev,
5548 struct rtw89_vif_link *rtwvif_link,
5549 struct rtw89_sta_link *rtwsta_link,
5550 bool valid, struct ieee80211_ampdu_params *params);
5551 int rtw89_fw_h2c_ba_cam_v1(struct rtw89_dev *rtwdev,
5552 struct rtw89_vif_link *rtwvif_link,
5553 struct rtw89_sta_link *rtwsta_link,
5554 bool valid, struct ieee80211_ampdu_params *params);
5555 void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev);
5556 int rtw89_fw_h2c_init_ba_cam_users(struct rtw89_dev *rtwdev, u8 users,
5557 u8 offset, u8 mac_idx);
5558
5559 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,
5560 struct rtw89_lps_parm *lps_param);
5561 int rtw89_fw_h2c_lps_ch_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
5562 int rtw89_fw_h2c_lps_ml_cmn_info(struct rtw89_dev *rtwdev,
5563 struct rtw89_vif *rtwvif);
5564 void rtw89_bb_lps_cmn_info_rx_gain_fill(struct rtw89_dev *rtwdev,
5565 struct rtw89_bb_link_info_rx_gain *h2c_gain,
5566 const struct rtw89_chan *chan, u8 phy_idx);
5567 int rtw89_fw_h2c_lps_ml_cmn_info_v1(struct rtw89_dev *rtwdev,
5568 struct rtw89_vif *rtwvif);
5569 int rtw89_fw_h2c_fwips(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5570 bool enable);
5571 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len);
5572 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len);
5573 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev,
5574 struct rtw89_mac_h2c_info *h2c_info,
5575 struct rtw89_mac_c2h_info *c2h_info);
5576 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable);
5577 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev);
5578 int rtw89_hw_scan_start(struct rtw89_dev *rtwdev,
5579 struct rtw89_vif_link *rtwvif_link,
5580 struct ieee80211_scan_request *scan_req);
5581 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev,
5582 struct rtw89_vif_link *rtwvif_link,
5583 bool aborted);
5584 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev,
5585 struct rtw89_vif_link *rtwvif_link,
5586 bool enable);
5587 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev,
5588 struct rtw89_vif_link *rtwvif_link);
5589 int rtw89_hw_scan_prep_chan_list_ax(struct rtw89_dev *rtwdev,
5590 struct rtw89_vif_link *rtwvif_link);
5591 void rtw89_hw_scan_free_chan_list_ax(struct rtw89_dev *rtwdev);
5592 int rtw89_hw_scan_add_chan_list_ax(struct rtw89_dev *rtwdev,
5593 struct rtw89_vif_link *rtwvif_link);
5594 int rtw89_pno_scan_add_chan_list_ax(struct rtw89_dev *rtwdev,
5595 struct rtw89_vif_link *rtwvif_link);
5596 int rtw89_hw_scan_prep_chan_list_be(struct rtw89_dev *rtwdev,
5597 struct rtw89_vif_link *rtwvif_link);
5598 void rtw89_hw_scan_free_chan_list_be(struct rtw89_dev *rtwdev);
5599 int rtw89_hw_scan_add_chan_list_be(struct rtw89_dev *rtwdev,
5600 struct rtw89_vif_link *rtwvif_link);
5601 int rtw89_pno_scan_add_chan_list_be(struct rtw89_dev *rtwdev,
5602 struct rtw89_vif_link *rtwvif_link);
5603 int rtw89_hw_scan_append_wildcard_probe_req(struct rtw89_dev *rtwdev,
5604 struct rtw89_vif_link *rtwvif_link,
5605 const u8 *mac_addr, bool wowlan);
5606 void rtw89_hw_scan_calc_req_ssid(struct rtw89_dev *rtwdev,
5607 struct rtw89_vif_link *rtwvif_link, bool wowlan);
5608 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev);
5609 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev,
5610 const struct rtw89_pkt_drop_params *params);
5611 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev,
5612 struct rtw89_vif_link *rtwvif_link,
5613 struct ieee80211_p2p_noa_desc *desc,
5614 u8 act, u8 noa_id, u8 ctwindow_oppps);
5615 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev,
5616 struct rtw89_vif_link *rtwvif_link,
5617 bool en);
5618 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5619 bool enable);
5620 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
5621 struct rtw89_vif_link *rtwvif_link, bool enable);
5622 int rtw89_fw_h2c_cfg_pno(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5623 bool enable);
5624 int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5625 bool enable);
5626 int rtw89_fw_h2c_arp_offload(struct rtw89_dev *rtwdev,
5627 struct rtw89_vif_link *rtwvif_link, bool enable);
5628 int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
5629 struct rtw89_vif_link *rtwvif_link, bool enable);
5630 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5631 bool enable);
5632 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
5633 struct rtw89_vif_link *rtwvif_link, bool enable);
5634 int rtw89_fw_h2c_wow_cam_update(struct rtw89_dev *rtwdev,
5635 struct rtw89_wow_cam_info *cam_info);
5636 int rtw89_fw_h2c_wow_cam_update_v1(struct rtw89_dev *rtwdev,
5637 struct rtw89_wow_cam_info *cam_info);
5638 int rtw89_fw_h2c_wow_gtk_ofld(struct rtw89_dev *rtwdev,
5639 struct rtw89_vif_link *rtwvif_link,
5640 bool enable);
5641 int rtw89_fw_h2c_wow_request_aoac(struct rtw89_dev *rtwdev);
5642 int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
5643 const struct rtw89_fw_mcc_add_req *p);
5644 int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
5645 const struct rtw89_fw_mcc_start_req *p);
5646 int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
5647 bool prev_groups);
5648 int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
5649 bool prev_groups);
5650 int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group);
5651 int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
5652 const struct rtw89_fw_mcc_tsf_req *req,
5653 struct rtw89_mac_mcc_tsf_rpt *rpt);
5654 int rtw89_fw_h2c_mcc_macid_bitmap(struct rtw89_dev *rtwdev, u8 group, u8 macid,
5655 u8 *bitmap);
5656 int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
5657 u8 target, u8 offset);
5658 int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
5659 const struct rtw89_fw_mcc_duration *p);
5660 int rtw89_fw_h2c_mrc_add(struct rtw89_dev *rtwdev,
5661 const struct rtw89_fw_mrc_add_arg *arg);
5662 int rtw89_fw_h2c_mrc_start(struct rtw89_dev *rtwdev,
5663 const struct rtw89_fw_mrc_start_arg *arg);
5664 int rtw89_fw_h2c_mrc_del(struct rtw89_dev *rtwdev, u8 sch_idx, u8 slot_idx);
5665 int rtw89_fw_h2c_mrc_req_tsf(struct rtw89_dev *rtwdev,
5666 const struct rtw89_fw_mrc_req_tsf_arg *arg,
5667 struct rtw89_mac_mrc_tsf_rpt *rpt);
5668 int rtw89_fw_h2c_mrc_upd_bitmap(struct rtw89_dev *rtwdev,
5669 const struct rtw89_fw_mrc_upd_bitmap_arg *arg);
5670 int rtw89_fw_h2c_mrc_sync(struct rtw89_dev *rtwdev,
5671 const struct rtw89_fw_mrc_sync_arg *arg);
5672 int rtw89_fw_h2c_mrc_upd_duration(struct rtw89_dev *rtwdev,
5673 const struct rtw89_fw_mrc_upd_duration_arg *arg);
5674 int rtw89_fw_h2c_ap_info_refcount(struct rtw89_dev *rtwdev, bool en);
5675 int rtw89_fw_h2c_mlo_link_cfg(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5676 bool enable);
5677
rtw89_fw_h2c_init_ba_cam(struct rtw89_dev * rtwdev)5678 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
5679 {
5680 const struct rtw89_chip_info *chip = rtwdev->chip;
5681
5682 if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
5683 rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev);
5684 }
5685
rtw89_fw_h2c_init_trx_protect(struct rtw89_dev * rtwdev)5686 static inline void rtw89_fw_h2c_init_trx_protect(struct rtw89_dev *rtwdev)
5687 {
5688 u8 active_bands = rtw89_get_active_phy_bitmap(rtwdev);
5689 int i;
5690
5691 for (i = 0; i < RTW89_PHY_NUM; i++)
5692 rtw89_fw_h2c_trx_protect(rtwdev, i, active_bands & BIT(i));
5693 }
5694
rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5695 static inline int rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
5696 struct rtw89_vif_link *rtwvif_link,
5697 struct rtw89_sta_link *rtwsta_link)
5698 {
5699 const struct rtw89_chip_info *chip = rtwdev->chip;
5700
5701 return chip->ops->h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
5702 }
5703
rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5704 static inline int rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev *rtwdev,
5705 struct rtw89_vif_link *rtwvif_link,
5706 struct rtw89_sta_link *rtwsta_link)
5707 {
5708 const struct rtw89_chip_info *chip = rtwdev->chip;
5709
5710 if (chip->ops->h2c_default_dmac_tbl)
5711 return chip->ops->h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
5712
5713 return 0;
5714 }
5715
rtw89_chip_h2c_update_beacon(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)5716 static inline int rtw89_chip_h2c_update_beacon(struct rtw89_dev *rtwdev,
5717 struct rtw89_vif_link *rtwvif_link)
5718 {
5719 const struct rtw89_chip_info *chip = rtwdev->chip;
5720
5721 return chip->ops->h2c_update_beacon(rtwdev, rtwvif_link);
5722 }
5723
rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5724 static inline int rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
5725 struct rtw89_vif_link *rtwvif_link,
5726 struct rtw89_sta_link *rtwsta_link)
5727 {
5728 const struct rtw89_chip_info *chip = rtwdev->chip;
5729
5730 return chip->ops->h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
5731 }
5732
5733 static inline
rtw89_chip_h2c_ampdu_link_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5734 int rtw89_chip_h2c_ampdu_link_cmac_tbl(struct rtw89_dev *rtwdev,
5735 struct rtw89_vif_link *rtwvif_link,
5736 struct rtw89_sta_link *rtwsta_link)
5737 {
5738 const struct rtw89_chip_info *chip = rtwdev->chip;
5739
5740 if (chip->ops->h2c_ampdu_cmac_tbl)
5741 return chip->ops->h2c_ampdu_cmac_tbl(rtwdev, rtwvif_link,
5742 rtwsta_link);
5743
5744 return 0;
5745 }
5746
rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)5747 static inline int rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev *rtwdev,
5748 struct rtw89_vif *rtwvif,
5749 struct rtw89_sta *rtwsta)
5750 {
5751 struct rtw89_vif_link *rtwvif_link;
5752 struct rtw89_sta_link *rtwsta_link;
5753 unsigned int link_id;
5754 int ret;
5755
5756 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
5757 rtwvif_link = rtwsta_link->rtwvif_link;
5758 ret = rtw89_chip_h2c_ampdu_link_cmac_tbl(rtwdev, rtwvif_link,
5759 rtwsta_link);
5760 if (ret)
5761 return ret;
5762 }
5763
5764 return 0;
5765 }
5766
5767 static inline
rtw89_chip_h2c_txtime_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link)5768 int rtw89_chip_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
5769 struct rtw89_sta_link *rtwsta_link)
5770 {
5771 const struct rtw89_chip_info *chip = rtwdev->chip;
5772
5773 return chip->ops->h2c_txtime_cmac_tbl(rtwdev, rtwsta_link);
5774 }
5775
5776 static inline
rtw89_chip_h2c_punctured_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u16 punctured)5777 int rtw89_chip_h2c_punctured_cmac_tbl(struct rtw89_dev *rtwdev,
5778 struct rtw89_vif_link *rtwvif_link,
5779 u16 punctured)
5780 {
5781 const struct rtw89_chip_info *chip = rtwdev->chip;
5782
5783 if (!chip->ops->h2c_punctured_cmac_tbl)
5784 return 0;
5785
5786 return chip->ops->h2c_punctured_cmac_tbl(rtwdev, rtwvif_link, punctured);
5787 }
5788
5789 static inline
rtw89_chip_h2c_ba_cam(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,bool valid,struct ieee80211_ampdu_params * params)5790 int rtw89_chip_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
5791 bool valid, struct ieee80211_ampdu_params *params)
5792 {
5793 const struct rtw89_chip_info *chip = rtwdev->chip;
5794 struct rtw89_vif_link *rtwvif_link;
5795 struct rtw89_sta_link *rtwsta_link;
5796 unsigned int link_id;
5797 int ret;
5798
5799 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
5800 rtwvif_link = rtwsta_link->rtwvif_link;
5801 ret = chip->ops->h2c_ba_cam(rtwdev, rtwvif_link, rtwsta_link,
5802 valid, params);
5803 if (ret)
5804 return ret;
5805 }
5806
5807 return 0;
5808 }
5809
5810 static inline
rtw89_chip_h2c_wow_cam_update(struct rtw89_dev * rtwdev,struct rtw89_wow_cam_info * cam_info)5811 int rtw89_chip_h2c_wow_cam_update(struct rtw89_dev *rtwdev,
5812 struct rtw89_wow_cam_info *cam_info)
5813 {
5814 const struct rtw89_chip_info *chip = rtwdev->chip;
5815
5816 return chip->ops->h2c_wow_cam_update(rtwdev, cam_info);
5817 }
5818
5819 /* Must consider compatibility; don't insert new in the mid.
5820 * Fill each field's default value in rtw89_regd_entcpy().
5821 */
5822 struct rtw89_fw_regd_entry {
5823 u8 alpha2_0;
5824 u8 alpha2_1;
5825 u8 rule_2ghz;
5826 u8 rule_5ghz;
5827 u8 rule_6ghz;
5828 __le32 fmap;
5829 } __packed;
5830
5831 /* must consider compatibility; don't insert new in the mid */
5832 struct rtw89_fw_txpwr_byrate_entry {
5833 u8 band;
5834 u8 nss;
5835 u8 rs;
5836 u8 shf;
5837 u8 len;
5838 __le32 data;
5839 u8 bw;
5840 u8 ofdma;
5841 } __packed;
5842
5843 /* must consider compatibility; don't insert new in the mid */
5844 struct rtw89_fw_txpwr_lmt_2ghz_entry {
5845 u8 bw;
5846 u8 nt;
5847 u8 rs;
5848 u8 bf;
5849 u8 regd;
5850 u8 ch_idx;
5851 s8 v;
5852 } __packed;
5853
5854 /* must consider compatibility; don't insert new in the mid */
5855 struct rtw89_fw_txpwr_lmt_5ghz_entry {
5856 u8 bw;
5857 u8 nt;
5858 u8 rs;
5859 u8 bf;
5860 u8 regd;
5861 u8 ch_idx;
5862 s8 v;
5863 } __packed;
5864
5865 /* must consider compatibility; don't insert new in the mid */
5866 struct rtw89_fw_txpwr_lmt_6ghz_entry {
5867 u8 bw;
5868 u8 nt;
5869 u8 rs;
5870 u8 bf;
5871 u8 regd;
5872 u8 reg_6ghz_power;
5873 u8 ch_idx;
5874 s8 v;
5875 } __packed;
5876
5877 /* must consider compatibility; don't insert new in the mid */
5878 struct rtw89_fw_txpwr_lmt_ru_2ghz_entry {
5879 u8 ru;
5880 u8 nt;
5881 u8 regd;
5882 u8 ch_idx;
5883 s8 v;
5884 } __packed;
5885
5886 /* must consider compatibility; don't insert new in the mid */
5887 struct rtw89_fw_txpwr_lmt_ru_5ghz_entry {
5888 u8 ru;
5889 u8 nt;
5890 u8 regd;
5891 u8 ch_idx;
5892 s8 v;
5893 } __packed;
5894
5895 /* must consider compatibility; don't insert new in the mid */
5896 struct rtw89_fw_txpwr_lmt_ru_6ghz_entry {
5897 u8 ru;
5898 u8 nt;
5899 u8 regd;
5900 u8 reg_6ghz_power;
5901 u8 ch_idx;
5902 s8 v;
5903 } __packed;
5904
5905 /* must consider compatibility; don't insert new in the mid */
5906 struct rtw89_fw_tx_shape_lmt_entry {
5907 u8 band;
5908 u8 tx_shape_rs;
5909 u8 regd;
5910 u8 v;
5911 u8 reg6_pwr;
5912 } __packed;
5913
5914 /* must consider compatibility; don't insert new in the mid */
5915 struct rtw89_fw_tx_shape_lmt_ru_entry {
5916 u8 band;
5917 u8 regd;
5918 u8 v;
5919 u8 reg6_pwr;
5920 } __packed;
5921
5922 const struct rtw89_rfe_parms *
5923 rtw89_load_rfe_data_from_fw(struct rtw89_dev *rtwdev,
5924 const struct rtw89_rfe_parms *init);
5925
5926 enum rtw89_wow_wakeup_ver {
5927 RTW89_WOW_REASON_V0,
5928 RTW89_WOW_REASON_V1,
5929 RTW89_WOW_REASON_NUM,
5930 };
5931
5932 const struct rtw89_io_ops *
5933 rtw89_fw_cmd_ofld_alloc_and_get_io_ops(struct rtw89_dev *rtwdev);
5934
5935 #endif
5936