1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2013-2017 Broadcom
3
4 #include <linux/err.h>
5 #include <linux/init.h>
6 #include <linux/io.h>
7 #include <linux/of.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10 #include <linux/seq_file.h>
11 #include <linux/slab.h>
12
13 #include <linux/pinctrl/pinconf-generic.h>
14 #include <linux/pinctrl/pinconf.h>
15 #include <linux/pinctrl/pinctrl.h>
16 #include <linux/pinctrl/pinmux.h>
17
18 #include "../core.h"
19 #include "../pinctrl-utils.h"
20
21 /* BCM281XX Pin Control Registers Definitions */
22
23 /* Function Select bits are the same for all pin control registers */
24 #define BCM281XX_PIN_REG_F_SEL_MASK 0x0700
25 #define BCM281XX_PIN_REG_F_SEL_SHIFT 8
26
27 /* Standard pin register */
28 #define BCM281XX_STD_PIN_REG_DRV_STR_MASK 0x0007
29 #define BCM281XX_STD_PIN_REG_DRV_STR_SHIFT 0
30 #define BCM281XX_STD_PIN_REG_INPUT_DIS_MASK 0x0008
31 #define BCM281XX_STD_PIN_REG_INPUT_DIS_SHIFT 3
32 #define BCM281XX_STD_PIN_REG_SLEW_MASK 0x0010
33 #define BCM281XX_STD_PIN_REG_SLEW_SHIFT 4
34 #define BCM281XX_STD_PIN_REG_PULL_UP_MASK 0x0020
35 #define BCM281XX_STD_PIN_REG_PULL_UP_SHIFT 5
36 #define BCM281XX_STD_PIN_REG_PULL_DN_MASK 0x0040
37 #define BCM281XX_STD_PIN_REG_PULL_DN_SHIFT 6
38 #define BCM281XX_STD_PIN_REG_HYST_MASK 0x0080
39 #define BCM281XX_STD_PIN_REG_HYST_SHIFT 7
40
41 /* I2C pin register */
42 #define BCM281XX_I2C_PIN_REG_INPUT_DIS_MASK 0x0004
43 #define BCM281XX_I2C_PIN_REG_INPUT_DIS_SHIFT 2
44 #define BCM281XX_I2C_PIN_REG_SLEW_MASK 0x0008
45 #define BCM281XX_I2C_PIN_REG_SLEW_SHIFT 3
46 #define BCM281XX_I2C_PIN_REG_PULL_UP_STR_MASK 0x0070
47 #define BCM281XX_I2C_PIN_REG_PULL_UP_STR_SHIFT 4
48
49 /* HDMI pin register */
50 #define BCM281XX_HDMI_PIN_REG_INPUT_DIS_MASK 0x0008
51 #define BCM281XX_HDMI_PIN_REG_INPUT_DIS_SHIFT 3
52 #define BCM281XX_HDMI_PIN_REG_MODE_MASK 0x0010
53 #define BCM281XX_HDMI_PIN_REG_MODE_SHIFT 4
54
55 /* BCM21664 access lock registers */
56 #define BCM21664_WR_ACCESS_OFFSET 0x07F0
57 #define BCM21664_WR_ACCESS_PASSWORD 0xA5A501
58 #define BCM21664_ACCESS_LOCK_OFFSET(lock) (0x0780 + (lock * 4))
59 #define BCM21664_ACCESS_LOCK_COUNT 5
60
61 /*
62 * bcm281xx_pin_type - types of pin register
63 */
64 enum bcm281xx_pin_type {
65 BCM281XX_PIN_TYPE_UNKNOWN = 0,
66 BCM281XX_PIN_TYPE_STD,
67 BCM281XX_PIN_TYPE_I2C,
68 BCM281XX_PIN_TYPE_HDMI,
69 };
70
71 static enum bcm281xx_pin_type std_pin = BCM281XX_PIN_TYPE_STD;
72 static enum bcm281xx_pin_type i2c_pin = BCM281XX_PIN_TYPE_I2C;
73 static enum bcm281xx_pin_type hdmi_pin = BCM281XX_PIN_TYPE_HDMI;
74
75 /*
76 * bcm281xx_pin_function- define pin function
77 */
78 struct bcm281xx_pin_function {
79 const char *name;
80 const char * const *groups;
81 const unsigned int ngroups;
82 };
83
84 /*
85 * Device types (used in bcm281xx_pinctrl_desc to differentiate
86 * the two device types from each other)
87 */
88 enum bcm281xx_pinctrl_type {
89 BCM281XX_PINCTRL_TYPE,
90 BCM21664_PINCTRL_TYPE,
91 };
92
93 /*
94 * bcm281xx_pinctrl_info - description of a pinctrl device supported
95 * by this driver, intended to be used as a provider of OF match data.
96 */
97 struct bcm281xx_pinctrl_info {
98 enum bcm281xx_pinctrl_type device_type;
99
100 /* List of all pins */
101 const struct pinctrl_pin_desc *pins;
102 unsigned int npins;
103
104 const struct bcm281xx_pin_function *functions;
105 unsigned int nfunctions;
106
107 const struct regmap_config *regmap_config;
108 };
109
110 /*
111 * bcm281xx_pinctrl_data - Broadcom-specific pinctrl data
112 * @reg_base - base of pinctrl registers
113 */
114 struct bcm281xx_pinctrl_data {
115 struct device *dev;
116 void __iomem *reg_base;
117
118 struct regmap *regmap;
119 const struct bcm281xx_pinctrl_info *info;
120 };
121
122 /*
123 * Pin number definition. The order here must be the same as defined in the
124 * PADCTRLREG block in the RDB.
125 */
126 #define BCM281XX_PIN_ADCSYNC 0
127 #define BCM281XX_PIN_BAT_RM 1
128 #define BCM281XX_PIN_BSC1_SCL 2
129 #define BCM281XX_PIN_BSC1_SDA 3
130 #define BCM281XX_PIN_BSC2_SCL 4
131 #define BCM281XX_PIN_BSC2_SDA 5
132 #define BCM281XX_PIN_CLASSGPWR 6
133 #define BCM281XX_PIN_CLK_CX8 7
134 #define BCM281XX_PIN_CLKOUT_0 8
135 #define BCM281XX_PIN_CLKOUT_1 9
136 #define BCM281XX_PIN_CLKOUT_2 10
137 #define BCM281XX_PIN_CLKOUT_3 11
138 #define BCM281XX_PIN_CLKREQ_IN_0 12
139 #define BCM281XX_PIN_CLKREQ_IN_1 13
140 #define BCM281XX_PIN_CWS_SYS_REQ1 14
141 #define BCM281XX_PIN_CWS_SYS_REQ2 15
142 #define BCM281XX_PIN_CWS_SYS_REQ3 16
143 #define BCM281XX_PIN_DIGMIC1_CLK 17
144 #define BCM281XX_PIN_DIGMIC1_DQ 18
145 #define BCM281XX_PIN_DIGMIC2_CLK 19
146 #define BCM281XX_PIN_DIGMIC2_DQ 20
147 #define BCM281XX_PIN_GPEN13 21
148 #define BCM281XX_PIN_GPEN14 22
149 #define BCM281XX_PIN_GPEN15 23
150 #define BCM281XX_PIN_GPIO00 24
151 #define BCM281XX_PIN_GPIO01 25
152 #define BCM281XX_PIN_GPIO02 26
153 #define BCM281XX_PIN_GPIO03 27
154 #define BCM281XX_PIN_GPIO04 28
155 #define BCM281XX_PIN_GPIO05 29
156 #define BCM281XX_PIN_GPIO06 30
157 #define BCM281XX_PIN_GPIO07 31
158 #define BCM281XX_PIN_GPIO08 32
159 #define BCM281XX_PIN_GPIO09 33
160 #define BCM281XX_PIN_GPIO10 34
161 #define BCM281XX_PIN_GPIO11 35
162 #define BCM281XX_PIN_GPIO12 36
163 #define BCM281XX_PIN_GPIO13 37
164 #define BCM281XX_PIN_GPIO14 38
165 #define BCM281XX_PIN_GPS_PABLANK 39
166 #define BCM281XX_PIN_GPS_TMARK 40
167 #define BCM281XX_PIN_HDMI_SCL 41
168 #define BCM281XX_PIN_HDMI_SDA 42
169 #define BCM281XX_PIN_IC_DM 43
170 #define BCM281XX_PIN_IC_DP 44
171 #define BCM281XX_PIN_KP_COL_IP_0 45
172 #define BCM281XX_PIN_KP_COL_IP_1 46
173 #define BCM281XX_PIN_KP_COL_IP_2 47
174 #define BCM281XX_PIN_KP_COL_IP_3 48
175 #define BCM281XX_PIN_KP_ROW_OP_0 49
176 #define BCM281XX_PIN_KP_ROW_OP_1 50
177 #define BCM281XX_PIN_KP_ROW_OP_2 51
178 #define BCM281XX_PIN_KP_ROW_OP_3 52
179 #define BCM281XX_PIN_LCD_B_0 53
180 #define BCM281XX_PIN_LCD_B_1 54
181 #define BCM281XX_PIN_LCD_B_2 55
182 #define BCM281XX_PIN_LCD_B_3 56
183 #define BCM281XX_PIN_LCD_B_4 57
184 #define BCM281XX_PIN_LCD_B_5 58
185 #define BCM281XX_PIN_LCD_B_6 59
186 #define BCM281XX_PIN_LCD_B_7 60
187 #define BCM281XX_PIN_LCD_G_0 61
188 #define BCM281XX_PIN_LCD_G_1 62
189 #define BCM281XX_PIN_LCD_G_2 63
190 #define BCM281XX_PIN_LCD_G_3 64
191 #define BCM281XX_PIN_LCD_G_4 65
192 #define BCM281XX_PIN_LCD_G_5 66
193 #define BCM281XX_PIN_LCD_G_6 67
194 #define BCM281XX_PIN_LCD_G_7 68
195 #define BCM281XX_PIN_LCD_HSYNC 69
196 #define BCM281XX_PIN_LCD_OE 70
197 #define BCM281XX_PIN_LCD_PCLK 71
198 #define BCM281XX_PIN_LCD_R_0 72
199 #define BCM281XX_PIN_LCD_R_1 73
200 #define BCM281XX_PIN_LCD_R_2 74
201 #define BCM281XX_PIN_LCD_R_3 75
202 #define BCM281XX_PIN_LCD_R_4 76
203 #define BCM281XX_PIN_LCD_R_5 77
204 #define BCM281XX_PIN_LCD_R_6 78
205 #define BCM281XX_PIN_LCD_R_7 79
206 #define BCM281XX_PIN_LCD_VSYNC 80
207 #define BCM281XX_PIN_MDMGPIO0 81
208 #define BCM281XX_PIN_MDMGPIO1 82
209 #define BCM281XX_PIN_MDMGPIO2 83
210 #define BCM281XX_PIN_MDMGPIO3 84
211 #define BCM281XX_PIN_MDMGPIO4 85
212 #define BCM281XX_PIN_MDMGPIO5 86
213 #define BCM281XX_PIN_MDMGPIO6 87
214 #define BCM281XX_PIN_MDMGPIO7 88
215 #define BCM281XX_PIN_MDMGPIO8 89
216 #define BCM281XX_PIN_MPHI_DATA_0 90
217 #define BCM281XX_PIN_MPHI_DATA_1 91
218 #define BCM281XX_PIN_MPHI_DATA_2 92
219 #define BCM281XX_PIN_MPHI_DATA_3 93
220 #define BCM281XX_PIN_MPHI_DATA_4 94
221 #define BCM281XX_PIN_MPHI_DATA_5 95
222 #define BCM281XX_PIN_MPHI_DATA_6 96
223 #define BCM281XX_PIN_MPHI_DATA_7 97
224 #define BCM281XX_PIN_MPHI_DATA_8 98
225 #define BCM281XX_PIN_MPHI_DATA_9 99
226 #define BCM281XX_PIN_MPHI_DATA_10 100
227 #define BCM281XX_PIN_MPHI_DATA_11 101
228 #define BCM281XX_PIN_MPHI_DATA_12 102
229 #define BCM281XX_PIN_MPHI_DATA_13 103
230 #define BCM281XX_PIN_MPHI_DATA_14 104
231 #define BCM281XX_PIN_MPHI_DATA_15 105
232 #define BCM281XX_PIN_MPHI_HA0 106
233 #define BCM281XX_PIN_MPHI_HAT0 107
234 #define BCM281XX_PIN_MPHI_HAT1 108
235 #define BCM281XX_PIN_MPHI_HCE0_N 109
236 #define BCM281XX_PIN_MPHI_HCE1_N 110
237 #define BCM281XX_PIN_MPHI_HRD_N 111
238 #define BCM281XX_PIN_MPHI_HWR_N 112
239 #define BCM281XX_PIN_MPHI_RUN0 113
240 #define BCM281XX_PIN_MPHI_RUN1 114
241 #define BCM281XX_PIN_MTX_SCAN_CLK 115
242 #define BCM281XX_PIN_MTX_SCAN_DATA 116
243 #define BCM281XX_PIN_NAND_AD_0 117
244 #define BCM281XX_PIN_NAND_AD_1 118
245 #define BCM281XX_PIN_NAND_AD_2 119
246 #define BCM281XX_PIN_NAND_AD_3 120
247 #define BCM281XX_PIN_NAND_AD_4 121
248 #define BCM281XX_PIN_NAND_AD_5 122
249 #define BCM281XX_PIN_NAND_AD_6 123
250 #define BCM281XX_PIN_NAND_AD_7 124
251 #define BCM281XX_PIN_NAND_ALE 125
252 #define BCM281XX_PIN_NAND_CEN_0 126
253 #define BCM281XX_PIN_NAND_CEN_1 127
254 #define BCM281XX_PIN_NAND_CLE 128
255 #define BCM281XX_PIN_NAND_OEN 129
256 #define BCM281XX_PIN_NAND_RDY_0 130
257 #define BCM281XX_PIN_NAND_RDY_1 131
258 #define BCM281XX_PIN_NAND_WEN 132
259 #define BCM281XX_PIN_NAND_WP 133
260 #define BCM281XX_PIN_PC1 134
261 #define BCM281XX_PIN_PC2 135
262 #define BCM281XX_PIN_PMU_INT 136
263 #define BCM281XX_PIN_PMU_SCL 137
264 #define BCM281XX_PIN_PMU_SDA 138
265 #define BCM281XX_PIN_RFST2G_MTSLOTEN3G 139
266 #define BCM281XX_PIN_RGMII_0_RX_CTL 140
267 #define BCM281XX_PIN_RGMII_0_RXC 141
268 #define BCM281XX_PIN_RGMII_0_RXD_0 142
269 #define BCM281XX_PIN_RGMII_0_RXD_1 143
270 #define BCM281XX_PIN_RGMII_0_RXD_2 144
271 #define BCM281XX_PIN_RGMII_0_RXD_3 145
272 #define BCM281XX_PIN_RGMII_0_TX_CTL 146
273 #define BCM281XX_PIN_RGMII_0_TXC 147
274 #define BCM281XX_PIN_RGMII_0_TXD_0 148
275 #define BCM281XX_PIN_RGMII_0_TXD_1 149
276 #define BCM281XX_PIN_RGMII_0_TXD_2 150
277 #define BCM281XX_PIN_RGMII_0_TXD_3 151
278 #define BCM281XX_PIN_RGMII_1_RX_CTL 152
279 #define BCM281XX_PIN_RGMII_1_RXC 153
280 #define BCM281XX_PIN_RGMII_1_RXD_0 154
281 #define BCM281XX_PIN_RGMII_1_RXD_1 155
282 #define BCM281XX_PIN_RGMII_1_RXD_2 156
283 #define BCM281XX_PIN_RGMII_1_RXD_3 157
284 #define BCM281XX_PIN_RGMII_1_TX_CTL 158
285 #define BCM281XX_PIN_RGMII_1_TXC 159
286 #define BCM281XX_PIN_RGMII_1_TXD_0 160
287 #define BCM281XX_PIN_RGMII_1_TXD_1 161
288 #define BCM281XX_PIN_RGMII_1_TXD_2 162
289 #define BCM281XX_PIN_RGMII_1_TXD_3 163
290 #define BCM281XX_PIN_RGMII_GPIO_0 164
291 #define BCM281XX_PIN_RGMII_GPIO_1 165
292 #define BCM281XX_PIN_RGMII_GPIO_2 166
293 #define BCM281XX_PIN_RGMII_GPIO_3 167
294 #define BCM281XX_PIN_RTXDATA2G_TXDATA3G1 168
295 #define BCM281XX_PIN_RTXEN2G_TXDATA3G2 169
296 #define BCM281XX_PIN_RXDATA3G0 170
297 #define BCM281XX_PIN_RXDATA3G1 171
298 #define BCM281XX_PIN_RXDATA3G2 172
299 #define BCM281XX_PIN_SDIO1_CLK 173
300 #define BCM281XX_PIN_SDIO1_CMD 174
301 #define BCM281XX_PIN_SDIO1_DATA_0 175
302 #define BCM281XX_PIN_SDIO1_DATA_1 176
303 #define BCM281XX_PIN_SDIO1_DATA_2 177
304 #define BCM281XX_PIN_SDIO1_DATA_3 178
305 #define BCM281XX_PIN_SDIO4_CLK 179
306 #define BCM281XX_PIN_SDIO4_CMD 180
307 #define BCM281XX_PIN_SDIO4_DATA_0 181
308 #define BCM281XX_PIN_SDIO4_DATA_1 182
309 #define BCM281XX_PIN_SDIO4_DATA_2 183
310 #define BCM281XX_PIN_SDIO4_DATA_3 184
311 #define BCM281XX_PIN_SIM_CLK 185
312 #define BCM281XX_PIN_SIM_DATA 186
313 #define BCM281XX_PIN_SIM_DET 187
314 #define BCM281XX_PIN_SIM_RESETN 188
315 #define BCM281XX_PIN_SIM2_CLK 189
316 #define BCM281XX_PIN_SIM2_DATA 190
317 #define BCM281XX_PIN_SIM2_DET 191
318 #define BCM281XX_PIN_SIM2_RESETN 192
319 #define BCM281XX_PIN_SRI_C 193
320 #define BCM281XX_PIN_SRI_D 194
321 #define BCM281XX_PIN_SRI_E 195
322 #define BCM281XX_PIN_SSP_EXTCLK 196
323 #define BCM281XX_PIN_SSP0_CLK 197
324 #define BCM281XX_PIN_SSP0_FS 198
325 #define BCM281XX_PIN_SSP0_RXD 199
326 #define BCM281XX_PIN_SSP0_TXD 200
327 #define BCM281XX_PIN_SSP2_CLK 201
328 #define BCM281XX_PIN_SSP2_FS_0 202
329 #define BCM281XX_PIN_SSP2_FS_1 203
330 #define BCM281XX_PIN_SSP2_FS_2 204
331 #define BCM281XX_PIN_SSP2_FS_3 205
332 #define BCM281XX_PIN_SSP2_RXD_0 206
333 #define BCM281XX_PIN_SSP2_RXD_1 207
334 #define BCM281XX_PIN_SSP2_TXD_0 208
335 #define BCM281XX_PIN_SSP2_TXD_1 209
336 #define BCM281XX_PIN_SSP3_CLK 210
337 #define BCM281XX_PIN_SSP3_FS 211
338 #define BCM281XX_PIN_SSP3_RXD 212
339 #define BCM281XX_PIN_SSP3_TXD 213
340 #define BCM281XX_PIN_SSP4_CLK 214
341 #define BCM281XX_PIN_SSP4_FS 215
342 #define BCM281XX_PIN_SSP4_RXD 216
343 #define BCM281XX_PIN_SSP4_TXD 217
344 #define BCM281XX_PIN_SSP5_CLK 218
345 #define BCM281XX_PIN_SSP5_FS 219
346 #define BCM281XX_PIN_SSP5_RXD 220
347 #define BCM281XX_PIN_SSP5_TXD 221
348 #define BCM281XX_PIN_SSP6_CLK 222
349 #define BCM281XX_PIN_SSP6_FS 223
350 #define BCM281XX_PIN_SSP6_RXD 224
351 #define BCM281XX_PIN_SSP6_TXD 225
352 #define BCM281XX_PIN_STAT_1 226
353 #define BCM281XX_PIN_STAT_2 227
354 #define BCM281XX_PIN_SYSCLKEN 228
355 #define BCM281XX_PIN_TRACECLK 229
356 #define BCM281XX_PIN_TRACEDT00 230
357 #define BCM281XX_PIN_TRACEDT01 231
358 #define BCM281XX_PIN_TRACEDT02 232
359 #define BCM281XX_PIN_TRACEDT03 233
360 #define BCM281XX_PIN_TRACEDT04 234
361 #define BCM281XX_PIN_TRACEDT05 235
362 #define BCM281XX_PIN_TRACEDT06 236
363 #define BCM281XX_PIN_TRACEDT07 237
364 #define BCM281XX_PIN_TRACEDT08 238
365 #define BCM281XX_PIN_TRACEDT09 239
366 #define BCM281XX_PIN_TRACEDT10 240
367 #define BCM281XX_PIN_TRACEDT11 241
368 #define BCM281XX_PIN_TRACEDT12 242
369 #define BCM281XX_PIN_TRACEDT13 243
370 #define BCM281XX_PIN_TRACEDT14 244
371 #define BCM281XX_PIN_TRACEDT15 245
372 #define BCM281XX_PIN_TXDATA3G0 246
373 #define BCM281XX_PIN_TXPWRIND 247
374 #define BCM281XX_PIN_UARTB1_UCTS 248
375 #define BCM281XX_PIN_UARTB1_URTS 249
376 #define BCM281XX_PIN_UARTB1_URXD 250
377 #define BCM281XX_PIN_UARTB1_UTXD 251
378 #define BCM281XX_PIN_UARTB2_URXD 252
379 #define BCM281XX_PIN_UARTB2_UTXD 253
380 #define BCM281XX_PIN_UARTB3_UCTS 254
381 #define BCM281XX_PIN_UARTB3_URTS 255
382 #define BCM281XX_PIN_UARTB3_URXD 256
383 #define BCM281XX_PIN_UARTB3_UTXD 257
384 #define BCM281XX_PIN_UARTB4_UCTS 258
385 #define BCM281XX_PIN_UARTB4_URTS 259
386 #define BCM281XX_PIN_UARTB4_URXD 260
387 #define BCM281XX_PIN_UARTB4_UTXD 261
388 #define BCM281XX_PIN_VC_CAM1_SCL 262
389 #define BCM281XX_PIN_VC_CAM1_SDA 263
390 #define BCM281XX_PIN_VC_CAM2_SCL 264
391 #define BCM281XX_PIN_VC_CAM2_SDA 265
392 #define BCM281XX_PIN_VC_CAM3_SCL 266
393 #define BCM281XX_PIN_VC_CAM3_SDA 267
394
395 #define BCM281XX_PIN_DESC(a, b, c) \
396 { .number = a, .name = b, .drv_data = &c##_pin }
397
398 /*
399 * Pin description definition. The order here must be the same as defined in
400 * the PADCTRLREG block in the RDB, since the pin number is used as an index
401 * into this array.
402 */
403 static const struct pinctrl_pin_desc bcm281xx_pinctrl_pins[] = {
404 BCM281XX_PIN_DESC(BCM281XX_PIN_ADCSYNC, "adcsync", std),
405 BCM281XX_PIN_DESC(BCM281XX_PIN_BAT_RM, "bat_rm", std),
406 BCM281XX_PIN_DESC(BCM281XX_PIN_BSC1_SCL, "bsc1_scl", i2c),
407 BCM281XX_PIN_DESC(BCM281XX_PIN_BSC1_SDA, "bsc1_sda", i2c),
408 BCM281XX_PIN_DESC(BCM281XX_PIN_BSC2_SCL, "bsc2_scl", i2c),
409 BCM281XX_PIN_DESC(BCM281XX_PIN_BSC2_SDA, "bsc2_sda", i2c),
410 BCM281XX_PIN_DESC(BCM281XX_PIN_CLASSGPWR, "classgpwr", std),
411 BCM281XX_PIN_DESC(BCM281XX_PIN_CLK_CX8, "clk_cx8", std),
412 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_0, "clkout_0", std),
413 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_1, "clkout_1", std),
414 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_2, "clkout_2", std),
415 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_3, "clkout_3", std),
416 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKREQ_IN_0, "clkreq_in_0", std),
417 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKREQ_IN_1, "clkreq_in_1", std),
418 BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ1, "cws_sys_req1", std),
419 BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ2, "cws_sys_req2", std),
420 BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ3, "cws_sys_req3", std),
421 BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC1_CLK, "digmic1_clk", std),
422 BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC1_DQ, "digmic1_dq", std),
423 BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC2_CLK, "digmic2_clk", std),
424 BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC2_DQ, "digmic2_dq", std),
425 BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN13, "gpen13", std),
426 BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN14, "gpen14", std),
427 BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN15, "gpen15", std),
428 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO00, "gpio00", std),
429 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO01, "gpio01", std),
430 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO02, "gpio02", std),
431 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO03, "gpio03", std),
432 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO04, "gpio04", std),
433 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO05, "gpio05", std),
434 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO06, "gpio06", std),
435 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO07, "gpio07", std),
436 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO08, "gpio08", std),
437 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO09, "gpio09", std),
438 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO10, "gpio10", std),
439 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO11, "gpio11", std),
440 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO12, "gpio12", std),
441 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO13, "gpio13", std),
442 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO14, "gpio14", std),
443 BCM281XX_PIN_DESC(BCM281XX_PIN_GPS_PABLANK, "gps_pablank", std),
444 BCM281XX_PIN_DESC(BCM281XX_PIN_GPS_TMARK, "gps_tmark", std),
445 BCM281XX_PIN_DESC(BCM281XX_PIN_HDMI_SCL, "hdmi_scl", hdmi),
446 BCM281XX_PIN_DESC(BCM281XX_PIN_HDMI_SDA, "hdmi_sda", hdmi),
447 BCM281XX_PIN_DESC(BCM281XX_PIN_IC_DM, "ic_dm", std),
448 BCM281XX_PIN_DESC(BCM281XX_PIN_IC_DP, "ic_dp", std),
449 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_0, "kp_col_ip_0", std),
450 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_1, "kp_col_ip_1", std),
451 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_2, "kp_col_ip_2", std),
452 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_3, "kp_col_ip_3", std),
453 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_0, "kp_row_op_0", std),
454 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_1, "kp_row_op_1", std),
455 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_2, "kp_row_op_2", std),
456 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_3, "kp_row_op_3", std),
457 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_0, "lcd_b_0", std),
458 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_1, "lcd_b_1", std),
459 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_2, "lcd_b_2", std),
460 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_3, "lcd_b_3", std),
461 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_4, "lcd_b_4", std),
462 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_5, "lcd_b_5", std),
463 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_6, "lcd_b_6", std),
464 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_7, "lcd_b_7", std),
465 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_0, "lcd_g_0", std),
466 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_1, "lcd_g_1", std),
467 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_2, "lcd_g_2", std),
468 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_3, "lcd_g_3", std),
469 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_4, "lcd_g_4", std),
470 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_5, "lcd_g_5", std),
471 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_6, "lcd_g_6", std),
472 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_7, "lcd_g_7", std),
473 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_HSYNC, "lcd_hsync", std),
474 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_OE, "lcd_oe", std),
475 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_PCLK, "lcd_pclk", std),
476 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_0, "lcd_r_0", std),
477 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_1, "lcd_r_1", std),
478 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_2, "lcd_r_2", std),
479 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_3, "lcd_r_3", std),
480 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_4, "lcd_r_4", std),
481 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_5, "lcd_r_5", std),
482 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_6, "lcd_r_6", std),
483 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_7, "lcd_r_7", std),
484 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_VSYNC, "lcd_vsync", std),
485 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO0, "mdmgpio0", std),
486 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO1, "mdmgpio1", std),
487 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO2, "mdmgpio2", std),
488 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO3, "mdmgpio3", std),
489 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO4, "mdmgpio4", std),
490 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO5, "mdmgpio5", std),
491 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO6, "mdmgpio6", std),
492 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO7, "mdmgpio7", std),
493 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO8, "mdmgpio8", std),
494 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_0, "mphi_data_0", std),
495 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_1, "mphi_data_1", std),
496 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_2, "mphi_data_2", std),
497 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_3, "mphi_data_3", std),
498 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_4, "mphi_data_4", std),
499 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_5, "mphi_data_5", std),
500 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_6, "mphi_data_6", std),
501 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_7, "mphi_data_7", std),
502 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_8, "mphi_data_8", std),
503 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_9, "mphi_data_9", std),
504 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_10, "mphi_data_10", std),
505 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_11, "mphi_data_11", std),
506 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_12, "mphi_data_12", std),
507 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_13, "mphi_data_13", std),
508 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_14, "mphi_data_14", std),
509 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_15, "mphi_data_15", std),
510 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HA0, "mphi_ha0", std),
511 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HAT0, "mphi_hat0", std),
512 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HAT1, "mphi_hat1", std),
513 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HCE0_N, "mphi_hce0_n", std),
514 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HCE1_N, "mphi_hce1_n", std),
515 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HRD_N, "mphi_hrd_n", std),
516 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HWR_N, "mphi_hwr_n", std),
517 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_RUN0, "mphi_run0", std),
518 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_RUN1, "mphi_run1", std),
519 BCM281XX_PIN_DESC(BCM281XX_PIN_MTX_SCAN_CLK, "mtx_scan_clk", std),
520 BCM281XX_PIN_DESC(BCM281XX_PIN_MTX_SCAN_DATA, "mtx_scan_data", std),
521 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_0, "nand_ad_0", std),
522 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_1, "nand_ad_1", std),
523 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_2, "nand_ad_2", std),
524 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_3, "nand_ad_3", std),
525 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_4, "nand_ad_4", std),
526 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_5, "nand_ad_5", std),
527 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_6, "nand_ad_6", std),
528 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_7, "nand_ad_7", std),
529 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_ALE, "nand_ale", std),
530 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CEN_0, "nand_cen_0", std),
531 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CEN_1, "nand_cen_1", std),
532 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CLE, "nand_cle", std),
533 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_OEN, "nand_oen", std),
534 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_RDY_0, "nand_rdy_0", std),
535 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_RDY_1, "nand_rdy_1", std),
536 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_WEN, "nand_wen", std),
537 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_WP, "nand_wp", std),
538 BCM281XX_PIN_DESC(BCM281XX_PIN_PC1, "pc1", std),
539 BCM281XX_PIN_DESC(BCM281XX_PIN_PC2, "pc2", std),
540 BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_INT, "pmu_int", std),
541 BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_SCL, "pmu_scl", i2c),
542 BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_SDA, "pmu_sda", i2c),
543 BCM281XX_PIN_DESC(BCM281XX_PIN_RFST2G_MTSLOTEN3G, "rfst2g_mtsloten3g",
544 std),
545 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RX_CTL, "rgmii_0_rx_ctl", std),
546 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXC, "rgmii_0_rxc", std),
547 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_0, "rgmii_0_rxd_0", std),
548 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_1, "rgmii_0_rxd_1", std),
549 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_2, "rgmii_0_rxd_2", std),
550 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_3, "rgmii_0_rxd_3", std),
551 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TX_CTL, "rgmii_0_tx_ctl", std),
552 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXC, "rgmii_0_txc", std),
553 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_0, "rgmii_0_txd_0", std),
554 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_1, "rgmii_0_txd_1", std),
555 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_2, "rgmii_0_txd_2", std),
556 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_3, "rgmii_0_txd_3", std),
557 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RX_CTL, "rgmii_1_rx_ctl", std),
558 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXC, "rgmii_1_rxc", std),
559 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_0, "rgmii_1_rxd_0", std),
560 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_1, "rgmii_1_rxd_1", std),
561 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_2, "rgmii_1_rxd_2", std),
562 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_3, "rgmii_1_rxd_3", std),
563 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TX_CTL, "rgmii_1_tx_ctl", std),
564 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXC, "rgmii_1_txc", std),
565 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_0, "rgmii_1_txd_0", std),
566 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_1, "rgmii_1_txd_1", std),
567 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_2, "rgmii_1_txd_2", std),
568 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_3, "rgmii_1_txd_3", std),
569 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_0, "rgmii_gpio_0", std),
570 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_1, "rgmii_gpio_1", std),
571 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_2, "rgmii_gpio_2", std),
572 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_3, "rgmii_gpio_3", std),
573 BCM281XX_PIN_DESC(BCM281XX_PIN_RTXDATA2G_TXDATA3G1,
574 "rtxdata2g_txdata3g1", std),
575 BCM281XX_PIN_DESC(BCM281XX_PIN_RTXEN2G_TXDATA3G2, "rtxen2g_txdata3g2",
576 std),
577 BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G0, "rxdata3g0", std),
578 BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G1, "rxdata3g1", std),
579 BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G2, "rxdata3g2", std),
580 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_CLK, "sdio1_clk", std),
581 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_CMD, "sdio1_cmd", std),
582 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_0, "sdio1_data_0", std),
583 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_1, "sdio1_data_1", std),
584 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_2, "sdio1_data_2", std),
585 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_3, "sdio1_data_3", std),
586 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_CLK, "sdio4_clk", std),
587 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_CMD, "sdio4_cmd", std),
588 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_0, "sdio4_data_0", std),
589 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_1, "sdio4_data_1", std),
590 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_2, "sdio4_data_2", std),
591 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_3, "sdio4_data_3", std),
592 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_CLK, "sim_clk", std),
593 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_DATA, "sim_data", std),
594 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_DET, "sim_det", std),
595 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_RESETN, "sim_resetn", std),
596 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_CLK, "sim2_clk", std),
597 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_DATA, "sim2_data", std),
598 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_DET, "sim2_det", std),
599 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_RESETN, "sim2_resetn", std),
600 BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_C, "sri_c", std),
601 BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_D, "sri_d", std),
602 BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_E, "sri_e", std),
603 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP_EXTCLK, "ssp_extclk", std),
604 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_CLK, "ssp0_clk", std),
605 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_FS, "ssp0_fs", std),
606 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_RXD, "ssp0_rxd", std),
607 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_TXD, "ssp0_txd", std),
608 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_CLK, "ssp2_clk", std),
609 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_0, "ssp2_fs_0", std),
610 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_1, "ssp2_fs_1", std),
611 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_2, "ssp2_fs_2", std),
612 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_3, "ssp2_fs_3", std),
613 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_RXD_0, "ssp2_rxd_0", std),
614 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_RXD_1, "ssp2_rxd_1", std),
615 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_TXD_0, "ssp2_txd_0", std),
616 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_TXD_1, "ssp2_txd_1", std),
617 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_CLK, "ssp3_clk", std),
618 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_FS, "ssp3_fs", std),
619 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_RXD, "ssp3_rxd", std),
620 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_TXD, "ssp3_txd", std),
621 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_CLK, "ssp4_clk", std),
622 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_FS, "ssp4_fs", std),
623 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_RXD, "ssp4_rxd", std),
624 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_TXD, "ssp4_txd", std),
625 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_CLK, "ssp5_clk", std),
626 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_FS, "ssp5_fs", std),
627 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_RXD, "ssp5_rxd", std),
628 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_TXD, "ssp5_txd", std),
629 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_CLK, "ssp6_clk", std),
630 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_FS, "ssp6_fs", std),
631 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_RXD, "ssp6_rxd", std),
632 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_TXD, "ssp6_txd", std),
633 BCM281XX_PIN_DESC(BCM281XX_PIN_STAT_1, "stat_1", std),
634 BCM281XX_PIN_DESC(BCM281XX_PIN_STAT_2, "stat_2", std),
635 BCM281XX_PIN_DESC(BCM281XX_PIN_SYSCLKEN, "sysclken", std),
636 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACECLK, "traceclk", std),
637 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT00, "tracedt00", std),
638 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT01, "tracedt01", std),
639 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT02, "tracedt02", std),
640 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT03, "tracedt03", std),
641 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT04, "tracedt04", std),
642 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT05, "tracedt05", std),
643 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT06, "tracedt06", std),
644 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT07, "tracedt07", std),
645 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT08, "tracedt08", std),
646 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT09, "tracedt09", std),
647 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT10, "tracedt10", std),
648 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT11, "tracedt11", std),
649 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT12, "tracedt12", std),
650 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT13, "tracedt13", std),
651 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT14, "tracedt14", std),
652 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT15, "tracedt15", std),
653 BCM281XX_PIN_DESC(BCM281XX_PIN_TXDATA3G0, "txdata3g0", std),
654 BCM281XX_PIN_DESC(BCM281XX_PIN_TXPWRIND, "txpwrind", std),
655 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_UCTS, "uartb1_ucts", std),
656 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_URTS, "uartb1_urts", std),
657 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_URXD, "uartb1_urxd", std),
658 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_UTXD, "uartb1_utxd", std),
659 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB2_URXD, "uartb2_urxd", std),
660 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB2_UTXD, "uartb2_utxd", std),
661 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_UCTS, "uartb3_ucts", std),
662 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_URTS, "uartb3_urts", std),
663 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_URXD, "uartb3_urxd", std),
664 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_UTXD, "uartb3_utxd", std),
665 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_UCTS, "uartb4_ucts", std),
666 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_URTS, "uartb4_urts", std),
667 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_URXD, "uartb4_urxd", std),
668 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_UTXD, "uartb4_utxd", std),
669 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM1_SCL, "vc_cam1_scl", i2c),
670 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM1_SDA, "vc_cam1_sda", i2c),
671 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM2_SCL, "vc_cam2_scl", i2c),
672 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM2_SDA, "vc_cam2_sda", i2c),
673 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM3_SCL, "vc_cam3_scl", i2c),
674 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM3_SDA, "vc_cam3_sda", i2c),
675 };
676
677 static const char * const bcm281xx_alt_groups[] = {
678 "adcsync",
679 "bat_rm",
680 "bsc1_scl",
681 "bsc1_sda",
682 "bsc2_scl",
683 "bsc2_sda",
684 "classgpwr",
685 "clk_cx8",
686 "clkout_0",
687 "clkout_1",
688 "clkout_2",
689 "clkout_3",
690 "clkreq_in_0",
691 "clkreq_in_1",
692 "cws_sys_req1",
693 "cws_sys_req2",
694 "cws_sys_req3",
695 "digmic1_clk",
696 "digmic1_dq",
697 "digmic2_clk",
698 "digmic2_dq",
699 "gpen13",
700 "gpen14",
701 "gpen15",
702 "gpio00",
703 "gpio01",
704 "gpio02",
705 "gpio03",
706 "gpio04",
707 "gpio05",
708 "gpio06",
709 "gpio07",
710 "gpio08",
711 "gpio09",
712 "gpio10",
713 "gpio11",
714 "gpio12",
715 "gpio13",
716 "gpio14",
717 "gps_pablank",
718 "gps_tmark",
719 "hdmi_scl",
720 "hdmi_sda",
721 "ic_dm",
722 "ic_dp",
723 "kp_col_ip_0",
724 "kp_col_ip_1",
725 "kp_col_ip_2",
726 "kp_col_ip_3",
727 "kp_row_op_0",
728 "kp_row_op_1",
729 "kp_row_op_2",
730 "kp_row_op_3",
731 "lcd_b_0",
732 "lcd_b_1",
733 "lcd_b_2",
734 "lcd_b_3",
735 "lcd_b_4",
736 "lcd_b_5",
737 "lcd_b_6",
738 "lcd_b_7",
739 "lcd_g_0",
740 "lcd_g_1",
741 "lcd_g_2",
742 "lcd_g_3",
743 "lcd_g_4",
744 "lcd_g_5",
745 "lcd_g_6",
746 "lcd_g_7",
747 "lcd_hsync",
748 "lcd_oe",
749 "lcd_pclk",
750 "lcd_r_0",
751 "lcd_r_1",
752 "lcd_r_2",
753 "lcd_r_3",
754 "lcd_r_4",
755 "lcd_r_5",
756 "lcd_r_6",
757 "lcd_r_7",
758 "lcd_vsync",
759 "mdmgpio0",
760 "mdmgpio1",
761 "mdmgpio2",
762 "mdmgpio3",
763 "mdmgpio4",
764 "mdmgpio5",
765 "mdmgpio6",
766 "mdmgpio7",
767 "mdmgpio8",
768 "mphi_data_0",
769 "mphi_data_1",
770 "mphi_data_2",
771 "mphi_data_3",
772 "mphi_data_4",
773 "mphi_data_5",
774 "mphi_data_6",
775 "mphi_data_7",
776 "mphi_data_8",
777 "mphi_data_9",
778 "mphi_data_10",
779 "mphi_data_11",
780 "mphi_data_12",
781 "mphi_data_13",
782 "mphi_data_14",
783 "mphi_data_15",
784 "mphi_ha0",
785 "mphi_hat0",
786 "mphi_hat1",
787 "mphi_hce0_n",
788 "mphi_hce1_n",
789 "mphi_hrd_n",
790 "mphi_hwr_n",
791 "mphi_run0",
792 "mphi_run1",
793 "mtx_scan_clk",
794 "mtx_scan_data",
795 "nand_ad_0",
796 "nand_ad_1",
797 "nand_ad_2",
798 "nand_ad_3",
799 "nand_ad_4",
800 "nand_ad_5",
801 "nand_ad_6",
802 "nand_ad_7",
803 "nand_ale",
804 "nand_cen_0",
805 "nand_cen_1",
806 "nand_cle",
807 "nand_oen",
808 "nand_rdy_0",
809 "nand_rdy_1",
810 "nand_wen",
811 "nand_wp",
812 "pc1",
813 "pc2",
814 "pmu_int",
815 "pmu_scl",
816 "pmu_sda",
817 "rfst2g_mtsloten3g",
818 "rgmii_0_rx_ctl",
819 "rgmii_0_rxc",
820 "rgmii_0_rxd_0",
821 "rgmii_0_rxd_1",
822 "rgmii_0_rxd_2",
823 "rgmii_0_rxd_3",
824 "rgmii_0_tx_ctl",
825 "rgmii_0_txc",
826 "rgmii_0_txd_0",
827 "rgmii_0_txd_1",
828 "rgmii_0_txd_2",
829 "rgmii_0_txd_3",
830 "rgmii_1_rx_ctl",
831 "rgmii_1_rxc",
832 "rgmii_1_rxd_0",
833 "rgmii_1_rxd_1",
834 "rgmii_1_rxd_2",
835 "rgmii_1_rxd_3",
836 "rgmii_1_tx_ctl",
837 "rgmii_1_txc",
838 "rgmii_1_txd_0",
839 "rgmii_1_txd_1",
840 "rgmii_1_txd_2",
841 "rgmii_1_txd_3",
842 "rgmii_gpio_0",
843 "rgmii_gpio_1",
844 "rgmii_gpio_2",
845 "rgmii_gpio_3",
846 "rtxdata2g_txdata3g1",
847 "rtxen2g_txdata3g2",
848 "rxdata3g0",
849 "rxdata3g1",
850 "rxdata3g2",
851 "sdio1_clk",
852 "sdio1_cmd",
853 "sdio1_data_0",
854 "sdio1_data_1",
855 "sdio1_data_2",
856 "sdio1_data_3",
857 "sdio4_clk",
858 "sdio4_cmd",
859 "sdio4_data_0",
860 "sdio4_data_1",
861 "sdio4_data_2",
862 "sdio4_data_3",
863 "sim_clk",
864 "sim_data",
865 "sim_det",
866 "sim_resetn",
867 "sim2_clk",
868 "sim2_data",
869 "sim2_det",
870 "sim2_resetn",
871 "sri_c",
872 "sri_d",
873 "sri_e",
874 "ssp_extclk",
875 "ssp0_clk",
876 "ssp0_fs",
877 "ssp0_rxd",
878 "ssp0_txd",
879 "ssp2_clk",
880 "ssp2_fs_0",
881 "ssp2_fs_1",
882 "ssp2_fs_2",
883 "ssp2_fs_3",
884 "ssp2_rxd_0",
885 "ssp2_rxd_1",
886 "ssp2_txd_0",
887 "ssp2_txd_1",
888 "ssp3_clk",
889 "ssp3_fs",
890 "ssp3_rxd",
891 "ssp3_txd",
892 "ssp4_clk",
893 "ssp4_fs",
894 "ssp4_rxd",
895 "ssp4_txd",
896 "ssp5_clk",
897 "ssp5_fs",
898 "ssp5_rxd",
899 "ssp5_txd",
900 "ssp6_clk",
901 "ssp6_fs",
902 "ssp6_rxd",
903 "ssp6_txd",
904 "stat_1",
905 "stat_2",
906 "sysclken",
907 "traceclk",
908 "tracedt00",
909 "tracedt01",
910 "tracedt02",
911 "tracedt03",
912 "tracedt04",
913 "tracedt05",
914 "tracedt06",
915 "tracedt07",
916 "tracedt08",
917 "tracedt09",
918 "tracedt10",
919 "tracedt11",
920 "tracedt12",
921 "tracedt13",
922 "tracedt14",
923 "tracedt15",
924 "txdata3g0",
925 "txpwrind",
926 "uartb1_ucts",
927 "uartb1_urts",
928 "uartb1_urxd",
929 "uartb1_utxd",
930 "uartb2_urxd",
931 "uartb2_utxd",
932 "uartb3_ucts",
933 "uartb3_urts",
934 "uartb3_urxd",
935 "uartb3_utxd",
936 "uartb4_ucts",
937 "uartb4_urts",
938 "uartb4_urxd",
939 "uartb4_utxd",
940 "vc_cam1_scl",
941 "vc_cam1_sda",
942 "vc_cam2_scl",
943 "vc_cam2_sda",
944 "vc_cam3_scl",
945 "vc_cam3_sda",
946 };
947
948 /* Every pin can implement all ALT1-ALT4 functions */
949 #define BCM281XX_PIN_FUNCTION(fcn_name) \
950 { \
951 .name = #fcn_name, \
952 .groups = bcm281xx_alt_groups, \
953 .ngroups = ARRAY_SIZE(bcm281xx_alt_groups), \
954 }
955
956 static const struct bcm281xx_pin_function bcm281xx_functions[] = {
957 BCM281XX_PIN_FUNCTION(alt1),
958 BCM281XX_PIN_FUNCTION(alt2),
959 BCM281XX_PIN_FUNCTION(alt3),
960 BCM281XX_PIN_FUNCTION(alt4),
961 };
962
963 static const struct regmap_config bcm281xx_pinctrl_regmap_config = {
964 .reg_bits = 32,
965 .reg_stride = 4,
966 .val_bits = 32,
967 .max_register = BCM281XX_PIN_VC_CAM3_SDA * 4,
968 };
969
970 static const struct bcm281xx_pinctrl_info bcm281xx_pinctrl = {
971 .device_type = BCM281XX_PINCTRL_TYPE,
972
973 .pins = bcm281xx_pinctrl_pins,
974 .npins = ARRAY_SIZE(bcm281xx_pinctrl_pins),
975 .functions = bcm281xx_functions,
976 .nfunctions = ARRAY_SIZE(bcm281xx_functions),
977
978 .regmap_config = &bcm281xx_pinctrl_regmap_config,
979 };
980
981 /* BCM21664 data */
982 #define BCM21664_PIN_ADCSYN 0
983 #define BCM21664_PIN_BATRM 1
984 #define BCM21664_PIN_BSC1CLK 2
985 #define BCM21664_PIN_BSC1DAT 3
986 #define BCM21664_PIN_CAMCS0 4
987 #define BCM21664_PIN_CAMCS1 5
988 #define BCM21664_PIN_CLK32K 6
989 #define BCM21664_PIN_CLK_CX8 7
990 #define BCM21664_PIN_DCLK1 8
991 #define BCM21664_PIN_DCLK4 9
992 #define BCM21664_PIN_DCLKREQ1 10
993 #define BCM21664_PIN_DCLKREQ4 11
994 #define BCM21664_PIN_DMIC0CLK 12
995 #define BCM21664_PIN_DMIC0DQ 13
996 #define BCM21664_PIN_DSI0TE 14
997 #define BCM21664_PIN_GPIO00 15
998 #define BCM21664_PIN_GPIO01 16
999 #define BCM21664_PIN_GPIO02 17
1000 #define BCM21664_PIN_GPIO03 18
1001 #define BCM21664_PIN_GPIO04 19
1002 #define BCM21664_PIN_GPIO05 20
1003 #define BCM21664_PIN_GPIO06 21
1004 #define BCM21664_PIN_GPIO07 22
1005 #define BCM21664_PIN_GPIO08 23
1006 #define BCM21664_PIN_GPIO09 24
1007 #define BCM21664_PIN_GPIO10 25
1008 #define BCM21664_PIN_GPIO11 26
1009 #define BCM21664_PIN_GPIO12 27
1010 #define BCM21664_PIN_GPIO13 28
1011 #define BCM21664_PIN_GPIO14 29
1012 #define BCM21664_PIN_GPIO15 30
1013 #define BCM21664_PIN_GPIO16 31
1014 #define BCM21664_PIN_GPIO17 32
1015 #define BCM21664_PIN_GPIO18 33
1016 #define BCM21664_PIN_GPIO19 34
1017 #define BCM21664_PIN_GPIO20 35
1018 #define BCM21664_PIN_GPIO21 36
1019 #define BCM21664_PIN_GPIO22 37
1020 #define BCM21664_PIN_GPIO23 38
1021 #define BCM21664_PIN_GPIO24 39
1022 #define BCM21664_PIN_GPIO25 40
1023 #define BCM21664_PIN_GPIO26 41
1024 #define BCM21664_PIN_GPIO27 42
1025 #define BCM21664_PIN_GPIO28 43
1026 #define BCM21664_PIN_GPIO32 44
1027 #define BCM21664_PIN_GPIO33 45
1028 #define BCM21664_PIN_GPIO34 46
1029 #define BCM21664_PIN_GPS_CALREQ 47
1030 #define BCM21664_PIN_GPS_HOSTREQ 48
1031 #define BCM21664_PIN_GPS_PABLANK 49
1032 #define BCM21664_PIN_GPS_TMARK 50
1033 #define BCM21664_PIN_ICUSBDM 51
1034 #define BCM21664_PIN_ICUSBDP 52
1035 #define BCM21664_PIN_LCDCS0 53
1036 #define BCM21664_PIN_LCDRES 54
1037 #define BCM21664_PIN_LCDSCL 55
1038 #define BCM21664_PIN_LCDSDA 56
1039 #define BCM21664_PIN_LCDTE 57
1040 #define BCM21664_PIN_MDMGPIO00 58
1041 #define BCM21664_PIN_MDMGPIO01 59
1042 #define BCM21664_PIN_MDMGPIO02 60
1043 #define BCM21664_PIN_MDMGPIO03 61
1044 #define BCM21664_PIN_MDMGPIO04 62
1045 #define BCM21664_PIN_MDMGPIO05 63
1046 #define BCM21664_PIN_MDMGPIO06 64
1047 #define BCM21664_PIN_MDMGPIO07 65
1048 #define BCM21664_PIN_MDMGPIO08 66
1049 #define BCM21664_PIN_MMC0CK 67
1050 #define BCM21664_PIN_MMC0CMD 68
1051 #define BCM21664_PIN_MMC0DAT0 69
1052 #define BCM21664_PIN_MMC0DAT1 70
1053 #define BCM21664_PIN_MMC0DAT2 71
1054 #define BCM21664_PIN_MMC0DAT3 72
1055 #define BCM21664_PIN_MMC0DAT4 73
1056 #define BCM21664_PIN_MMC0DAT5 74
1057 #define BCM21664_PIN_MMC0DAT6 75
1058 #define BCM21664_PIN_MMC0DAT7 76
1059 #define BCM21664_PIN_MMC0RST 77
1060 #define BCM21664_PIN_MMC1CK 78
1061 #define BCM21664_PIN_MMC1CMD 79
1062 #define BCM21664_PIN_MMC1DAT0 80
1063 #define BCM21664_PIN_MMC1DAT1 81
1064 #define BCM21664_PIN_MMC1DAT2 82
1065 #define BCM21664_PIN_MMC1DAT3 83
1066 #define BCM21664_PIN_MMC1DAT4 84
1067 #define BCM21664_PIN_MMC1DAT5 85
1068 #define BCM21664_PIN_MMC1DAT6 86
1069 #define BCM21664_PIN_MMC1DAT7 87
1070 #define BCM21664_PIN_MMC1RST 88
1071 #define BCM21664_PIN_PC1 89
1072 #define BCM21664_PIN_PC2 90
1073 #define BCM21664_PIN_PMBSCCLK 91
1074 #define BCM21664_PIN_PMBSCDAT 92
1075 #define BCM21664_PIN_PMUINT 93
1076 #define BCM21664_PIN_RESETN 94
1077 #define BCM21664_PIN_RFST2G_MTSLOTEN3G 95
1078 #define BCM21664_PIN_RTXDATA2G_TXDATA3G1 96
1079 #define BCM21664_PIN_RTXEN2G_TXDATA3G2 97
1080 #define BCM21664_PIN_RXDATA3G0 98
1081 #define BCM21664_PIN_RXDATA3G1 99
1082 #define BCM21664_PIN_RXDATA3G2 100
1083 #define BCM21664_PIN_SDCK 101
1084 #define BCM21664_PIN_SDCMD 102
1085 #define BCM21664_PIN_SDDAT0 103
1086 #define BCM21664_PIN_SDDAT1 104
1087 #define BCM21664_PIN_SDDAT2 105
1088 #define BCM21664_PIN_SDDAT3 106
1089 #define BCM21664_PIN_SIMCLK 107
1090 #define BCM21664_PIN_SIMDAT 108
1091 #define BCM21664_PIN_SIMDET 109
1092 #define BCM21664_PIN_SIMRST 110
1093 #define BCM21664_PIN_GPIO93 111
1094 #define BCM21664_PIN_GPIO94 112
1095 #define BCM21664_PIN_SPI0CLK 113
1096 #define BCM21664_PIN_SPI0FSS 114
1097 #define BCM21664_PIN_SPI0RXD 115
1098 #define BCM21664_PIN_SPI0TXD 116
1099 #define BCM21664_PIN_SRI_C 117
1100 #define BCM21664_PIN_SRI_D 118
1101 #define BCM21664_PIN_SRI_E 119
1102 #define BCM21664_PIN_SSPCK 120
1103 #define BCM21664_PIN_SSPDI 121
1104 #define BCM21664_PIN_SSPDO 122
1105 #define BCM21664_PIN_SSPSYN 123
1106 #define BCM21664_PIN_STAT1 124
1107 #define BCM21664_PIN_STAT2 125
1108 #define BCM21664_PIN_SWCLKTCK 126
1109 #define BCM21664_PIN_SWDIOTMS 127
1110 #define BCM21664_PIN_SYSCLKEN 128
1111 #define BCM21664_PIN_TDI 129
1112 #define BCM21664_PIN_TDO 130
1113 #define BCM21664_PIN_TESTMODE 131
1114 #define BCM21664_PIN_TRACECLK 132
1115 #define BCM21664_PIN_TRACEDT00 133
1116 #define BCM21664_PIN_TRACEDT01 134
1117 #define BCM21664_PIN_TRACEDT02 135
1118 #define BCM21664_PIN_TRACEDT03 136
1119 #define BCM21664_PIN_TRACEDT04 137
1120 #define BCM21664_PIN_TRACEDT05 138
1121 #define BCM21664_PIN_TRACEDT06 139
1122 #define BCM21664_PIN_TRACEDT07 140
1123 #define BCM21664_PIN_TRSTB 141
1124 #define BCM21664_PIN_TXDATA3G0 142
1125 #define BCM21664_PIN_UBCTSN 143
1126 #define BCM21664_PIN_UBRTSN 144
1127 #define BCM21664_PIN_UBRX 145
1128 #define BCM21664_PIN_UBTX 146
1129 #define BCM21664_PIN_TRACEDT08 147
1130 #define BCM21664_PIN_TRACEDT09 148
1131 #define BCM21664_PIN_TRACEDT10 149
1132 #define BCM21664_PIN_TRACEDT11 150
1133 #define BCM21664_PIN_TRACEDT12 151
1134 #define BCM21664_PIN_TRACEDT13 152
1135 #define BCM21664_PIN_TRACEDT14 153
1136 #define BCM21664_PIN_TRACEDT15 154
1137
1138 static const struct pinctrl_pin_desc bcm21664_pinctrl_pins[] = {
1139 BCM281XX_PIN_DESC(BCM21664_PIN_ADCSYN, "adcsyn", std),
1140 BCM281XX_PIN_DESC(BCM21664_PIN_BATRM, "batrm", std),
1141 BCM281XX_PIN_DESC(BCM21664_PIN_BSC1CLK, "bsc1clk", i2c),
1142 BCM281XX_PIN_DESC(BCM21664_PIN_BSC1DAT, "bsc1dat", i2c),
1143 BCM281XX_PIN_DESC(BCM21664_PIN_CAMCS0, "camcs0", std),
1144 BCM281XX_PIN_DESC(BCM21664_PIN_CAMCS1, "camcs1", std),
1145 BCM281XX_PIN_DESC(BCM21664_PIN_CLK32K, "clk32k", std),
1146 BCM281XX_PIN_DESC(BCM21664_PIN_CLK_CX8, "clk_cx8", std),
1147 BCM281XX_PIN_DESC(BCM21664_PIN_DCLK1, "dclk1", std),
1148 BCM281XX_PIN_DESC(BCM21664_PIN_DCLK4, "dclk4", std),
1149 BCM281XX_PIN_DESC(BCM21664_PIN_DCLKREQ1, "dclkreq1", std),
1150 BCM281XX_PIN_DESC(BCM21664_PIN_DCLKREQ4, "dclkreq4", std),
1151 BCM281XX_PIN_DESC(BCM21664_PIN_DMIC0CLK, "dmic0clk", std),
1152 BCM281XX_PIN_DESC(BCM21664_PIN_DMIC0DQ, "dmic0dq", std),
1153 BCM281XX_PIN_DESC(BCM21664_PIN_DSI0TE, "dsi0te", std),
1154 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO00, "gpio00", std),
1155 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO01, "gpio01", std),
1156 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO02, "gpio02", std),
1157 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO03, "gpio03", std),
1158 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO04, "gpio04", std),
1159 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO05, "gpio05", std),
1160 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO06, "gpio06", std),
1161 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO07, "gpio07", std),
1162 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO08, "gpio08", std),
1163 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO09, "gpio09", std),
1164 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO10, "gpio10", std),
1165 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO11, "gpio11", std),
1166 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO12, "gpio12", std),
1167 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO13, "gpio13", std),
1168 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO14, "gpio14", std),
1169 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO15, "gpio15", std),
1170 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO16, "gpio16", i2c),
1171 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO17, "gpio17", i2c),
1172 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO18, "gpio18", std),
1173 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO19, "gpio19", std),
1174 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO20, "gpio20", std),
1175 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO21, "gpio21", std),
1176 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO22, "gpio22", std),
1177 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO23, "gpio23", std),
1178 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO24, "gpio24", std),
1179 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO25, "gpio25", std),
1180 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO26, "gpio26", std),
1181 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO27, "gpio27", std),
1182 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO28, "gpio28", std),
1183 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO32, "gpio32", std),
1184 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO33, "gpio33", std),
1185 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO34, "gpio34", std),
1186 BCM281XX_PIN_DESC(BCM21664_PIN_GPS_CALREQ, "gps_calreq", std),
1187 BCM281XX_PIN_DESC(BCM21664_PIN_GPS_HOSTREQ, "gps_hostreq", std),
1188 BCM281XX_PIN_DESC(BCM21664_PIN_GPS_PABLANK, "gps_pablank", std),
1189 BCM281XX_PIN_DESC(BCM21664_PIN_GPS_TMARK, "gps_tmark", std),
1190 BCM281XX_PIN_DESC(BCM21664_PIN_ICUSBDM, "icusbdm", std),
1191 BCM281XX_PIN_DESC(BCM21664_PIN_ICUSBDP, "icusbdp", std),
1192 BCM281XX_PIN_DESC(BCM21664_PIN_LCDCS0, "lcdcs0", std),
1193 BCM281XX_PIN_DESC(BCM21664_PIN_LCDRES, "lcdres", std),
1194 BCM281XX_PIN_DESC(BCM21664_PIN_LCDSCL, "lcdscl", std),
1195 BCM281XX_PIN_DESC(BCM21664_PIN_LCDSDA, "lcdsda", std),
1196 BCM281XX_PIN_DESC(BCM21664_PIN_LCDTE, "lcdte", std),
1197 BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO00, "mdmgpio00", std),
1198 BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO01, "mdmgpio01", std),
1199 BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO02, "mdmgpio02", std),
1200 BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO03, "mdmgpio03", std),
1201 BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO04, "mdmgpio04", std),
1202 BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO05, "mdmgpio05", std),
1203 BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO06, "mdmgpio06", std),
1204 BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO07, "mdmgpio07", std),
1205 BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO08, "mdmgpio08", std),
1206 BCM281XX_PIN_DESC(BCM21664_PIN_MMC0CK, "mmc0ck", std),
1207 BCM281XX_PIN_DESC(BCM21664_PIN_MMC0CMD, "mmc0cmd", std),
1208 BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT0, "mmc0dat0", std),
1209 BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT1, "mmc0dat1", std),
1210 BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT2, "mmc0dat2", std),
1211 BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT3, "mmc0dat3", std),
1212 BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT4, "mmc0dat4", std),
1213 BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT5, "mmc0dat5", std),
1214 BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT6, "mmc0dat6", std),
1215 BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT7, "mmc0dat7", std),
1216 BCM281XX_PIN_DESC(BCM21664_PIN_MMC0RST, "mmc0rst", std),
1217 BCM281XX_PIN_DESC(BCM21664_PIN_MMC1CK, "mmc1ck", std),
1218 BCM281XX_PIN_DESC(BCM21664_PIN_MMC1CMD, "mmc1cmd", std),
1219 BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT0, "mmc1dat0", std),
1220 BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT1, "mmc1dat1", std),
1221 BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT2, "mmc1dat2", std),
1222 BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT3, "mmc1dat3", std),
1223 BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT4, "mmc1dat4", std),
1224 BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT5, "mmc1dat5", std),
1225 BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT6, "mmc1dat6", std),
1226 BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT7, "mmc1dat7", std),
1227 BCM281XX_PIN_DESC(BCM21664_PIN_MMC1RST, "mmc1rst", std),
1228 BCM281XX_PIN_DESC(BCM21664_PIN_PC1, "pc1", std),
1229 BCM281XX_PIN_DESC(BCM21664_PIN_PC2, "pc2", std),
1230 BCM281XX_PIN_DESC(BCM21664_PIN_PMBSCCLK, "pmbscclk", i2c),
1231 BCM281XX_PIN_DESC(BCM21664_PIN_PMBSCDAT, "pmbscdat", i2c),
1232 BCM281XX_PIN_DESC(BCM21664_PIN_PMUINT, "pmuint", std),
1233 BCM281XX_PIN_DESC(BCM21664_PIN_RESETN, "resetn", std),
1234 BCM281XX_PIN_DESC(BCM21664_PIN_RFST2G_MTSLOTEN3G, "rfst2g_mtsloten3g", std),
1235 BCM281XX_PIN_DESC(BCM21664_PIN_RTXDATA2G_TXDATA3G1, "rtxdata2g_txdata3g1", std),
1236 BCM281XX_PIN_DESC(BCM21664_PIN_RTXEN2G_TXDATA3G2, "rtxen2g_txdata3g2", std),
1237 BCM281XX_PIN_DESC(BCM21664_PIN_RXDATA3G0, "rxdata3g0", std),
1238 BCM281XX_PIN_DESC(BCM21664_PIN_RXDATA3G1, "rxdata3g1", std),
1239 BCM281XX_PIN_DESC(BCM21664_PIN_RXDATA3G2, "rxdata3g2", std),
1240 BCM281XX_PIN_DESC(BCM21664_PIN_SDCK, "sdck", std),
1241 BCM281XX_PIN_DESC(BCM21664_PIN_SDCMD, "sdcmd", std),
1242 BCM281XX_PIN_DESC(BCM21664_PIN_SDDAT0, "sddat0", std),
1243 BCM281XX_PIN_DESC(BCM21664_PIN_SDDAT1, "sddat1", std),
1244 BCM281XX_PIN_DESC(BCM21664_PIN_SDDAT2, "sddat2", std),
1245 BCM281XX_PIN_DESC(BCM21664_PIN_SDDAT3, "sddat3", std),
1246 BCM281XX_PIN_DESC(BCM21664_PIN_SIMCLK, "simclk", std),
1247 BCM281XX_PIN_DESC(BCM21664_PIN_SIMDAT, "simdat", std),
1248 BCM281XX_PIN_DESC(BCM21664_PIN_SIMDET, "simdet", std),
1249 BCM281XX_PIN_DESC(BCM21664_PIN_SIMRST, "simrst", std),
1250 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO93, "gpio93", std),
1251 BCM281XX_PIN_DESC(BCM21664_PIN_GPIO94, "gpio94", std),
1252 BCM281XX_PIN_DESC(BCM21664_PIN_SPI0CLK, "spi0clk", std),
1253 BCM281XX_PIN_DESC(BCM21664_PIN_SPI0FSS, "spi0fss", std),
1254 BCM281XX_PIN_DESC(BCM21664_PIN_SPI0RXD, "spi0rxd", std),
1255 BCM281XX_PIN_DESC(BCM21664_PIN_SPI0TXD, "spi0txd", std),
1256 BCM281XX_PIN_DESC(BCM21664_PIN_SRI_C, "sri_c", std),
1257 BCM281XX_PIN_DESC(BCM21664_PIN_SRI_D, "sri_d", std),
1258 BCM281XX_PIN_DESC(BCM21664_PIN_SRI_E, "sri_e", std),
1259 BCM281XX_PIN_DESC(BCM21664_PIN_SSPCK, "sspck", std),
1260 BCM281XX_PIN_DESC(BCM21664_PIN_SSPDI, "sspdi", std),
1261 BCM281XX_PIN_DESC(BCM21664_PIN_SSPDO, "sspdo", std),
1262 BCM281XX_PIN_DESC(BCM21664_PIN_SSPSYN, "sspsyn", std),
1263 BCM281XX_PIN_DESC(BCM21664_PIN_STAT1, "stat1", std),
1264 BCM281XX_PIN_DESC(BCM21664_PIN_STAT2, "stat2", std),
1265 BCM281XX_PIN_DESC(BCM21664_PIN_SWCLKTCK, "swclktck", std),
1266 BCM281XX_PIN_DESC(BCM21664_PIN_SWDIOTMS, "swdiotms", std),
1267 BCM281XX_PIN_DESC(BCM21664_PIN_SYSCLKEN, "sysclken", std),
1268 BCM281XX_PIN_DESC(BCM21664_PIN_TDI, "tdi", std),
1269 BCM281XX_PIN_DESC(BCM21664_PIN_TDO, "tdo", std),
1270 BCM281XX_PIN_DESC(BCM21664_PIN_TESTMODE, "testmode", std),
1271 BCM281XX_PIN_DESC(BCM21664_PIN_TRACECLK, "traceclk", std),
1272 BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT00, "tracedt00", std),
1273 BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT01, "tracedt01", std),
1274 BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT02, "tracedt02", std),
1275 BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT03, "tracedt03", std),
1276 BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT04, "tracedt04", std),
1277 BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT05, "tracedt05", std),
1278 BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT06, "tracedt06", std),
1279 BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT07, "tracedt07", std),
1280 BCM281XX_PIN_DESC(BCM21664_PIN_TRSTB, "trstb", std),
1281 BCM281XX_PIN_DESC(BCM21664_PIN_TXDATA3G0, "txdata3g0", std),
1282 BCM281XX_PIN_DESC(BCM21664_PIN_UBCTSN, "ubctsn", std),
1283 BCM281XX_PIN_DESC(BCM21664_PIN_UBRTSN, "ubrtsn", std),
1284 BCM281XX_PIN_DESC(BCM21664_PIN_UBRX, "ubrx", std),
1285 BCM281XX_PIN_DESC(BCM21664_PIN_UBTX, "ubtx", std),
1286 BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT08, "tracedt08", std),
1287 BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT09, "tracedt09", std),
1288 BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT10, "tracedt10", std),
1289 BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT11, "tracedt11", std),
1290 BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT12, "tracedt12", std),
1291 BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT13, "tracedt13", std),
1292 BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT14, "tracedt14", std),
1293 BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT15, "tracedt15", std),
1294 };
1295
1296 static const char * const bcm21664_alt_groups[] = {
1297 "adcsyn",
1298 "batrm",
1299 "bsc1clk",
1300 "bsc1dat",
1301 "camcs0",
1302 "camcs1",
1303 "clk32k",
1304 "clk_cx8",
1305 "dclk1",
1306 "dclk4",
1307 "dclkreq1",
1308 "dclkreq4",
1309 "dmic0clk",
1310 "dmic0dq",
1311 "dsi0te",
1312 "gpio00",
1313 "gpio01",
1314 "gpio02",
1315 "gpio03",
1316 "gpio04",
1317 "gpio05",
1318 "gpio06",
1319 "gpio07",
1320 "gpio08",
1321 "gpio09",
1322 "gpio10",
1323 "gpio11",
1324 "gpio12",
1325 "gpio13",
1326 "gpio14",
1327 "gpio15",
1328 "gpio16",
1329 "gpio17",
1330 "gpio18",
1331 "gpio19",
1332 "gpio20",
1333 "gpio21",
1334 "gpio22",
1335 "gpio23",
1336 "gpio24",
1337 "gpio25",
1338 "gpio26",
1339 "gpio27",
1340 "gpio28",
1341 "gpio32",
1342 "gpio33",
1343 "gpio34",
1344 "gps_calreq",
1345 "gps_hostreq",
1346 "gps_pablank",
1347 "gps_tmark",
1348 "icusbdm",
1349 "icusbdp",
1350 "lcdcs0",
1351 "lcdres",
1352 "lcdscl",
1353 "lcdsda",
1354 "lcdte",
1355 "mdmgpio00",
1356 "mdmgpio01",
1357 "mdmgpio02",
1358 "mdmgpio03",
1359 "mdmgpio04",
1360 "mdmgpio05",
1361 "mdmgpio06",
1362 "mdmgpio07",
1363 "mdmgpio08",
1364 "mmc0ck",
1365 "mmc0cmd",
1366 "mmc0dat0",
1367 "mmc0dat1",
1368 "mmc0dat2",
1369 "mmc0dat3",
1370 "mmc0dat4",
1371 "mmc0dat5",
1372 "mmc0dat6",
1373 "mmc0dat7",
1374 "mmc0rst",
1375 "mmc1ck",
1376 "mmc1cmd",
1377 "mmc1dat0",
1378 "mmc1dat1",
1379 "mmc1dat2",
1380 "mmc1dat3",
1381 "mmc1dat4",
1382 "mmc1dat5",
1383 "mmc1dat6",
1384 "mmc1dat7",
1385 "mmc1rst",
1386 "pc1",
1387 "pc2",
1388 "pmbscclk",
1389 "pmbscdat",
1390 "pmuint",
1391 "resetn",
1392 "rfst2g_mtsloten3g",
1393 "rtxdata2g_txdata3g1",
1394 "rtxen2g_txdata3g2",
1395 "rxdata3g0",
1396 "rxdata3g1",
1397 "rxdata3g2",
1398 "sdck",
1399 "sdcmd",
1400 "sddat0",
1401 "sddat1",
1402 "sddat2",
1403 "sddat3",
1404 "simclk",
1405 "simdat",
1406 "simdet",
1407 "simrst",
1408 "gpio93",
1409 "gpio94",
1410 "spi0clk",
1411 "spi0fss",
1412 "spi0rxd",
1413 "spi0txd",
1414 "sri_c",
1415 "sri_d",
1416 "sri_e",
1417 "sspck",
1418 "sspdi",
1419 "sspdo",
1420 "sspsyn",
1421 "stat1",
1422 "stat2",
1423 "swclktck",
1424 "swdiotms",
1425 "sysclken",
1426 "tdi",
1427 "tdo",
1428 "testmode",
1429 "traceclk",
1430 "tracedt00",
1431 "tracedt01",
1432 "tracedt02",
1433 "tracedt03",
1434 "tracedt04",
1435 "tracedt05",
1436 "tracedt06",
1437 "tracedt07",
1438 "trstb",
1439 "txdata3g0",
1440 "ubctsn",
1441 "ubrtsn",
1442 "ubrx",
1443 "ubtx",
1444 "tracedt08",
1445 "tracedt09",
1446 "tracedt10",
1447 "tracedt11",
1448 "tracedt12",
1449 "tracedt13",
1450 "tracedt14",
1451 "tracedt15",
1452 };
1453
1454 #define BCM21664_PIN_FUNCTION(fcn_name) \
1455 { \
1456 .name = #fcn_name, \
1457 .groups = bcm21664_alt_groups, \
1458 .ngroups = ARRAY_SIZE(bcm21664_alt_groups), \
1459 }
1460
1461 static const struct bcm281xx_pin_function bcm21664_functions[] = {
1462 BCM21664_PIN_FUNCTION(alt1),
1463 BCM21664_PIN_FUNCTION(alt2),
1464 BCM21664_PIN_FUNCTION(alt3),
1465 BCM21664_PIN_FUNCTION(alt4),
1466 BCM21664_PIN_FUNCTION(alt5),
1467 BCM21664_PIN_FUNCTION(alt6),
1468 };
1469
1470 static const struct regmap_config bcm21664_pinctrl_regmap_config = {
1471 .reg_bits = 32,
1472 .reg_stride = 4,
1473 .val_bits = 32,
1474 .max_register = BCM21664_WR_ACCESS_OFFSET,
1475 };
1476
1477 static const struct bcm281xx_pinctrl_info bcm21664_pinctrl = {
1478 .device_type = BCM21664_PINCTRL_TYPE,
1479
1480 .pins = bcm21664_pinctrl_pins,
1481 .npins = ARRAY_SIZE(bcm21664_pinctrl_pins),
1482 .functions = bcm21664_functions,
1483 .nfunctions = ARRAY_SIZE(bcm21664_functions),
1484
1485 .regmap_config = &bcm21664_pinctrl_regmap_config,
1486 };
1487
1488 /* BCM21664 pinctrl access lock handlers */
bcm21664_pinctrl_lock_all(struct bcm281xx_pinctrl_data * pdata)1489 static int bcm21664_pinctrl_lock_all(struct bcm281xx_pinctrl_data *pdata)
1490 {
1491 int i, rc;
1492
1493 for (i = 0; i < BCM21664_ACCESS_LOCK_COUNT; i++) {
1494 rc = regmap_write(pdata->regmap, BCM21664_WR_ACCESS_OFFSET,
1495 BCM21664_WR_ACCESS_PASSWORD);
1496 if (rc) {
1497 dev_err(pdata->dev, "Failed to enable write access: %d\n",
1498 rc);
1499 return rc;
1500 }
1501 rc = regmap_write(pdata->regmap, BCM21664_ACCESS_LOCK_OFFSET(i),
1502 0xffffffff);
1503 if (rc) {
1504 dev_err(pdata->dev, "Failed to write access lock: %d\n",
1505 rc);
1506 return rc;
1507 }
1508 }
1509
1510 return 0;
1511 }
1512
bcm21664_pinctrl_set_pin_lock(struct bcm281xx_pinctrl_data * pdata,unsigned int pin,bool lock)1513 static int bcm21664_pinctrl_set_pin_lock(struct bcm281xx_pinctrl_data *pdata,
1514 unsigned int pin, bool lock)
1515 {
1516 unsigned int access_lock = pin / 32;
1517 int rc;
1518
1519 dev_dbg(pdata->dev,
1520 "%s(): %s pin %s (%d)\n",
1521 __func__, lock ? "Lock" : "Unlock", pdata->info->pins[pin].name,
1522 pin);
1523
1524 rc = regmap_write(pdata->regmap, BCM21664_WR_ACCESS_OFFSET,
1525 BCM21664_WR_ACCESS_PASSWORD);
1526 if (rc) {
1527 dev_err(pdata->dev, "Failed to enable write access: %d\n",
1528 rc);
1529 return rc;
1530 }
1531
1532 rc = regmap_update_bits(pdata->regmap,
1533 BCM21664_ACCESS_LOCK_OFFSET(access_lock),
1534 BIT(pin % 32),
1535 (int)lock << (pin % 32));
1536
1537 if (rc) {
1538 dev_err(pdata->dev, "Failed to %s pin: %d\n",
1539 lock ? "lock" : "unlock", rc);
1540 return rc;
1541 }
1542
1543 return 0;
1544 }
1545
pin_type_get(struct pinctrl_dev * pctldev,unsigned int pin)1546 static inline enum bcm281xx_pin_type pin_type_get(struct pinctrl_dev *pctldev,
1547 unsigned int pin)
1548 {
1549 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1550
1551 if (pin >= pdata->info->npins)
1552 return BCM281XX_PIN_TYPE_UNKNOWN;
1553
1554 return *(enum bcm281xx_pin_type *)(pdata->info->pins[pin].drv_data);
1555 }
1556
1557 #define BCM281XX_PIN_SHIFT(type, param) \
1558 (BCM281XX_ ## type ## _PIN_REG_ ## param ## _SHIFT)
1559
1560 #define BCM281XX_PIN_MASK(type, param) \
1561 (BCM281XX_ ## type ## _PIN_REG_ ## param ## _MASK)
1562
1563 /*
1564 * This helper function is used to build up the value and mask used to write to
1565 * a pin register, but does not actually write to the register.
1566 */
bcm281xx_pin_update(u32 * reg_val,u32 * reg_mask,u32 param_val,u32 param_shift,u32 param_mask)1567 static inline void bcm281xx_pin_update(u32 *reg_val, u32 *reg_mask,
1568 u32 param_val, u32 param_shift,
1569 u32 param_mask)
1570 {
1571 *reg_val &= ~param_mask;
1572 *reg_val |= (param_val << param_shift) & param_mask;
1573 *reg_mask |= param_mask;
1574 }
1575
bcm281xx_pinctrl_get_groups_count(struct pinctrl_dev * pctldev)1576 static int bcm281xx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
1577 {
1578 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1579
1580 return pdata->info->npins;
1581 }
1582
bcm281xx_pinctrl_get_group_name(struct pinctrl_dev * pctldev,unsigned int group)1583 static const char *bcm281xx_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
1584 unsigned int group)
1585 {
1586 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1587
1588 return pdata->info->pins[group].name;
1589 }
1590
bcm281xx_pinctrl_get_group_pins(struct pinctrl_dev * pctldev,unsigned int group,const unsigned ** pins,unsigned int * num_pins)1591 static int bcm281xx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
1592 unsigned int group,
1593 const unsigned **pins,
1594 unsigned int *num_pins)
1595 {
1596 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1597
1598 *pins = &pdata->info->pins[group].number;
1599 *num_pins = 1;
1600
1601 return 0;
1602 }
1603
bcm281xx_pinctrl_pin_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned int offset)1604 static void bcm281xx_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
1605 struct seq_file *s,
1606 unsigned int offset)
1607 {
1608 seq_printf(s, " %s", dev_name(pctldev->dev));
1609 }
1610
1611 static const struct pinctrl_ops bcm281xx_pinctrl_ops = {
1612 .get_groups_count = bcm281xx_pinctrl_get_groups_count,
1613 .get_group_name = bcm281xx_pinctrl_get_group_name,
1614 .get_group_pins = bcm281xx_pinctrl_get_group_pins,
1615 .pin_dbg_show = bcm281xx_pinctrl_pin_dbg_show,
1616 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1617 .dt_free_map = pinctrl_utils_free_map,
1618 };
1619
bcm281xx_pinctrl_get_fcns_count(struct pinctrl_dev * pctldev)1620 static int bcm281xx_pinctrl_get_fcns_count(struct pinctrl_dev *pctldev)
1621 {
1622 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1623
1624 return pdata->info->nfunctions;
1625 }
1626
bcm281xx_pinctrl_get_fcn_name(struct pinctrl_dev * pctldev,unsigned int function)1627 static const char *bcm281xx_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev,
1628 unsigned int function)
1629 {
1630 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1631
1632 return pdata->info->functions[function].name;
1633 }
1634
bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev * pctldev,unsigned int function,const char * const ** groups,unsigned int * const num_groups)1635 static int bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev,
1636 unsigned int function,
1637 const char * const **groups,
1638 unsigned int * const num_groups)
1639 {
1640 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1641
1642 *groups = pdata->info->functions[function].groups;
1643 *num_groups = pdata->info->functions[function].ngroups;
1644
1645 return 0;
1646 }
1647
bcm281xx_pinmux_set(struct pinctrl_dev * pctldev,unsigned int function,unsigned int group)1648 static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev,
1649 unsigned int function,
1650 unsigned int group)
1651 {
1652 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1653 const struct bcm281xx_pin_function *f = &pdata->info->functions[function];
1654 enum bcm281xx_pinctrl_type device_type = pdata->info->device_type;
1655 unsigned int pin = pdata->info->pins[group].number;
1656 u32 offset = 4 * pin;
1657 int rc = 0;
1658
1659 dev_dbg(pctldev->dev,
1660 "%s(): Enable function %s (%d) of pin %s (%d) @offset 0x%x.\n",
1661 __func__, f->name, function, pdata->info->pins[group].name,
1662 pin, offset);
1663
1664 if (device_type == BCM21664_PINCTRL_TYPE) {
1665 rc = bcm21664_pinctrl_set_pin_lock(pdata, pin, false);
1666 if (rc) {
1667 /* Error is printed in bcm21664_pinctrl_set_pin_lock */
1668 return rc;
1669 }
1670 }
1671
1672 rc = regmap_update_bits(pdata->regmap, offset,
1673 BCM281XX_PIN_REG_F_SEL_MASK,
1674 function << BCM281XX_PIN_REG_F_SEL_SHIFT);
1675 if (rc)
1676 dev_err(pctldev->dev,
1677 "Error updating register for pin %s (%d).\n",
1678 pdata->info->pins[group].name, pin);
1679
1680 if (device_type == BCM21664_PINCTRL_TYPE) {
1681 rc = bcm21664_pinctrl_set_pin_lock(pdata, pin, true);
1682 if (rc) {
1683 /* Error is printed in bcm21664_pinctrl_set_pin_lock */
1684 return rc;
1685 }
1686 }
1687
1688 return rc;
1689 }
1690
1691 static const struct pinmux_ops bcm281xx_pinctrl_pinmux_ops = {
1692 .get_functions_count = bcm281xx_pinctrl_get_fcns_count,
1693 .get_function_name = bcm281xx_pinctrl_get_fcn_name,
1694 .get_function_groups = bcm281xx_pinctrl_get_fcn_groups,
1695 .set_mux = bcm281xx_pinmux_set,
1696 };
1697
bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)1698 static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev,
1699 unsigned int pin,
1700 unsigned long *config)
1701 {
1702 return -ENOTSUPP;
1703 }
1704
1705
1706 /* Goes through the configs and update register val/mask */
bcm281xx_std_pin_update(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs,u32 * val,u32 * mask)1707 static int bcm281xx_std_pin_update(struct pinctrl_dev *pctldev,
1708 unsigned int pin,
1709 unsigned long *configs,
1710 unsigned int num_configs,
1711 u32 *val,
1712 u32 *mask)
1713 {
1714 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1715 int i;
1716 enum pin_config_param param;
1717 u32 arg;
1718
1719 for (i = 0; i < num_configs; i++) {
1720 param = pinconf_to_config_param(configs[i]);
1721 arg = pinconf_to_config_argument(configs[i]);
1722
1723 switch (param) {
1724 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1725 arg = (arg >= 1 ? 1 : 0);
1726 bcm281xx_pin_update(val, mask, arg,
1727 BCM281XX_PIN_SHIFT(STD, HYST),
1728 BCM281XX_PIN_MASK(STD, HYST));
1729 break;
1730 /*
1731 * The pin bias can only be one of pull-up, pull-down, or
1732 * disable. The user does not need to specify a value for the
1733 * property, and the default value from pinconf-generic is
1734 * ignored.
1735 */
1736 case PIN_CONFIG_BIAS_DISABLE:
1737 bcm281xx_pin_update(val, mask, 0,
1738 BCM281XX_PIN_SHIFT(STD, PULL_UP),
1739 BCM281XX_PIN_MASK(STD, PULL_UP));
1740 bcm281xx_pin_update(val, mask, 0,
1741 BCM281XX_PIN_SHIFT(STD, PULL_DN),
1742 BCM281XX_PIN_MASK(STD, PULL_DN));
1743 break;
1744
1745 case PIN_CONFIG_BIAS_PULL_UP:
1746 bcm281xx_pin_update(val, mask, 1,
1747 BCM281XX_PIN_SHIFT(STD, PULL_UP),
1748 BCM281XX_PIN_MASK(STD, PULL_UP));
1749 bcm281xx_pin_update(val, mask, 0,
1750 BCM281XX_PIN_SHIFT(STD, PULL_DN),
1751 BCM281XX_PIN_MASK(STD, PULL_DN));
1752 break;
1753
1754 case PIN_CONFIG_BIAS_PULL_DOWN:
1755 bcm281xx_pin_update(val, mask, 0,
1756 BCM281XX_PIN_SHIFT(STD, PULL_UP),
1757 BCM281XX_PIN_MASK(STD, PULL_UP));
1758 bcm281xx_pin_update(val, mask, 1,
1759 BCM281XX_PIN_SHIFT(STD, PULL_DN),
1760 BCM281XX_PIN_MASK(STD, PULL_DN));
1761 break;
1762
1763 case PIN_CONFIG_SLEW_RATE:
1764 arg = (arg >= 1 ? 1 : 0);
1765 bcm281xx_pin_update(val, mask, arg,
1766 BCM281XX_PIN_SHIFT(STD, SLEW),
1767 BCM281XX_PIN_MASK(STD, SLEW));
1768 break;
1769
1770 case PIN_CONFIG_INPUT_ENABLE:
1771 /* inversed since register is for input _disable_ */
1772 arg = (arg >= 1 ? 0 : 1);
1773 bcm281xx_pin_update(val, mask, arg,
1774 BCM281XX_PIN_SHIFT(STD, INPUT_DIS),
1775 BCM281XX_PIN_MASK(STD, INPUT_DIS));
1776 break;
1777
1778 case PIN_CONFIG_DRIVE_STRENGTH:
1779 /* Valid range is 2-16 mA, even numbers only */
1780 if ((arg < 2) || (arg > 16) || (arg % 2)) {
1781 dev_err(pctldev->dev,
1782 "Invalid Drive Strength value (%d) for "
1783 "pin %s (%d). Valid values are "
1784 "(2..16) mA, even numbers only.\n",
1785 arg, pdata->info->pins[pin].name, pin);
1786 return -EINVAL;
1787 }
1788 bcm281xx_pin_update(val, mask, (arg/2)-1,
1789 BCM281XX_PIN_SHIFT(STD, DRV_STR),
1790 BCM281XX_PIN_MASK(STD, DRV_STR));
1791 break;
1792
1793 default:
1794 dev_err(pctldev->dev,
1795 "Unrecognized pin config %d for pin %s (%d).\n",
1796 param, pdata->info->pins[pin].name, pin);
1797 return -EINVAL;
1798
1799 } /* switch config */
1800 } /* for each config */
1801
1802 return 0;
1803 }
1804
1805 /*
1806 * The pull-up strength for an I2C pin is represented by bits 4-6 in the
1807 * register with the following mapping:
1808 * 0b000: No pull-up
1809 * 0b001: 1200 Ohm
1810 * 0b010: 1800 Ohm
1811 * 0b011: 720 Ohm
1812 * 0b100: 2700 Ohm
1813 * 0b101: 831 Ohm
1814 * 0b110: 1080 Ohm
1815 * 0b111: 568 Ohm
1816 * This array maps pull-up strength in Ohms to register values (1+index).
1817 */
1818 static const u16 bcm281xx_pullup_map[] = {
1819 1200, 1800, 720, 2700, 831, 1080, 568
1820 };
1821
1822 /* Goes through the configs and update register val/mask */
bcm281xx_i2c_pin_update(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs,u32 * val,u32 * mask)1823 static int bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev,
1824 unsigned int pin,
1825 unsigned long *configs,
1826 unsigned int num_configs,
1827 u32 *val,
1828 u32 *mask)
1829 {
1830 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1831 int i, j;
1832 enum pin_config_param param;
1833 u32 arg;
1834
1835 for (i = 0; i < num_configs; i++) {
1836 param = pinconf_to_config_param(configs[i]);
1837 arg = pinconf_to_config_argument(configs[i]);
1838
1839 switch (param) {
1840 case PIN_CONFIG_BIAS_PULL_UP:
1841 for (j = 0; j < ARRAY_SIZE(bcm281xx_pullup_map); j++)
1842 if (bcm281xx_pullup_map[j] == arg)
1843 break;
1844
1845 if (j == ARRAY_SIZE(bcm281xx_pullup_map)) {
1846 dev_err(pctldev->dev,
1847 "Invalid pull-up value (%d) for pin %s "
1848 "(%d). Valid values are 568, 720, 831, "
1849 "1080, 1200, 1800, 2700 Ohms.\n",
1850 arg, pdata->info->pins[pin].name, pin);
1851 return -EINVAL;
1852 }
1853
1854 bcm281xx_pin_update(val, mask, j+1,
1855 BCM281XX_PIN_SHIFT(I2C, PULL_UP_STR),
1856 BCM281XX_PIN_MASK(I2C, PULL_UP_STR));
1857 break;
1858
1859 case PIN_CONFIG_BIAS_DISABLE:
1860 bcm281xx_pin_update(val, mask, 0,
1861 BCM281XX_PIN_SHIFT(I2C, PULL_UP_STR),
1862 BCM281XX_PIN_MASK(I2C, PULL_UP_STR));
1863 break;
1864
1865 case PIN_CONFIG_SLEW_RATE:
1866 arg = (arg >= 1 ? 1 : 0);
1867 bcm281xx_pin_update(val, mask, arg,
1868 BCM281XX_PIN_SHIFT(I2C, SLEW),
1869 BCM281XX_PIN_MASK(I2C, SLEW));
1870 break;
1871
1872 case PIN_CONFIG_INPUT_ENABLE:
1873 /* inversed since register is for input _disable_ */
1874 arg = (arg >= 1 ? 0 : 1);
1875 bcm281xx_pin_update(val, mask, arg,
1876 BCM281XX_PIN_SHIFT(I2C, INPUT_DIS),
1877 BCM281XX_PIN_MASK(I2C, INPUT_DIS));
1878 break;
1879
1880 default:
1881 dev_err(pctldev->dev,
1882 "Unrecognized pin config %d for pin %s (%d).\n",
1883 param, pdata->info->pins[pin].name, pin);
1884 return -EINVAL;
1885
1886 } /* switch config */
1887 } /* for each config */
1888
1889 return 0;
1890 }
1891
1892 /* Goes through the configs and update register val/mask */
bcm21664_i2c_pin_update(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs,u32 * val,u32 * mask)1893 static int bcm21664_i2c_pin_update(struct pinctrl_dev *pctldev,
1894 unsigned int pin,
1895 unsigned long *configs,
1896 unsigned int num_configs,
1897 u32 *val,
1898 u32 *mask)
1899 {
1900 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1901 int i;
1902 enum pin_config_param param;
1903 u32 arg;
1904
1905 for (i = 0; i < num_configs; i++) {
1906 param = pinconf_to_config_param(configs[i]);
1907 arg = pinconf_to_config_argument(configs[i]);
1908
1909 /*
1910 * BCM21664 I2C pins use the same config bits as standard pins,
1911 * but only pull up/none, slew rate and input enable/disable
1912 * options are supported.
1913 */
1914 switch (param) {
1915 case PIN_CONFIG_BIAS_PULL_UP:
1916 bcm281xx_pin_update(val, mask, 1,
1917 BCM281XX_PIN_SHIFT(STD, PULL_UP),
1918 BCM281XX_PIN_MASK(STD, PULL_UP));
1919 break;
1920
1921 case PIN_CONFIG_BIAS_DISABLE:
1922 bcm281xx_pin_update(val, mask, 0,
1923 BCM281XX_PIN_SHIFT(STD, PULL_UP),
1924 BCM281XX_PIN_MASK(STD, PULL_UP));
1925 break;
1926
1927 case PIN_CONFIG_SLEW_RATE:
1928 arg = (arg >= 1 ? 1 : 0);
1929 bcm281xx_pin_update(val, mask, arg,
1930 BCM281XX_PIN_SHIFT(STD, SLEW),
1931 BCM281XX_PIN_MASK(STD, SLEW));
1932 break;
1933
1934 case PIN_CONFIG_INPUT_ENABLE:
1935 /* inversed since register is for input _disable_ */
1936 arg = (arg >= 1 ? 0 : 1);
1937 bcm281xx_pin_update(val, mask, arg,
1938 BCM281XX_PIN_SHIFT(STD, INPUT_DIS),
1939 BCM281XX_PIN_MASK(STD, INPUT_DIS));
1940 break;
1941
1942 default:
1943 dev_err(pctldev->dev,
1944 "Unrecognized pin config %d for pin %s (%d).\n",
1945 param, pdata->info->pins[pin].name, pin);
1946 return -EINVAL;
1947
1948 } /* switch config */
1949 } /* for each config */
1950
1951 return 0;
1952 }
1953
1954 /* Goes through the configs and update register val/mask */
bcm281xx_hdmi_pin_update(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs,u32 * val,u32 * mask)1955 static int bcm281xx_hdmi_pin_update(struct pinctrl_dev *pctldev,
1956 unsigned int pin,
1957 unsigned long *configs,
1958 unsigned int num_configs,
1959 u32 *val,
1960 u32 *mask)
1961 {
1962 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1963 int i;
1964 enum pin_config_param param;
1965 u32 arg;
1966
1967 for (i = 0; i < num_configs; i++) {
1968 param = pinconf_to_config_param(configs[i]);
1969 arg = pinconf_to_config_argument(configs[i]);
1970
1971 switch (param) {
1972 case PIN_CONFIG_SLEW_RATE:
1973 arg = (arg >= 1 ? 1 : 0);
1974 bcm281xx_pin_update(val, mask, arg,
1975 BCM281XX_PIN_SHIFT(HDMI, MODE),
1976 BCM281XX_PIN_MASK(HDMI, MODE));
1977 break;
1978
1979 case PIN_CONFIG_INPUT_ENABLE:
1980 /* inversed since register is for input _disable_ */
1981 arg = (arg >= 1 ? 0 : 1);
1982 bcm281xx_pin_update(val, mask, arg,
1983 BCM281XX_PIN_SHIFT(HDMI, INPUT_DIS),
1984 BCM281XX_PIN_MASK(HDMI, INPUT_DIS));
1985 break;
1986
1987 default:
1988 dev_err(pctldev->dev,
1989 "Unrecognized pin config %d for pin %s (%d).\n",
1990 param, pdata->info->pins[pin].name, pin);
1991 return -EINVAL;
1992
1993 } /* switch config */
1994 } /* for each config */
1995
1996 return 0;
1997 }
1998
bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)1999 static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev,
2000 unsigned int pin,
2001 unsigned long *configs,
2002 unsigned int num_configs)
2003 {
2004 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
2005 enum bcm281xx_pinctrl_type device_type = pdata->info->device_type;
2006 enum bcm281xx_pin_type pin_type;
2007 u32 offset = 4 * pin;
2008 u32 cfg_val, cfg_mask;
2009 int rc;
2010
2011 cfg_val = 0;
2012 cfg_mask = 0;
2013 pin_type = pin_type_get(pctldev, pin);
2014
2015 /* Different pins have different configuration options */
2016 switch (pin_type) {
2017 case BCM281XX_PIN_TYPE_STD:
2018 rc = bcm281xx_std_pin_update(pctldev, pin, configs,
2019 num_configs, &cfg_val, &cfg_mask);
2020 break;
2021
2022 case BCM281XX_PIN_TYPE_I2C:
2023 if (device_type == BCM21664_PINCTRL_TYPE)
2024 rc = bcm21664_i2c_pin_update(pctldev, pin, configs,
2025 num_configs, &cfg_val, &cfg_mask);
2026 else
2027 rc = bcm281xx_i2c_pin_update(pctldev, pin, configs,
2028 num_configs, &cfg_val, &cfg_mask);
2029 break;
2030
2031 case BCM281XX_PIN_TYPE_HDMI:
2032 rc = bcm281xx_hdmi_pin_update(pctldev, pin, configs,
2033 num_configs, &cfg_val, &cfg_mask);
2034 break;
2035
2036 default:
2037 dev_err(pctldev->dev, "Unknown pin type for pin %s (%d).\n",
2038 pdata->info->pins[pin].name, pin);
2039 return -EINVAL;
2040
2041 } /* switch pin type */
2042
2043 if (rc)
2044 return rc;
2045
2046 dev_dbg(pctldev->dev,
2047 "%s(): Set pin %s (%d) with config 0x%x, mask 0x%x\n",
2048 __func__, pdata->info->pins[pin].name, pin, cfg_val, cfg_mask);
2049
2050 if (device_type == BCM21664_PINCTRL_TYPE) {
2051 rc = bcm21664_pinctrl_set_pin_lock(pdata, pin, false);
2052 if (rc) {
2053 /* Error is printed in bcm21664_pinctrl_set_pin_lock */
2054 return rc;
2055 }
2056 }
2057
2058 rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val);
2059 if (rc) {
2060 dev_err(pctldev->dev,
2061 "Error updating register for pin %s (%d).\n",
2062 pdata->info->pins[pin].name, pin);
2063 return rc;
2064 }
2065
2066 if (device_type == BCM21664_PINCTRL_TYPE) {
2067 rc = bcm21664_pinctrl_set_pin_lock(pdata, pin, true);
2068 if (rc) {
2069 /* Error is printed in bcm21664_pinctrl_set_pin_lock */
2070 return rc;
2071 }
2072 }
2073
2074 return 0;
2075 }
2076
2077 static const struct pinconf_ops bcm281xx_pinctrl_pinconf_ops = {
2078 .pin_config_get = bcm281xx_pinctrl_pin_config_get,
2079 .pin_config_set = bcm281xx_pinctrl_pin_config_set,
2080 };
2081
2082 static struct pinctrl_desc bcm281xx_pinctrl_desc = {
2083 /* name, pins, npins members initialized in probe function */
2084 .pctlops = &bcm281xx_pinctrl_ops,
2085 .pmxops = &bcm281xx_pinctrl_pinmux_ops,
2086 .confops = &bcm281xx_pinctrl_pinconf_ops,
2087 .owner = THIS_MODULE,
2088 };
2089
2090 static struct bcm281xx_pinctrl_data bcm281xx_pinctrl_pdata;
2091
bcm281xx_pinctrl_probe(struct platform_device * pdev)2092 static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev)
2093 {
2094 struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl_pdata;
2095 struct pinctrl_dev *pctl;
2096 int rc;
2097
2098 /* Set device pointer in platform data */
2099 pdata->dev = &pdev->dev;
2100
2101 /* Get the data to use from OF match */
2102 pdata->info = of_device_get_match_data(&pdev->dev);
2103 if (!pdata->info) {
2104 dev_err(&pdev->dev, "Failed to get data from OF match\n");
2105 return -ENODEV;
2106 }
2107
2108 /* So far We can assume there is only 1 bank of registers */
2109 pdata->reg_base = devm_platform_ioremap_resource(pdev, 0);
2110 if (IS_ERR(pdata->reg_base)) {
2111 dev_err(&pdev->dev, "Failed to ioremap MEM resource\n");
2112 return PTR_ERR(pdata->reg_base);
2113 }
2114
2115 /* Initialize the dynamic part of pinctrl_desc */
2116 pdata->regmap = devm_regmap_init_mmio(&pdev->dev, pdata->reg_base,
2117 pdata->info->regmap_config);
2118 if (IS_ERR(pdata->regmap)) {
2119 dev_err(&pdev->dev, "Regmap MMIO init failed.\n");
2120 return -ENODEV;
2121 }
2122
2123 bcm281xx_pinctrl_desc.name = dev_name(&pdev->dev);
2124 bcm281xx_pinctrl_desc.pins = pdata->info->pins;
2125 bcm281xx_pinctrl_desc.npins = pdata->info->npins;
2126
2127 /*
2128 * For BCM21664, lock all pins by default; they will be unlocked
2129 * as needed
2130 */
2131 if (pdata->info->device_type == BCM21664_PINCTRL_TYPE) {
2132 rc = bcm21664_pinctrl_lock_all(pdata);
2133 if (rc) {
2134 dev_err(&pdev->dev, "Failed to lock all pins\n");
2135 return rc;
2136 }
2137 }
2138
2139 pctl = devm_pinctrl_register(&pdev->dev, &bcm281xx_pinctrl_desc, pdata);
2140 if (IS_ERR(pctl)) {
2141 dev_err(&pdev->dev, "Failed to register pinctrl\n");
2142 return PTR_ERR(pctl);
2143 }
2144
2145 platform_set_drvdata(pdev, pdata);
2146
2147 return 0;
2148 }
2149
2150 static const struct of_device_id bcm281xx_pinctrl_of_match[] = {
2151 { .compatible = "brcm,bcm11351-pinctrl", .data = &bcm281xx_pinctrl },
2152 { .compatible = "brcm,bcm21664-pinctrl", .data = &bcm21664_pinctrl },
2153 { },
2154 };
2155
2156 static struct platform_driver bcm281xx_pinctrl_driver = {
2157 .driver = {
2158 .name = "bcm281xx-pinctrl",
2159 .of_match_table = bcm281xx_pinctrl_of_match,
2160 },
2161 };
2162 builtin_platform_driver_probe(bcm281xx_pinctrl_driver, bcm281xx_pinctrl_probe);
2163