Searched refs:BAR0 (Results 1 – 17 of 17) sorted by relevance
11 For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR214 BAR0 offset Register36 For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0:39 BAR0 offset Register54 For Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:57 BAR0 offset Register78 For Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:81 BAR0 offset Register119 relative to the IOP BAR0.
1085 CONFIG_PORT uses HBA's view of its BAR0.
108 BAR0 Config Region121 BAR0 Config Region + Scratchpad
33 This register will be used to test BAR0. A known pattern will be written34 and read back from MAGIC register to verify BAR0.
239 BAR0 Config Region261 BAR0 Config Region + Self Scratchpad277 | BAR0 | | CONFIG REGION | | BAR0 |293 region and scratchpad region (self scratchpad) using BAR0 of EP controller 1.305 | BAR0 | | | Doorbell 1 +-----------> MSI-X ADDRESS 1 |
148 # RUN pci_ep_bar.BAR0.BAR_TEST ...149 # OK pci_ep_bar.BAR0.BAR_TEST150 ok 1 pci_ep_bar.BAR0.BAR_TEST
98 program BAR0 size as 1MB::106 Program BAR0 Address as DDR (0x2100000). This is the physical address of109 as BAR0 address then when this device will be connected to a host, it will be
21 accepted by a BAR. Note that BAR0 must map PCI configuration space
1141 u64 BAR0, BAR1; in setup_cn23xx_octeon_pf_device() local1144 BAR0 = (u64)(data32 & ~0xf); in setup_cn23xx_octeon_pf_device()1146 BAR0 |= ((u64)data32 << 32); in setup_cn23xx_octeon_pf_device()1152 if (!BAR0 || !BAR1) { in setup_cn23xx_octeon_pf_device()1153 if (!BAR0) in setup_cn23xx_octeon_pf_device()
56 FIXTURE_VARIANT_ADD(pci_ep_bar, BAR0) { .barno = 0 }; in FIXTURE_VARIANT_ADD() argument
167 readl(chip->bar[BAR0].remap_addr + i)); in lola_proc_regs_read()
50 configuration and status BAR0. (hinic_hw_csr.h)
105 /* Also try modern mode if we can't map BAR0 (no IO space). */
1090 /* PF0-6 BAR0 - non-prefetchable memory */1094 /* PF0: VF0-1 BAR0 - non-prefetchable memory */1098 /* PF1: VF0-1 BAR0 - non-prefetchable memory */
2104 /* ENETC0~2 and Timer BAR0 - non-prefetchable memory */2108 /* ENETC0~2: VF0-1 BAR0 - non-prefetchable memory */2149 /* EMDIO BAR0 - non-prefetchable memory */
180 1MB VF BAR0, the address in that VF BAR sets the base of an 8MB region.182 is a BAR0 for one of the VFs. Note that even though the VF BAR
31 The cx2341x exposes its entire 64M memory space to the PCI host via the PCI BAR033 address held in BAR0.54 The registers occupy the 64k space starting at the 0x02000000 offset from BAR0.