1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef B43_NPHY_H_ 3 #define B43_NPHY_H_ 4 5 #include "phy_common.h" 6 #include "ppr.h" 7 8 9 /* N-PHY registers. */ 10 11 #define B43_NPHY_BBCFG B43_PHY_N(0x001) /* BB config */ 12 #define B43_NPHY_BBCFG_RSTCCA 0x4000 /* Reset CCA */ 13 #define B43_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */ 14 #define B43_NPHY_CHANNEL B43_PHY_N(0x005) /* Channel */ 15 #define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */ 16 #define B43_NPHY_BANDCTL B43_PHY_N(0x009) /* Band control */ 17 #define B43_NPHY_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */ 18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */ 19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */ 20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */ 21 #define B43_NPHY_BIST_STAT0 B43_PHY_N(0x00E) /* Built-in self test status 0 */ 22 #define B43_NPHY_BIST_STAT1 B43_PHY_N(0x00F) /* Built-in self test status 1 */ 23 24 #define B43_NPHY_C1_DESPWR B43_PHY_N(0x018) /* Core 1 desired power */ 25 #define B43_NPHY_C1_CCK_DESPWR B43_PHY_N(0x019) /* Core 1 CCK desired power */ 26 #define B43_NPHY_C1_BCLIPBKOFF B43_PHY_N(0x01A) /* Core 1 barely clip backoff */ 27 #define B43_NPHY_C1_CCK_BCLIPBKOFF B43_PHY_N(0x01B) /* Core 1 CCK barely clip backoff */ 28 #define B43_NPHY_C1_CGAINI B43_PHY_N(0x01C) /* Core 1 compute gain info */ 29 #define B43_NPHY_C1_CGAINI_GAINBKOFF 0x001F /* Gain backoff */ 30 #define B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT 0 31 #define B43_NPHY_C1_CGAINI_CLIPGBKOFF 0x03E0 /* Clip gain backoff */ 32 #define B43_NPHY_C1_CGAINI_CLIPGBKOFF_SHIFT 5 33 #define B43_NPHY_C1_CGAINI_GAINSTEP 0x1C00 /* Gain step */ 34 #define B43_NPHY_C1_CGAINI_GAINSTEP_SHIFT 10 35 #define B43_NPHY_C1_CGAINI_CL2DETECT 0x2000 /* Clip 2 detect mask */ 36 #define B43_NPHY_C1_CCK_CGAINI B43_PHY_N(0x01D) /* Core 1 CCK compute gain info */ 37 #define B43_NPHY_C1_CCK_CGAINI_GAINBKOFF 0x001F /* Gain backoff */ 38 #define B43_NPHY_C1_CCK_CGAINI_CLIPGBKOFF 0x01E0 /* CCK barely clip gain backoff */ 39 #define B43_NPHY_C1_MINMAX_GAIN B43_PHY_N(0x01E) /* Core 1 min/max gain */ 40 #define B43_NPHY_C1_MINGAIN 0x00FF /* Minimum gain */ 41 #define B43_NPHY_C1_MINGAIN_SHIFT 0 42 #define B43_NPHY_C1_MAXGAIN 0xFF00 /* Maximum gain */ 43 #define B43_NPHY_C1_MAXGAIN_SHIFT 8 44 #define B43_NPHY_C1_CCK_MINMAX_GAIN B43_PHY_N(0x01F) /* Core 1 CCK min/max gain */ 45 #define B43_NPHY_C1_CCK_MINGAIN 0x00FF /* Minimum gain */ 46 #define B43_NPHY_C1_CCK_MINGAIN_SHIFT 0 47 #define B43_NPHY_C1_CCK_MAXGAIN 0xFF00 /* Maximum gain */ 48 #define B43_NPHY_C1_CCK_MAXGAIN_SHIFT 8 49 #define B43_NPHY_C1_INITGAIN B43_PHY_N(0x020) /* Core 1 initial gain code */ 50 #define B43_NPHY_C1_INITGAIN_EXTLNA 0x0001 /* External LNA index */ 51 #define B43_NPHY_C1_INITGAIN_LNA 0x0006 /* LNA index */ 52 #define B43_NPHY_C1_INITGAIN_LNAIDX_SHIFT 1 53 #define B43_NPHY_C1_INITGAIN_HPVGA1 0x0078 /* HPVGA1 index */ 54 #define B43_NPHY_C1_INITGAIN_HPVGA1_SHIFT 3 55 #define B43_NPHY_C1_INITGAIN_HPVGA2 0x0F80 /* HPVGA2 index */ 56 #define B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT 7 57 #define B43_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */ 58 #define B43_NPHY_C1_INITGAIN_TRTX 0x2000 /* TR TX index */ 59 #define B43_NPHY_REV3_C1_INITGAIN_A B43_PHY_N(0x020) 60 #define B43_NPHY_C1_CLIP1_HIGAIN B43_PHY_N(0x021) /* Core 1 clip1 high gain code */ 61 #define B43_NPHY_REV3_C1_INITGAIN_B B43_PHY_N(0x021) 62 #define B43_NPHY_C1_CLIP1_MEDGAIN B43_PHY_N(0x022) /* Core 1 clip1 medium gain code */ 63 #define B43_NPHY_REV3_C1_CLIP_HIGAIN_A B43_PHY_N(0x022) 64 #define B43_NPHY_C1_CLIP1_LOGAIN B43_PHY_N(0x023) /* Core 1 clip1 low gain code */ 65 #define B43_NPHY_REV3_C1_CLIP_HIGAIN_B B43_PHY_N(0x023) 66 #define B43_NPHY_C1_CLIP2_GAIN B43_PHY_N(0x024) /* Core 1 clip2 gain code */ 67 #define B43_NPHY_REV3_C1_CLIP_MEDGAIN_A B43_PHY_N(0x024) 68 #define B43_NPHY_C1_FILTERGAIN B43_PHY_N(0x025) /* Core 1 filter gain */ 69 #define B43_NPHY_C1_LPF_QHPF_BW B43_PHY_N(0x026) /* Core 1 LPF Q HP F bandwidth */ 70 #define B43_NPHY_C1_CLIPWBTHRES B43_PHY_N(0x027) /* Core 1 clip wideband threshold */ 71 #define B43_NPHY_C1_CLIPWBTHRES_CLIP2 0x003F /* Clip 2 */ 72 #define B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT 0 73 #define B43_NPHY_C1_CLIPWBTHRES_CLIP1 0x0FC0 /* Clip 1 */ 74 #define B43_NPHY_C1_CLIPWBTHRES_CLIP1_SHIFT 6 75 #define B43_NPHY_C1_W1THRES B43_PHY_N(0x028) /* Core 1 W1 threshold */ 76 #define B43_NPHY_C1_EDTHRES B43_PHY_N(0x029) /* Core 1 ED threshold */ 77 #define B43_NPHY_C1_SMSIGTHRES B43_PHY_N(0x02A) /* Core 1 small sig threshold */ 78 #define B43_NPHY_C1_NBCLIPTHRES B43_PHY_N(0x02B) /* Core 1 NB clip threshold */ 79 #define B43_NPHY_C1_CLIP1THRES B43_PHY_N(0x02C) /* Core 1 clip1 threshold */ 80 #define B43_NPHY_C1_CLIP2THRES B43_PHY_N(0x02D) /* Core 1 clip2 threshold */ 81 82 #define B43_NPHY_C2_DESPWR B43_PHY_N(0x02E) /* Core 2 desired power */ 83 #define B43_NPHY_C2_CCK_DESPWR B43_PHY_N(0x02F) /* Core 2 CCK desired power */ 84 #define B43_NPHY_C2_BCLIPBKOFF B43_PHY_N(0x030) /* Core 2 barely clip backoff */ 85 #define B43_NPHY_C2_CCK_BCLIPBKOFF B43_PHY_N(0x031) /* Core 2 CCK barely clip backoff */ 86 #define B43_NPHY_C2_CGAINI B43_PHY_N(0x032) /* Core 2 compute gain info */ 87 #define B43_NPHY_C2_CGAINI_GAINBKOFF 0x001F /* Gain backoff */ 88 #define B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT 0 89 #define B43_NPHY_C2_CGAINI_CLIPGBKOFF 0x03E0 /* Clip gain backoff */ 90 #define B43_NPHY_C2_CGAINI_CLIPGBKOFF_SHIFT 5 91 #define B43_NPHY_C2_CGAINI_GAINSTEP 0x1C00 /* Gain step */ 92 #define B43_NPHY_C2_CGAINI_GAINSTEP_SHIFT 10 93 #define B43_NPHY_C2_CGAINI_CL2DETECT 0x2000 /* Clip 2 detect mask */ 94 #define B43_NPHY_C2_CCK_CGAINI B43_PHY_N(0x033) /* Core 2 CCK compute gain info */ 95 #define B43_NPHY_C2_CCK_CGAINI_GAINBKOFF 0x001F /* Gain backoff */ 96 #define B43_NPHY_C2_CCK_CGAINI_CLIPGBKOFF 0x01E0 /* CCK barely clip gain backoff */ 97 #define B43_NPHY_C2_MINMAX_GAIN B43_PHY_N(0x034) /* Core 2 min/max gain */ 98 #define B43_NPHY_C2_MINGAIN 0x00FF /* Minimum gain */ 99 #define B43_NPHY_C2_MINGAIN_SHIFT 0 100 #define B43_NPHY_C2_MAXGAIN 0xFF00 /* Maximum gain */ 101 #define B43_NPHY_C2_MAXGAIN_SHIFT 8 102 #define B43_NPHY_C2_CCK_MINMAX_GAIN B43_PHY_N(0x035) /* Core 2 CCK min/max gain */ 103 #define B43_NPHY_C2_CCK_MINGAIN 0x00FF /* Minimum gain */ 104 #define B43_NPHY_C2_CCK_MINGAIN_SHIFT 0 105 #define B43_NPHY_C2_CCK_MAXGAIN 0xFF00 /* Maximum gain */ 106 #define B43_NPHY_C2_CCK_MAXGAIN_SHIFT 8 107 #define B43_NPHY_C2_INITGAIN B43_PHY_N(0x036) /* Core 2 initial gain code */ 108 #define B43_NPHY_C2_INITGAIN_EXTLNA 0x0001 /* External LNA index */ 109 #define B43_NPHY_C2_INITGAIN_LNA 0x0006 /* LNA index */ 110 #define B43_NPHY_C2_INITGAIN_LNAIDX_SHIFT 1 111 #define B43_NPHY_C2_INITGAIN_HPVGA1 0x0078 /* HPVGA1 index */ 112 #define B43_NPHY_C2_INITGAIN_HPVGA1_SHIFT 3 113 #define B43_NPHY_C2_INITGAIN_HPVGA2 0x0F80 /* HPVGA2 index */ 114 #define B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT 7 115 #define B43_NPHY_C2_INITGAIN_TRRX 0x1000 /* TR RX index */ 116 #define B43_NPHY_C2_INITGAIN_TRTX 0x2000 /* TR TX index */ 117 #define B43_NPHY_REV3_C1_CLIP_MEDGAIN_B B43_PHY_N(0x036) 118 #define B43_NPHY_C2_CLIP1_HIGAIN B43_PHY_N(0x037) /* Core 2 clip1 high gain code */ 119 #define B43_NPHY_REV3_C1_CLIP_LOGAIN_A B43_PHY_N(0x037) 120 #define B43_NPHY_C2_CLIP1_MEDGAIN B43_PHY_N(0x038) /* Core 2 clip1 medium gain code */ 121 #define B43_NPHY_REV3_C1_CLIP_LOGAIN_B B43_PHY_N(0x038) 122 #define B43_NPHY_C2_CLIP1_LOGAIN B43_PHY_N(0x039) /* Core 2 clip1 low gain code */ 123 #define B43_NPHY_REV3_C1_CLIP2_GAIN_A B43_PHY_N(0x039) 124 #define B43_NPHY_C2_CLIP2_GAIN B43_PHY_N(0x03A) /* Core 2 clip2 gain code */ 125 #define B43_NPHY_REV3_C1_CLIP2_GAIN_B B43_PHY_N(0x03A) 126 #define B43_NPHY_C2_FILTERGAIN B43_PHY_N(0x03B) /* Core 2 filter gain */ 127 #define B43_NPHY_C2_LPF_QHPF_BW B43_PHY_N(0x03C) /* Core 2 LPF Q HP F bandwidth */ 128 #define B43_NPHY_C2_CLIPWBTHRES B43_PHY_N(0x03D) /* Core 2 clip wideband threshold */ 129 #define B43_NPHY_C2_CLIPWBTHRES_CLIP2 0x003F /* Clip 2 */ 130 #define B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT 0 131 #define B43_NPHY_C2_CLIPWBTHRES_CLIP1 0x0FC0 /* Clip 1 */ 132 #define B43_NPHY_C2_CLIPWBTHRES_CLIP1_SHIFT 6 133 #define B43_NPHY_C2_W1THRES B43_PHY_N(0x03E) /* Core 2 W1 threshold */ 134 #define B43_NPHY_C2_EDTHRES B43_PHY_N(0x03F) /* Core 2 ED threshold */ 135 #define B43_NPHY_C2_SMSIGTHRES B43_PHY_N(0x040) /* Core 2 small sig threshold */ 136 #define B43_NPHY_C2_NBCLIPTHRES B43_PHY_N(0x041) /* Core 2 NB clip threshold */ 137 #define B43_NPHY_C2_CLIP1THRES B43_PHY_N(0x042) /* Core 2 clip1 threshold */ 138 #define B43_NPHY_C2_CLIP2THRES B43_PHY_N(0x043) /* Core 2 clip2 threshold */ 139 140 #define B43_NPHY_CRS_THRES1 B43_PHY_N(0x044) /* CRS threshold 1 */ 141 #define B43_NPHY_CRS_THRES2 B43_PHY_N(0x045) /* CRS threshold 2 */ 142 #define B43_NPHY_CRS_THRES3 B43_PHY_N(0x046) /* CRS threshold 3 */ 143 #define B43_NPHY_CRSCTL B43_PHY_N(0x047) /* CRS control */ 144 #define B43_NPHY_DCFADDR B43_PHY_N(0x048) /* DC filter address */ 145 #define B43_NPHY_RXF20_NUM0 B43_PHY_N(0x049) /* RX filter 20 numerator 0 */ 146 #define B43_NPHY_RXF20_NUM1 B43_PHY_N(0x04A) /* RX filter 20 numerator 1 */ 147 #define B43_NPHY_RXF20_NUM2 B43_PHY_N(0x04B) /* RX filter 20 numerator 2 */ 148 #define B43_NPHY_RXF20_DENOM0 B43_PHY_N(0x04C) /* RX filter 20 denominator 0 */ 149 #define B43_NPHY_RXF20_DENOM1 B43_PHY_N(0x04D) /* RX filter 20 denominator 1 */ 150 #define B43_NPHY_RXF20_NUM10 B43_PHY_N(0x04E) /* RX filter 20 numerator 10 */ 151 #define B43_NPHY_RXF20_NUM11 B43_PHY_N(0x04F) /* RX filter 20 numerator 11 */ 152 #define B43_NPHY_RXF20_NUM12 B43_PHY_N(0x050) /* RX filter 20 numerator 12 */ 153 #define B43_NPHY_RXF20_DENOM10 B43_PHY_N(0x051) /* RX filter 20 denominator 10 */ 154 #define B43_NPHY_RXF20_DENOM11 B43_PHY_N(0x052) /* RX filter 20 denominator 11 */ 155 #define B43_NPHY_RXF40_NUM0 B43_PHY_N(0x053) /* RX filter 40 numerator 0 */ 156 #define B43_NPHY_RXF40_NUM1 B43_PHY_N(0x054) /* RX filter 40 numerator 1 */ 157 #define B43_NPHY_RXF40_NUM2 B43_PHY_N(0x055) /* RX filter 40 numerator 2 */ 158 #define B43_NPHY_RXF40_DENOM0 B43_PHY_N(0x056) /* RX filter 40 denominator 0 */ 159 #define B43_NPHY_RXF40_DENOM1 B43_PHY_N(0x057) /* RX filter 40 denominator 1 */ 160 #define B43_NPHY_RXF40_NUM10 B43_PHY_N(0x058) /* RX filter 40 numerator 10 */ 161 #define B43_NPHY_RXF40_NUM11 B43_PHY_N(0x059) /* RX filter 40 numerator 11 */ 162 #define B43_NPHY_RXF40_NUM12 B43_PHY_N(0x05A) /* RX filter 40 numerator 12 */ 163 #define B43_NPHY_RXF40_DENOM10 B43_PHY_N(0x05B) /* RX filter 40 denominator 10 */ 164 #define B43_NPHY_RXF40_DENOM11 B43_PHY_N(0x05C) /* RX filter 40 denominator 11 */ 165 #define B43_NPHY_PPROC_RSTLEN B43_PHY_N(0x060) /* Packet processing reset length */ 166 #define B43_NPHY_INITCARR_DLEN B43_PHY_N(0x061) /* Initial carrier detection length */ 167 #define B43_NPHY_CLIP1CARR_DLEN B43_PHY_N(0x062) /* Clip1 carrier detection length */ 168 #define B43_NPHY_CLIP2CARR_DLEN B43_PHY_N(0x063) /* Clip2 carrier detection length */ 169 #define B43_NPHY_INITGAIN_SLEN B43_PHY_N(0x064) /* Initial gain settle length */ 170 #define B43_NPHY_CLIP1GAIN_SLEN B43_PHY_N(0x065) /* Clip1 gain settle length */ 171 #define B43_NPHY_CLIP2GAIN_SLEN B43_PHY_N(0x066) /* Clip2 gain settle length */ 172 #define B43_NPHY_PACKGAIN_SLEN B43_PHY_N(0x067) /* Packet gain settle length */ 173 #define B43_NPHY_CARRSRC_TLEN B43_PHY_N(0x068) /* Carrier search timeout length */ 174 #define B43_NPHY_TISRC_TLEN B43_PHY_N(0x069) /* Timing search timeout length */ 175 #define B43_NPHY_ENDROP_TLEN B43_PHY_N(0x06A) /* Energy drop timeout length */ 176 #define B43_NPHY_CLIP1_NBDWELL_LEN B43_PHY_N(0x06B) /* Clip1 NB dwell length */ 177 #define B43_NPHY_CLIP2_NBDWELL_LEN B43_PHY_N(0x06C) /* Clip2 NB dwell length */ 178 #define B43_NPHY_W1CLIP1_DWELL_LEN B43_PHY_N(0x06D) /* W1 clip1 dwell length */ 179 #define B43_NPHY_W1CLIP2_DWELL_LEN B43_PHY_N(0x06E) /* W1 clip2 dwell length */ 180 #define B43_NPHY_W2CLIP1_DWELL_LEN B43_PHY_N(0x06F) /* W2 clip1 dwell length */ 181 #define B43_NPHY_PLOAD_CSENSE_EXTLEN B43_PHY_N(0x070) /* Payload carrier sense extension length */ 182 #define B43_NPHY_EDROP_CSENSE_EXTLEN B43_PHY_N(0x071) /* Energy drop carrier sense extension length */ 183 #define B43_NPHY_TABLE_ADDR B43_PHY_N(0x072) /* Table address */ 184 #define B43_NPHY_TABLE_DATALO B43_PHY_N(0x073) /* Table data low */ 185 #define B43_NPHY_TABLE_DATAHI B43_PHY_N(0x074) /* Table data high */ 186 #define B43_NPHY_WWISE_LENIDX B43_PHY_N(0x075) /* WWiSE length index */ 187 #define B43_NPHY_TGNSYNC_LENIDX B43_PHY_N(0x076) /* TGNsync length index */ 188 #define B43_NPHY_TXMACIF_HOLDOFF B43_PHY_N(0x077) /* TX MAC IF Hold off */ 189 #define B43_NPHY_RFCTL_CMD B43_PHY_N(0x078) /* RF control (command) */ 190 #define B43_NPHY_RFCTL_CMD_START 0x0001 /* Start sequence */ 191 #define B43_NPHY_RFCTL_CMD_RXTX 0x0002 /* RX/TX */ 192 #define B43_NPHY_RFCTL_CMD_CORESEL 0x0038 /* Core select */ 193 #define B43_NPHY_RFCTL_CMD_CORESEL_SHIFT 3 194 #define B43_NPHY_RFCTL_CMD_PORFORCE 0x0040 /* POR force */ 195 #define B43_NPHY_RFCTL_CMD_OEPORFORCE 0x0080 /* OE POR force */ 196 #define B43_NPHY_RFCTL_CMD_RXEN 0x0100 /* RX enable */ 197 #define B43_NPHY_RFCTL_CMD_TXEN 0x0200 /* TX enable */ 198 #define B43_NPHY_RFCTL_CMD_CHIP0PU 0x0400 /* Chip0 PU */ 199 #define B43_NPHY_RFCTL_CMD_EN 0x0800 /* Radio enabled */ 200 #define B43_NPHY_RFCTL_CMD_SEQENCORE 0xF000 /* Seq en core */ 201 #define B43_NPHY_RFCTL_CMD_SEQENCORE_SHIFT 12 202 #define B43_NPHY_RFCTL_RSSIO1 B43_PHY_N(0x07A) /* RF control (RSSI others 1) */ 203 #define B43_NPHY_RFCTL_RSSIO1_RXPD 0x0001 /* RX PD */ 204 #define B43_NPHY_RFCTL_RSSIO1_TXPD 0x0002 /* TX PD */ 205 #define B43_NPHY_RFCTL_RSSIO1_PAPD 0x0004 /* PA PD */ 206 #define B43_NPHY_RFCTL_RSSIO1_RSSICTL 0x0030 /* RSSI control */ 207 #define B43_NPHY_RFCTL_RSSIO1_LPFBW 0x00C0 /* LPF bandwidth */ 208 #define B43_NPHY_RFCTL_RSSIO1_HPFBWHI 0x0100 /* HPF bandwidth high */ 209 #define B43_NPHY_RFCTL_RSSIO1_HIQDISCO 0x0200 /* HIQ dis core */ 210 #define B43_NPHY_RFCTL_RXG1 B43_PHY_N(0x07B) /* RF control (RX gain 1) */ 211 #define B43_NPHY_RFCTL_TXG1 B43_PHY_N(0x07C) /* RF control (TX gain 1) */ 212 #define B43_NPHY_RFCTL_RSSIO2 B43_PHY_N(0x07D) /* RF control (RSSI others 2) */ 213 #define B43_NPHY_RFCTL_RSSIO2_RXPD 0x0001 /* RX PD */ 214 #define B43_NPHY_RFCTL_RSSIO2_TXPD 0x0002 /* TX PD */ 215 #define B43_NPHY_RFCTL_RSSIO2_PAPD 0x0004 /* PA PD */ 216 #define B43_NPHY_RFCTL_RSSIO2_RSSICTL 0x0030 /* RSSI control */ 217 #define B43_NPHY_RFCTL_RSSIO2_LPFBW 0x00C0 /* LPF bandwidth */ 218 #define B43_NPHY_RFCTL_RSSIO2_HPFBWHI 0x0100 /* HPF bandwidth high */ 219 #define B43_NPHY_RFCTL_RSSIO2_HIQDISCO 0x0200 /* HIQ dis core */ 220 #define B43_NPHY_RFCTL_RXG2 B43_PHY_N(0x07E) /* RF control (RX gain 2) */ 221 #define B43_NPHY_RFCTL_TXG2 B43_PHY_N(0x07F) /* RF control (TX gain 2) */ 222 #define B43_NPHY_RFCTL_RSSIO3 B43_PHY_N(0x080) /* RF control (RSSI others 3) */ 223 #define B43_NPHY_RFCTL_RSSIO3_RXPD 0x0001 /* RX PD */ 224 #define B43_NPHY_RFCTL_RSSIO3_TXPD 0x0002 /* TX PD */ 225 #define B43_NPHY_RFCTL_RSSIO3_PAPD 0x0004 /* PA PD */ 226 #define B43_NPHY_RFCTL_RSSIO3_RSSICTL 0x0030 /* RSSI control */ 227 #define B43_NPHY_RFCTL_RSSIO3_LPFBW 0x00C0 /* LPF bandwidth */ 228 #define B43_NPHY_RFCTL_RSSIO3_HPFBWHI 0x0100 /* HPF bandwidth high */ 229 #define B43_NPHY_RFCTL_RSSIO3_HIQDISCO 0x0200 /* HIQ dis core */ 230 #define B43_NPHY_RFCTL_RXG3 B43_PHY_N(0x081) /* RF control (RX gain 3) */ 231 #define B43_NPHY_RFCTL_TXG3 B43_PHY_N(0x082) /* RF control (TX gain 3) */ 232 #define B43_NPHY_RFCTL_RSSIO4 B43_PHY_N(0x083) /* RF control (RSSI others 4) */ 233 #define B43_NPHY_RFCTL_RSSIO4_RXPD 0x0001 /* RX PD */ 234 #define B43_NPHY_RFCTL_RSSIO4_TXPD 0x0002 /* TX PD */ 235 #define B43_NPHY_RFCTL_RSSIO4_PAPD 0x0004 /* PA PD */ 236 #define B43_NPHY_RFCTL_RSSIO4_RSSICTL 0x0030 /* RSSI control */ 237 #define B43_NPHY_RFCTL_RSSIO4_LPFBW 0x00C0 /* LPF bandwidth */ 238 #define B43_NPHY_RFCTL_RSSIO4_HPFBWHI 0x0100 /* HPF bandwidth high */ 239 #define B43_NPHY_RFCTL_RSSIO4_HIQDISCO 0x0200 /* HIQ dis core */ 240 #define B43_NPHY_RFCTL_RXG4 B43_PHY_N(0x084) /* RF control (RX gain 4) */ 241 #define B43_NPHY_RFCTL_TXG4 B43_PHY_N(0x085) /* RF control (TX gain 4) */ 242 #define B43_NPHY_C1_TXIQ_COMP_OFF B43_PHY_N(0x087) /* Core 1 TX I/Q comp offset */ 243 #define B43_NPHY_C2_TXIQ_COMP_OFF B43_PHY_N(0x088) /* Core 2 TX I/Q comp offset */ 244 #define B43_NPHY_C1_TXCTL B43_PHY_N(0x08B) /* Core 1 TX control */ 245 #define B43_NPHY_C2_TXCTL B43_PHY_N(0x08C) /* Core 2 TX control */ 246 #define B43_NPHY_AFECTL_OVER1 B43_PHY_N(0x08F) /* AFE control override 1 */ 247 #define B43_NPHY_SCRAM_SIGCTL B43_PHY_N(0x090) /* Scram signal control */ 248 #define B43_NPHY_SCRAM_SIGCTL_INITST 0x007F /* Initial state value */ 249 #define B43_NPHY_SCRAM_SIGCTL_INITST_SHIFT 0 250 #define B43_NPHY_SCRAM_SIGCTL_SCM 0x0080 /* Scram control mode */ 251 #define B43_NPHY_SCRAM_SIGCTL_SICE 0x0100 /* Scram index control enable */ 252 #define B43_NPHY_SCRAM_SIGCTL_START 0xFE00 /* Scram start bit */ 253 #define B43_NPHY_SCRAM_SIGCTL_START_SHIFT 9 254 #define B43_NPHY_RFCTL_INTC1 B43_PHY_N(0x091) /* RF control (intc 1) */ 255 #define B43_NPHY_RFCTL_INTC2 B43_PHY_N(0x092) /* RF control (intc 2) */ 256 #define B43_NPHY_RFCTL_INTC3 B43_PHY_N(0x093) /* RF control (intc 3) */ 257 #define B43_NPHY_RFCTL_INTC4 B43_PHY_N(0x094) /* RF control (intc 4) */ 258 #define B43_NPHY_NRDTO_WWISE B43_PHY_N(0x095) /* # datatones WWiSE */ 259 #define B43_NPHY_NRDTO_TGNSYNC B43_PHY_N(0x096) /* # datatones TGNsync */ 260 #define B43_NPHY_SIGFMOD_WWISE B43_PHY_N(0x097) /* Signal field mod WWiSE */ 261 #define B43_NPHY_LEG_SIGFMOD_11N B43_PHY_N(0x098) /* Legacy signal field mod 11n */ 262 #define B43_NPHY_HT_SIGFMOD_11N B43_PHY_N(0x099) /* HT signal field mod 11n */ 263 #define B43_NPHY_C1_RXIQ_COMPA0 B43_PHY_N(0x09A) /* Core 1 RX I/Q comp A0 */ 264 #define B43_NPHY_C1_RXIQ_COMPB0 B43_PHY_N(0x09B) /* Core 1 RX I/Q comp B0 */ 265 #define B43_NPHY_C2_RXIQ_COMPA1 B43_PHY_N(0x09C) /* Core 2 RX I/Q comp A1 */ 266 #define B43_NPHY_C2_RXIQ_COMPB1 B43_PHY_N(0x09D) /* Core 2 RX I/Q comp B1 */ 267 #define B43_NPHY_RXCTL B43_PHY_N(0x0A0) /* RX control */ 268 #define B43_NPHY_RXCTL_BSELU20 0x0010 /* Band select upper 20 */ 269 #define B43_NPHY_RXCTL_RIFSEN 0x0080 /* RIFS enable */ 270 #define B43_NPHY_RFSEQMODE B43_PHY_N(0x0A1) /* RF seq mode */ 271 #define B43_NPHY_RFSEQMODE_CAOVER 0x0001 /* Core active override */ 272 #define B43_NPHY_RFSEQMODE_TROVER 0x0002 /* Trigger override */ 273 #define B43_NPHY_RFSEQCA B43_PHY_N(0x0A2) /* RF seq core active */ 274 #define B43_NPHY_RFSEQCA_TXEN 0x000F /* TX enable */ 275 #define B43_NPHY_RFSEQCA_TXEN_SHIFT 0 276 #define B43_NPHY_RFSEQCA_RXEN 0x00F0 /* RX enable */ 277 #define B43_NPHY_RFSEQCA_RXEN_SHIFT 4 278 #define B43_NPHY_RFSEQCA_TXDIS 0x0F00 /* TX disable */ 279 #define B43_NPHY_RFSEQCA_TXDIS_SHIFT 8 280 #define B43_NPHY_RFSEQCA_RXDIS 0xF000 /* RX disable */ 281 #define B43_NPHY_RFSEQCA_RXDIS_SHIFT 12 282 #define B43_NPHY_RFSEQTR B43_PHY_N(0x0A3) /* RF seq trigger */ 283 #define B43_NPHY_RFSEQTR_RX2TX 0x0001 /* RX2TX */ 284 #define B43_NPHY_RFSEQTR_TX2RX 0x0002 /* TX2RX */ 285 #define B43_NPHY_RFSEQTR_UPGH 0x0004 /* Update gain H */ 286 #define B43_NPHY_RFSEQTR_UPGL 0x0008 /* Update gain L */ 287 #define B43_NPHY_RFSEQTR_UPGU 0x0010 /* Update gain U */ 288 #define B43_NPHY_RFSEQTR_RST2RX 0x0020 /* Reset to RX */ 289 #define B43_NPHY_RFSEQST B43_PHY_N(0x0A4) /* RF seq status. Values same as trigger. */ 290 #define B43_NPHY_AFECTL_OVER B43_PHY_N(0x0A5) /* AFE control override */ 291 #define B43_NPHY_AFECTL_C1 B43_PHY_N(0x0A6) /* AFE control core 1 */ 292 #define B43_NPHY_AFECTL_C2 B43_PHY_N(0x0A7) /* AFE control core 2 */ 293 #define B43_NPHY_AFECTL_C3 B43_PHY_N(0x0A8) /* AFE control core 3 */ 294 #define B43_NPHY_AFECTL_C4 B43_PHY_N(0x0A9) /* AFE control core 4 */ 295 #define B43_NPHY_AFECTL_DACGAIN1 B43_PHY_N(0x0AA) /* AFE control DAC gain 1 */ 296 #define B43_NPHY_AFECTL_DACGAIN2 B43_PHY_N(0x0AB) /* AFE control DAC gain 2 */ 297 #define B43_NPHY_AFECTL_DACGAIN3 B43_PHY_N(0x0AC) /* AFE control DAC gain 3 */ 298 #define B43_NPHY_AFECTL_DACGAIN4 B43_PHY_N(0x0AD) /* AFE control DAC gain 4 */ 299 #define B43_NPHY_STR_ADDR1 B43_PHY_N(0x0AE) /* STR address 1 */ 300 #define B43_NPHY_STR_ADDR2 B43_PHY_N(0x0AF) /* STR address 2 */ 301 #define B43_NPHY_CLASSCTL B43_PHY_N(0x0B0) /* Classifier control */ 302 #define B43_NPHY_CLASSCTL_CCKEN 0x0001 /* CCK enable */ 303 #define B43_NPHY_CLASSCTL_OFDMEN 0x0002 /* OFDM enable */ 304 #define B43_NPHY_CLASSCTL_WAITEDEN 0x0004 /* Waited enable */ 305 #define B43_NPHY_IQFLIP B43_PHY_N(0x0B1) /* I/Q flip */ 306 #define B43_NPHY_IQFLIP_ADC1 0x0001 /* ADC1 */ 307 #define B43_NPHY_IQFLIP_ADC2 0x0010 /* ADC2 */ 308 #define B43_NPHY_SISO_SNR_THRES B43_PHY_N(0x0B2) /* SISO SNR threshold */ 309 #define B43_NPHY_SIGMA_N_MULT B43_PHY_N(0x0B3) /* Sigma N multiplier */ 310 #define B43_NPHY_TXMACDELAY B43_PHY_N(0x0B4) /* TX MAC delay */ 311 #define B43_NPHY_TXFRAMEDELAY B43_PHY_N(0x0B5) /* TX frame delay */ 312 #define B43_NPHY_MLPARM B43_PHY_N(0x0B6) /* ML parameters */ 313 #define B43_NPHY_MLCTL B43_PHY_N(0x0B7) /* ML control */ 314 #define B43_NPHY_WWISE_20NCYCDAT B43_PHY_N(0x0B8) /* WWiSE 20 N cyc data */ 315 #define B43_NPHY_WWISE_40NCYCDAT B43_PHY_N(0x0B9) /* WWiSE 40 N cyc data */ 316 #define B43_NPHY_TGNSYNC_20NCYCDAT B43_PHY_N(0x0BA) /* TGNsync 20 N cyc data */ 317 #define B43_NPHY_TGNSYNC_40NCYCDAT B43_PHY_N(0x0BB) /* TGNsync 40 N cyc data */ 318 #define B43_NPHY_INITSWIZP B43_PHY_N(0x0BC) /* Initial swizzle pattern */ 319 #define B43_NPHY_TXTAILCNT B43_PHY_N(0x0BD) /* TX tail count value */ 320 #define B43_NPHY_BPHY_CTL1 B43_PHY_N(0x0BE) /* B PHY control 1 */ 321 #define B43_NPHY_BPHY_CTL2 B43_PHY_N(0x0BF) /* B PHY control 2 */ 322 #define B43_NPHY_BPHY_CTL2_LUT 0x001F /* LUT index */ 323 #define B43_NPHY_BPHY_CTL2_LUT_SHIFT 0 324 #define B43_NPHY_BPHY_CTL2_MACDEL 0x7FE0 /* MAC delay */ 325 #define B43_NPHY_BPHY_CTL2_MACDEL_SHIFT 5 326 #define B43_NPHY_IQLOCAL_CMD B43_PHY_N(0x0C0) /* I/Q LO cal command */ 327 #define B43_NPHY_IQLOCAL_CMD_EN 0x8000 328 #define B43_NPHY_IQLOCAL_CMDNNUM B43_PHY_N(0x0C1) /* I/Q LO cal command N num */ 329 #define B43_NPHY_IQLOCAL_CMDGCTL B43_PHY_N(0x0C2) /* I/Q LO cal command G control */ 330 #define B43_NPHY_SAMP_CMD B43_PHY_N(0x0C3) /* Sample command */ 331 #define B43_NPHY_SAMP_CMD_STOP 0x0002 /* Stop */ 332 #define B43_NPHY_SAMP_LOOPCNT B43_PHY_N(0x0C4) /* Sample loop count */ 333 #define B43_NPHY_SAMP_WAITCNT B43_PHY_N(0x0C5) /* Sample wait count */ 334 #define B43_NPHY_SAMP_DEPCNT B43_PHY_N(0x0C6) /* Sample depth count */ 335 #define B43_NPHY_SAMP_STAT B43_PHY_N(0x0C7) /* Sample status */ 336 #define B43_NPHY_GPIO_LOOEN B43_PHY_N(0x0C8) /* GPIO low out enable */ 337 #define B43_NPHY_GPIO_HIOEN B43_PHY_N(0x0C9) /* GPIO high out enable */ 338 #define B43_NPHY_GPIO_SEL B43_PHY_N(0x0CA) /* GPIO select */ 339 #define B43_NPHY_GPIO_CLKCTL B43_PHY_N(0x0CB) /* GPIO clock control */ 340 #define B43_NPHY_TXF_20CO_AS0 B43_PHY_N(0x0CC) /* TX filter 20 coeff A stage 0 */ 341 #define B43_NPHY_TXF_20CO_AS1 B43_PHY_N(0x0CD) /* TX filter 20 coeff A stage 1 */ 342 #define B43_NPHY_TXF_20CO_AS2 B43_PHY_N(0x0CE) /* TX filter 20 coeff A stage 2 */ 343 #define B43_NPHY_TXF_20CO_B32S0 B43_PHY_N(0x0CF) /* TX filter 20 coeff B32 stage 0 */ 344 #define B43_NPHY_TXF_20CO_B1S0 B43_PHY_N(0x0D0) /* TX filter 20 coeff B1 stage 0 */ 345 #define B43_NPHY_TXF_20CO_B32S1 B43_PHY_N(0x0D1) /* TX filter 20 coeff B32 stage 1 */ 346 #define B43_NPHY_TXF_20CO_B1S1 B43_PHY_N(0x0D2) /* TX filter 20 coeff B1 stage 1 */ 347 #define B43_NPHY_TXF_20CO_B32S2 B43_PHY_N(0x0D3) /* TX filter 20 coeff B32 stage 2 */ 348 #define B43_NPHY_TXF_20CO_B1S2 B43_PHY_N(0x0D4) /* TX filter 20 coeff B1 stage 2 */ 349 #define B43_NPHY_SIGFLDTOL B43_PHY_N(0x0D5) /* Signal fld tolerance */ 350 #define B43_NPHY_TXSERFLD B43_PHY_N(0x0D6) /* TX service field */ 351 #define B43_NPHY_AFESEQ_RX2TX_PUD B43_PHY_N(0x0D7) /* AFE seq RX2TX power up/down delay */ 352 #define B43_NPHY_AFESEQ_TX2RX_PUD B43_PHY_N(0x0D8) /* AFE seq TX2RX power up/down delay */ 353 #define B43_NPHY_TGNSYNC_SCRAMI0 B43_PHY_N(0x0D9) /* TGNsync scram init 0 */ 354 #define B43_NPHY_TGNSYNC_SCRAMI1 B43_PHY_N(0x0DA) /* TGNsync scram init 1 */ 355 #define B43_NPHY_INITSWIZPATTLEG B43_PHY_N(0x0DB) /* Initial swizzle pattern leg */ 356 #define B43_NPHY_BPHY_CTL3 B43_PHY_N(0x0DC) /* B PHY control 3 */ 357 #define B43_NPHY_BPHY_CTL3_SCALE 0x00FF /* Scale */ 358 #define B43_NPHY_BPHY_CTL3_SCALE_SHIFT 0 359 #define B43_NPHY_BPHY_CTL3_FSC 0xFF00 /* Frame start count value */ 360 #define B43_NPHY_BPHY_CTL3_FSC_SHIFT 8 361 #define B43_NPHY_BPHY_CTL4 B43_PHY_N(0x0DD) /* B PHY control 4 */ 362 #define B43_NPHY_C1_TXBBMULT B43_PHY_N(0x0DE) /* Core 1 TX BB multiplier */ 363 #define B43_NPHY_C2_TXBBMULT B43_PHY_N(0x0DF) /* Core 2 TX BB multiplier */ 364 #define B43_NPHY_TXF_40CO_AS0 B43_PHY_N(0x0E1) /* TX filter 40 coeff A stage 0 */ 365 #define B43_NPHY_TXF_40CO_AS1 B43_PHY_N(0x0E2) /* TX filter 40 coeff A stage 1 */ 366 #define B43_NPHY_TXF_40CO_AS2 B43_PHY_N(0x0E3) /* TX filter 40 coeff A stage 2 */ 367 #define B43_NPHY_TXF_40CO_B32S0 B43_PHY_N(0x0E4) /* TX filter 40 coeff B32 stage 0 */ 368 #define B43_NPHY_TXF_40CO_B1S0 B43_PHY_N(0x0E5) /* TX filter 40 coeff B1 stage 0 */ 369 #define B43_NPHY_TXF_40CO_B32S1 B43_PHY_N(0x0E6) /* TX filter 40 coeff B32 stage 1 */ 370 #define B43_NPHY_TXF_40CO_B1S1 B43_PHY_N(0x0E7) /* TX filter 40 coeff B1 stage 1 */ 371 #define B43_NPHY_REV3_RFCTL_OVER0 B43_PHY_N(0x0E7) 372 #define B43_NPHY_TXF_40CO_B32S2 B43_PHY_N(0x0E8) /* TX filter 40 coeff B32 stage 2 */ 373 #define B43_NPHY_TXF_40CO_B1S2 B43_PHY_N(0x0E9) /* TX filter 40 coeff B1 stage 2 */ 374 #define B43_NPHY_BIST_STAT2 B43_PHY_N(0x0EA) /* BIST status 2 */ 375 #define B43_NPHY_BIST_STAT3 B43_PHY_N(0x0EB) /* BIST status 3 */ 376 #define B43_NPHY_RFCTL_OVER B43_PHY_N(0x0EC) /* RF control override */ 377 #define B43_NPHY_REV3_RFCTL_OVER1 B43_PHY_N(0x0EC) 378 #define B43_NPHY_MIMOCFG B43_PHY_N(0x0ED) /* MIMO config */ 379 #define B43_NPHY_MIMOCFG_GFMIX 0x0004 /* Greenfield or mixed mode */ 380 #define B43_NPHY_MIMOCFG_AUTO 0x0100 /* Greenfield/mixed mode auto */ 381 #define B43_NPHY_RADAR_BLNKCTL B43_PHY_N(0x0EE) /* Radar blank control */ 382 #define B43_NPHY_A0RADAR_FIFOCTL B43_PHY_N(0x0EF) /* Antenna 0 radar FIFO control */ 383 #define B43_NPHY_A1RADAR_FIFOCTL B43_PHY_N(0x0F0) /* Antenna 1 radar FIFO control */ 384 #define B43_NPHY_A0RADAR_FIFODAT B43_PHY_N(0x0F1) /* Antenna 0 radar FIFO data */ 385 #define B43_NPHY_A1RADAR_FIFODAT B43_PHY_N(0x0F2) /* Antenna 1 radar FIFO data */ 386 #define B43_NPHY_RADAR_THRES0 B43_PHY_N(0x0F3) /* Radar threshold 0 */ 387 #define B43_NPHY_RADAR_THRES1 B43_PHY_N(0x0F4) /* Radar threshold 1 */ 388 #define B43_NPHY_RADAR_THRES0R B43_PHY_N(0x0F5) /* Radar threshold 0R */ 389 #define B43_NPHY_RADAR_THRES1R B43_PHY_N(0x0F6) /* Radar threshold 1R */ 390 #define B43_NPHY_CSEN_20IN40_DLEN B43_PHY_N(0x0F7) /* Carrier sense 20 in 40 dwell length */ 391 #define B43_NPHY_RFCTL_LUT_TRSW_LO1 B43_PHY_N(0x0F8) /* RF control LUT TRSW lower 1 */ 392 #define B43_NPHY_RFCTL_LUT_TRSW_UP1 B43_PHY_N(0x0F9) /* RF control LUT TRSW upper 1 */ 393 #define B43_NPHY_RFCTL_LUT_TRSW_LO2 B43_PHY_N(0x0FA) /* RF control LUT TRSW lower 2 */ 394 #define B43_NPHY_RFCTL_LUT_TRSW_UP2 B43_PHY_N(0x0FB) /* RF control LUT TRSW upper 2 */ 395 #define B43_NPHY_RFCTL_LUT_TRSW_LO3 B43_PHY_N(0x0FC) /* RF control LUT TRSW lower 3 */ 396 #define B43_NPHY_RFCTL_LUT_TRSW_UP3 B43_PHY_N(0x0FD) /* RF control LUT TRSW upper 3 */ 397 #define B43_NPHY_RFCTL_LUT_TRSW_LO4 B43_PHY_N(0x0FE) /* RF control LUT TRSW lower 4 */ 398 #define B43_NPHY_RFCTL_LUT_TRSW_UP4 B43_PHY_N(0x0FF) /* RF control LUT TRSW upper 4 */ 399 #define B43_NPHY_RFCTL_LUT_LNAPA1 B43_PHY_N(0x100) /* RF control LUT LNA PA 1 */ 400 #define B43_NPHY_RFCTL_LUT_LNAPA2 B43_PHY_N(0x101) /* RF control LUT LNA PA 2 */ 401 #define B43_NPHY_RFCTL_LUT_LNAPA3 B43_PHY_N(0x102) /* RF control LUT LNA PA 3 */ 402 #define B43_NPHY_RFCTL_LUT_LNAPA4 B43_PHY_N(0x103) /* RF control LUT LNA PA 4 */ 403 #define B43_NPHY_TGNSYNC_CRCM0 B43_PHY_N(0x104) /* TGNsync CRC mask 0 */ 404 #define B43_NPHY_TGNSYNC_CRCM1 B43_PHY_N(0x105) /* TGNsync CRC mask 1 */ 405 #define B43_NPHY_TGNSYNC_CRCM2 B43_PHY_N(0x106) /* TGNsync CRC mask 2 */ 406 #define B43_NPHY_TGNSYNC_CRCM3 B43_PHY_N(0x107) /* TGNsync CRC mask 3 */ 407 #define B43_NPHY_TGNSYNC_CRCM4 B43_PHY_N(0x108) /* TGNsync CRC mask 4 */ 408 #define B43_NPHY_CRCPOLY B43_PHY_N(0x109) /* CRC polynomial */ 409 #define B43_NPHY_SIGCNT B43_PHY_N(0x10A) /* # sig count */ 410 #define B43_NPHY_SIGSTARTBIT_CTL B43_PHY_N(0x10B) /* Sig start bit control */ 411 #define B43_NPHY_CRCPOLY_ORDER B43_PHY_N(0x10C) /* CRC polynomial order */ 412 #define B43_NPHY_RFCTL_CST0 B43_PHY_N(0x10D) /* RF control core swap table 0 */ 413 #define B43_NPHY_RFCTL_CST1 B43_PHY_N(0x10E) /* RF control core swap table 1 */ 414 #define B43_NPHY_RFCTL_CST2O B43_PHY_N(0x10F) /* RF control core swap table 2 + others */ 415 #define B43_NPHY_BPHY_CTL5 B43_PHY_N(0x111) /* B PHY control 5 */ 416 #define B43_NPHY_RFSEQ_LPFBW B43_PHY_N(0x112) /* RF seq LPF bandwidth */ 417 #define B43_NPHY_TSSIBIAS1 B43_PHY_N(0x114) /* TSSI bias val 1 */ 418 #define B43_NPHY_TSSIBIAS2 B43_PHY_N(0x115) /* TSSI bias val 2 */ 419 #define B43_NPHY_TSSIBIAS_BIAS 0x00FF /* Bias */ 420 #define B43_NPHY_TSSIBIAS_BIAS_SHIFT 0 421 #define B43_NPHY_TSSIBIAS_VAL 0xFF00 /* Value */ 422 #define B43_NPHY_TSSIBIAS_VAL_SHIFT 8 423 #define B43_NPHY_ESTPWR1 B43_PHY_N(0x118) /* Estimated power 1 */ 424 #define B43_NPHY_ESTPWR2 B43_PHY_N(0x119) /* Estimated power 2 */ 425 #define B43_NPHY_ESTPWR_PWR 0x00FF /* Estimated power */ 426 #define B43_NPHY_ESTPWR_PWR_SHIFT 0 427 #define B43_NPHY_ESTPWR_VALID 0x0100 /* Estimated power valid */ 428 #define B43_NPHY_TSSI_MAXTXFDT B43_PHY_N(0x11C) /* TSSI max TX frame delay time */ 429 #define B43_NPHY_TSSI_MAXTXFDT_VAL 0x00FF /* max TX frame delay time */ 430 #define B43_NPHY_TSSI_MAXTXFDT_VAL_SHIFT 0 431 #define B43_NPHY_TSSI_MAXTDT B43_PHY_N(0x11D) /* TSSI max TSSI delay time */ 432 #define B43_NPHY_TSSI_MAXTDT_VAL 0x00FF /* max TSSI delay time */ 433 #define B43_NPHY_TSSI_MAXTDT_VAL_SHIFT 0 434 #define B43_NPHY_ITSSI1 B43_PHY_N(0x11E) /* TSSI idle 1 */ 435 #define B43_NPHY_ITSSI2 B43_PHY_N(0x11F) /* TSSI idle 2 */ 436 #define B43_NPHY_ITSSI_VAL 0x00FF /* Idle TSSI */ 437 #define B43_NPHY_ITSSI_VAL_SHIFT 0 438 #define B43_NPHY_TSSIMODE B43_PHY_N(0x122) /* TSSI mode */ 439 #define B43_NPHY_TSSIMODE_EN 0x0001 /* TSSI enable */ 440 #define B43_NPHY_TSSIMODE_PDEN 0x0002 /* Power det enable */ 441 #define B43_NPHY_RXMACIFM B43_PHY_N(0x123) /* RX Macif mode */ 442 #define B43_NPHY_CRSIT_COCNT_LO B43_PHY_N(0x124) /* CRS idle time CRS-on count (low) */ 443 #define B43_NPHY_CRSIT_COCNT_HI B43_PHY_N(0x125) /* CRS idle time CRS-on count (high) */ 444 #define B43_NPHY_CRSIT_MTCNT_LO B43_PHY_N(0x126) /* CRS idle time measure time count (low) */ 445 #define B43_NPHY_CRSIT_MTCNT_HI B43_PHY_N(0x127) /* CRS idle time measure time count (high) */ 446 #define B43_NPHY_SAMTWC B43_PHY_N(0x128) /* Sample tail wait count */ 447 #define B43_NPHY_IQEST_CMD B43_PHY_N(0x129) /* I/Q estimate command */ 448 #define B43_NPHY_IQEST_CMD_START 0x0001 /* Start */ 449 #define B43_NPHY_IQEST_CMD_MODE 0x0002 /* Mode */ 450 #define B43_NPHY_IQEST_WT B43_PHY_N(0x12A) /* I/Q estimate wait time */ 451 #define B43_NPHY_IQEST_WT_VAL 0x00FF /* Wait time */ 452 #define B43_NPHY_IQEST_WT_VAL_SHIFT 0 453 #define B43_NPHY_IQEST_SAMCNT B43_PHY_N(0x12B) /* I/Q estimate sample count */ 454 #define B43_NPHY_IQEST_IQACC_LO0 B43_PHY_N(0x12C) /* I/Q estimate I/Q acc lo 0 */ 455 #define B43_NPHY_IQEST_IQACC_HI0 B43_PHY_N(0x12D) /* I/Q estimate I/Q acc hi 0 */ 456 #define B43_NPHY_IQEST_IPACC_LO0 B43_PHY_N(0x12E) /* I/Q estimate I power acc lo 0 */ 457 #define B43_NPHY_IQEST_IPACC_HI0 B43_PHY_N(0x12F) /* I/Q estimate I power acc hi 0 */ 458 #define B43_NPHY_IQEST_QPACC_LO0 B43_PHY_N(0x130) /* I/Q estimate Q power acc lo 0 */ 459 #define B43_NPHY_IQEST_QPACC_HI0 B43_PHY_N(0x131) /* I/Q estimate Q power acc hi 0 */ 460 #define B43_NPHY_IQEST_IQACC_LO1 B43_PHY_N(0x134) /* I/Q estimate I/Q acc lo 1 */ 461 #define B43_NPHY_IQEST_IQACC_HI1 B43_PHY_N(0x135) /* I/Q estimate I/Q acc hi 1 */ 462 #define B43_NPHY_IQEST_IPACC_LO1 B43_PHY_N(0x136) /* I/Q estimate I power acc lo 1 */ 463 #define B43_NPHY_IQEST_IPACC_HI1 B43_PHY_N(0x137) /* I/Q estimate I power acc hi 1 */ 464 #define B43_NPHY_IQEST_QPACC_LO1 B43_PHY_N(0x138) /* I/Q estimate Q power acc lo 1 */ 465 #define B43_NPHY_IQEST_QPACC_HI1 B43_PHY_N(0x139) /* I/Q estimate Q power acc hi 1 */ 466 #define B43_NPHY_MIMO_CRSTXEXT B43_PHY_N(0x13A) /* MIMO PHY CRS TX extension */ 467 #define B43_NPHY_PWRDET1 B43_PHY_N(0x13B) /* Power det 1 */ 468 #define B43_NPHY_PWRDET2 B43_PHY_N(0x13C) /* Power det 2 */ 469 #define B43_NPHY_MAXRSSI_DTIME B43_PHY_N(0x13F) /* RSSI max RSSI delay time */ 470 #define B43_NPHY_PIL_DW0 B43_PHY_N(0x141) /* Pilot data weight 0 */ 471 #define B43_NPHY_PIL_DW1 B43_PHY_N(0x142) /* Pilot data weight 1 */ 472 #define B43_NPHY_PIL_DW2 B43_PHY_N(0x143) /* Pilot data weight 2 */ 473 #define B43_NPHY_PIL_DW_BPSK 0x000F /* BPSK */ 474 #define B43_NPHY_PIL_DW_BPSK_SHIFT 0 475 #define B43_NPHY_PIL_DW_QPSK 0x00F0 /* QPSK */ 476 #define B43_NPHY_PIL_DW_QPSK_SHIFT 4 477 #define B43_NPHY_PIL_DW_16QAM 0x0F00 /* 16-QAM */ 478 #define B43_NPHY_PIL_DW_16QAM_SHIFT 8 479 #define B43_NPHY_PIL_DW_64QAM 0xF000 /* 64-QAM */ 480 #define B43_NPHY_PIL_DW_64QAM_SHIFT 12 481 #define B43_NPHY_FMDEM_CFG B43_PHY_N(0x144) /* FM demodulation config */ 482 #define B43_NPHY_PHASETR_A0 B43_PHY_N(0x145) /* Phase track alpha 0 */ 483 #define B43_NPHY_PHASETR_A1 B43_PHY_N(0x146) /* Phase track alpha 1 */ 484 #define B43_NPHY_PHASETR_A2 B43_PHY_N(0x147) /* Phase track alpha 2 */ 485 #define B43_NPHY_PHASETR_B0 B43_PHY_N(0x148) /* Phase track beta 0 */ 486 #define B43_NPHY_PHASETR_B1 B43_PHY_N(0x149) /* Phase track beta 1 */ 487 #define B43_NPHY_PHASETR_B2 B43_PHY_N(0x14A) /* Phase track beta 2 */ 488 #define B43_NPHY_PHASETR_CHG0 B43_PHY_N(0x14B) /* Phase track change 0 */ 489 #define B43_NPHY_PHASETR_CHG1 B43_PHY_N(0x14C) /* Phase track change 1 */ 490 #define B43_NPHY_PHASETW_OFF B43_PHY_N(0x14D) /* Phase track offset */ 491 #define B43_NPHY_RFCTL_DBG B43_PHY_N(0x14E) /* RF control debug */ 492 #define B43_NPHY_CCK_SHIFTB_REF B43_PHY_N(0x150) /* CCK shiftbits reference var */ 493 #define B43_NPHY_OVER_DGAIN0 B43_PHY_N(0x152) /* Override digital gain 0 */ 494 #define B43_NPHY_OVER_DGAIN1 B43_PHY_N(0x153) /* Override digital gain 1 */ 495 #define B43_NPHY_OVER_DGAIN_FDGV 0x0007 /* Force digital gain value */ 496 #define B43_NPHY_OVER_DGAIN_FDGV_SHIFT 0 497 #define B43_NPHY_OVER_DGAIN_FDGEN 0x0008 /* Force digital gain enable */ 498 #define B43_NPHY_OVER_DGAIN_CCKDGECV 0xFF00 /* CCK digital gain enable count value */ 499 #define B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT 8 500 #define B43_NPHY_BIST_STAT4 B43_PHY_N(0x156) /* BIST status 4 */ 501 #define B43_NPHY_RADAR_MAL B43_PHY_N(0x157) /* Radar MA length */ 502 #define B43_NPHY_RADAR_SRCCTL B43_PHY_N(0x158) /* Radar search control */ 503 #define B43_NPHY_VLD_DTSIG B43_PHY_N(0x159) /* VLD data tones sig */ 504 #define B43_NPHY_VLD_DTDAT B43_PHY_N(0x15A) /* VLD data tones data */ 505 #define B43_NPHY_C1_BPHY_RXIQCA0 B43_PHY_N(0x15B) /* Core 1 B PHY RX I/Q comp A0 */ 506 #define B43_NPHY_C1_BPHY_RXIQCB0 B43_PHY_N(0x15C) /* Core 1 B PHY RX I/Q comp B0 */ 507 #define B43_NPHY_C2_BPHY_RXIQCA1 B43_PHY_N(0x15D) /* Core 2 B PHY RX I/Q comp A1 */ 508 #define B43_NPHY_C2_BPHY_RXIQCB1 B43_PHY_N(0x15E) /* Core 2 B PHY RX I/Q comp B1 */ 509 #define B43_NPHY_FREQGAIN0 B43_PHY_N(0x160) /* Frequency gain 0 */ 510 #define B43_NPHY_FREQGAIN1 B43_PHY_N(0x161) /* Frequency gain 1 */ 511 #define B43_NPHY_FREQGAIN2 B43_PHY_N(0x162) /* Frequency gain 2 */ 512 #define B43_NPHY_FREQGAIN3 B43_PHY_N(0x163) /* Frequency gain 3 */ 513 #define B43_NPHY_FREQGAIN4 B43_PHY_N(0x164) /* Frequency gain 4 */ 514 #define B43_NPHY_FREQGAIN5 B43_PHY_N(0x165) /* Frequency gain 5 */ 515 #define B43_NPHY_FREQGAIN6 B43_PHY_N(0x166) /* Frequency gain 6 */ 516 #define B43_NPHY_FREQGAIN7 B43_PHY_N(0x167) /* Frequency gain 7 */ 517 #define B43_NPHY_FREQGAIN_BYPASS B43_PHY_N(0x168) /* Frequency gain bypass */ 518 #define B43_NPHY_TRLOSS B43_PHY_N(0x169) /* TR loss value */ 519 #define B43_NPHY_C1_ADCCLIP B43_PHY_N(0x16A) /* Core 1 ADC clip */ 520 #define B43_NPHY_C2_ADCCLIP B43_PHY_N(0x16B) /* Core 2 ADC clip */ 521 #define B43_NPHY_LTRN_OFFGAIN B43_PHY_N(0x16F) /* LTRN offset gain */ 522 #define B43_NPHY_LTRN_OFF B43_PHY_N(0x170) /* LTRN offset */ 523 #define B43_NPHY_NRDATAT_WWISE20SIG B43_PHY_N(0x171) /* # data tones WWiSE 20 sig */ 524 #define B43_NPHY_NRDATAT_WWISE40SIG B43_PHY_N(0x172) /* # data tones WWiSE 40 sig */ 525 #define B43_NPHY_NRDATAT_TGNSYNC20SIG B43_PHY_N(0x173) /* # data tones TGNsync 20 sig */ 526 #define B43_NPHY_NRDATAT_TGNSYNC40SIG B43_PHY_N(0x174) /* # data tones TGNsync 40 sig */ 527 #define B43_NPHY_WWISE_CRCM0 B43_PHY_N(0x175) /* WWiSE CRC mask 0 */ 528 #define B43_NPHY_WWISE_CRCM1 B43_PHY_N(0x176) /* WWiSE CRC mask 1 */ 529 #define B43_NPHY_WWISE_CRCM2 B43_PHY_N(0x177) /* WWiSE CRC mask 2 */ 530 #define B43_NPHY_WWISE_CRCM3 B43_PHY_N(0x178) /* WWiSE CRC mask 3 */ 531 #define B43_NPHY_WWISE_CRCM4 B43_PHY_N(0x179) /* WWiSE CRC mask 4 */ 532 #define B43_NPHY_CHANEST_CDDSH B43_PHY_N(0x17A) /* Channel estimate CDD shift */ 533 #define B43_NPHY_HTAGC_WCNT B43_PHY_N(0x17B) /* HT ADC wait counters */ 534 #define B43_NPHY_SQPARM B43_PHY_N(0x17C) /* SQ params */ 535 #define B43_NPHY_MCSDUP6M B43_PHY_N(0x17D) /* MCS dup 6M */ 536 #define B43_NPHY_NDATAT_DUP40 B43_PHY_N(0x17E) /* # data tones dup 40 */ 537 #define B43_NPHY_DUP40_TGNSYNC_CYCD B43_PHY_N(0x17F) /* Dup40 TGNsync cycle data */ 538 #define B43_NPHY_DUP40_GFBL B43_PHY_N(0x180) /* Dup40 GF format BL address */ 539 #define B43_NPHY_DUP40_BL B43_PHY_N(0x181) /* Dup40 format BL address */ 540 #define B43_NPHY_LEGDUP_FTA B43_PHY_N(0x182) /* Legacy dup frm table address */ 541 #define B43_NPHY_PACPROC_DBG B43_PHY_N(0x183) /* Packet processing debug */ 542 #define B43_NPHY_PIL_CYC1 B43_PHY_N(0x184) /* Pilot cycle counter 1 */ 543 #define B43_NPHY_PIL_CYC2 B43_PHY_N(0x185) /* Pilot cycle counter 2 */ 544 #define B43_NPHY_TXF_20CO_S0A1 B43_PHY_N(0x186) /* TX filter 20 coeff stage 0 A1 */ 545 #define B43_NPHY_TXF_20CO_S0A2 B43_PHY_N(0x187) /* TX filter 20 coeff stage 0 A2 */ 546 #define B43_NPHY_TXF_20CO_S1A1 B43_PHY_N(0x188) /* TX filter 20 coeff stage 1 A1 */ 547 #define B43_NPHY_TXF_20CO_S1A2 B43_PHY_N(0x189) /* TX filter 20 coeff stage 1 A2 */ 548 #define B43_NPHY_TXF_20CO_S2A1 B43_PHY_N(0x18A) /* TX filter 20 coeff stage 2 A1 */ 549 #define B43_NPHY_TXF_20CO_S2A2 B43_PHY_N(0x18B) /* TX filter 20 coeff stage 2 A2 */ 550 #define B43_NPHY_TXF_20CO_S0B1 B43_PHY_N(0x18C) /* TX filter 20 coeff stage 0 B1 */ 551 #define B43_NPHY_TXF_20CO_S0B2 B43_PHY_N(0x18D) /* TX filter 20 coeff stage 0 B2 */ 552 #define B43_NPHY_TXF_20CO_S0B3 B43_PHY_N(0x18E) /* TX filter 20 coeff stage 0 B3 */ 553 #define B43_NPHY_TXF_20CO_S1B1 B43_PHY_N(0x18F) /* TX filter 20 coeff stage 1 B1 */ 554 #define B43_NPHY_TXF_20CO_S1B2 B43_PHY_N(0x190) /* TX filter 20 coeff stage 1 B2 */ 555 #define B43_NPHY_TXF_20CO_S1B3 B43_PHY_N(0x191) /* TX filter 20 coeff stage 1 B3 */ 556 #define B43_NPHY_TXF_20CO_S2B1 B43_PHY_N(0x192) /* TX filter 20 coeff stage 2 B1 */ 557 #define B43_NPHY_TXF_20CO_S2B2 B43_PHY_N(0x193) /* TX filter 20 coeff stage 2 B2 */ 558 #define B43_NPHY_TXF_20CO_S2B3 B43_PHY_N(0x194) /* TX filter 20 coeff stage 2 B3 */ 559 #define B43_NPHY_TXF_40CO_S0A1 B43_PHY_N(0x195) /* TX filter 40 coeff stage 0 A1 */ 560 #define B43_NPHY_TXF_40CO_S0A2 B43_PHY_N(0x196) /* TX filter 40 coeff stage 0 A2 */ 561 #define B43_NPHY_TXF_40CO_S1A1 B43_PHY_N(0x197) /* TX filter 40 coeff stage 1 A1 */ 562 #define B43_NPHY_TXF_40CO_S1A2 B43_PHY_N(0x198) /* TX filter 40 coeff stage 1 A2 */ 563 #define B43_NPHY_TXF_40CO_S2A1 B43_PHY_N(0x199) /* TX filter 40 coeff stage 2 A1 */ 564 #define B43_NPHY_TXF_40CO_S2A2 B43_PHY_N(0x19A) /* TX filter 40 coeff stage 2 A2 */ 565 #define B43_NPHY_TXF_40CO_S0B1 B43_PHY_N(0x19B) /* TX filter 40 coeff stage 0 B1 */ 566 #define B43_NPHY_TXF_40CO_S0B2 B43_PHY_N(0x19C) /* TX filter 40 coeff stage 0 B2 */ 567 #define B43_NPHY_TXF_40CO_S0B3 B43_PHY_N(0x19D) /* TX filter 40 coeff stage 0 B3 */ 568 #define B43_NPHY_TXF_40CO_S1B1 B43_PHY_N(0x19E) /* TX filter 40 coeff stage 1 B1 */ 569 #define B43_NPHY_TXF_40CO_S1B2 B43_PHY_N(0x19F) /* TX filter 40 coeff stage 1 B2 */ 570 #define B43_NPHY_TXF_40CO_S1B3 B43_PHY_N(0x1A0) /* TX filter 40 coeff stage 1 B3 */ 571 #define B43_NPHY_TXF_40CO_S2B1 B43_PHY_N(0x1A1) /* TX filter 40 coeff stage 2 B1 */ 572 #define B43_NPHY_TXF_40CO_S2B2 B43_PHY_N(0x1A2) /* TX filter 40 coeff stage 2 B2 */ 573 #define B43_NPHY_TXF_40CO_S2B3 B43_PHY_N(0x1A3) /* TX filter 40 coeff stage 2 B3 */ 574 #define B43_NPHY_RSSIMC_0I_RSSI_X B43_PHY_N(0x1A4) /* RSSI multiplication coefficient 0 I RSSI X */ 575 #define B43_NPHY_RSSIMC_0I_RSSI_Y B43_PHY_N(0x1A5) /* RSSI multiplication coefficient 0 I RSSI Y */ 576 #define B43_NPHY_RSSIMC_0I_RSSI_Z B43_PHY_N(0x1A6) /* RSSI multiplication coefficient 0 I RSSI Z */ 577 #define B43_NPHY_RSSIMC_0I_TBD B43_PHY_N(0x1A7) /* RSSI multiplication coefficient 0 I TBD */ 578 #define B43_NPHY_RSSIMC_0I_PWRDET B43_PHY_N(0x1A8) /* RSSI multiplication coefficient 0 I power det */ 579 #define B43_NPHY_RSSIMC_0I_TSSI B43_PHY_N(0x1A9) /* RSSI multiplication coefficient 0 I TSSI */ 580 #define B43_NPHY_RSSIMC_0Q_RSSI_X B43_PHY_N(0x1AA) /* RSSI multiplication coefficient 0 Q RSSI X */ 581 #define B43_NPHY_RSSIMC_0Q_RSSI_Y B43_PHY_N(0x1AB) /* RSSI multiplication coefficient 0 Q RSSI Y */ 582 #define B43_NPHY_RSSIMC_0Q_RSSI_Z B43_PHY_N(0x1AC) /* RSSI multiplication coefficient 0 Q RSSI Z */ 583 #define B43_NPHY_RSSIMC_0Q_TBD B43_PHY_N(0x1AD) /* RSSI multiplication coefficient 0 Q TBD */ 584 #define B43_NPHY_RSSIMC_0Q_PWRDET B43_PHY_N(0x1AE) /* RSSI multiplication coefficient 0 Q power det */ 585 #define B43_NPHY_RSSIMC_0Q_TSSI B43_PHY_N(0x1AF) /* RSSI multiplication coefficient 0 Q TSSI */ 586 #define B43_NPHY_RSSIMC_1I_RSSI_X B43_PHY_N(0x1B0) /* RSSI multiplication coefficient 1 I RSSI X */ 587 #define B43_NPHY_RSSIMC_1I_RSSI_Y B43_PHY_N(0x1B1) /* RSSI multiplication coefficient 1 I RSSI Y */ 588 #define B43_NPHY_RSSIMC_1I_RSSI_Z B43_PHY_N(0x1B2) /* RSSI multiplication coefficient 1 I RSSI Z */ 589 #define B43_NPHY_RSSIMC_1I_TBD B43_PHY_N(0x1B3) /* RSSI multiplication coefficient 1 I TBD */ 590 #define B43_NPHY_RSSIMC_1I_PWRDET B43_PHY_N(0x1B4) /* RSSI multiplication coefficient 1 I power det */ 591 #define B43_NPHY_RSSIMC_1I_TSSI B43_PHY_N(0x1B5) /* RSSI multiplication coefficient 1 I TSSI */ 592 #define B43_NPHY_RSSIMC_1Q_RSSI_X B43_PHY_N(0x1B6) /* RSSI multiplication coefficient 1 Q RSSI X */ 593 #define B43_NPHY_RSSIMC_1Q_RSSI_Y B43_PHY_N(0x1B7) /* RSSI multiplication coefficient 1 Q RSSI Y */ 594 #define B43_NPHY_RSSIMC_1Q_RSSI_Z B43_PHY_N(0x1B8) /* RSSI multiplication coefficient 1 Q RSSI Z */ 595 #define B43_NPHY_RSSIMC_1Q_TBD B43_PHY_N(0x1B9) /* RSSI multiplication coefficient 1 Q TBD */ 596 #define B43_NPHY_RSSIMC_1Q_PWRDET B43_PHY_N(0x1BA) /* RSSI multiplication coefficient 1 Q power det */ 597 #define B43_NPHY_RSSIMC_1Q_TSSI B43_PHY_N(0x1BB) /* RSSI multiplication coefficient 1 Q TSSI */ 598 #define B43_NPHY_SAMC_WCNT B43_PHY_N(0x1BC) /* Sample collect wait counter */ 599 #define B43_NPHY_PTHROUGH_CNT B43_PHY_N(0x1BD) /* Pass-through counter */ 600 #define B43_NPHY_LTRN_OFF_G20L B43_PHY_N(0x1C4) /* LTRN offset gain 20L */ 601 #define B43_NPHY_LTRN_OFF_20L B43_PHY_N(0x1C5) /* LTRN offset 20L */ 602 #define B43_NPHY_LTRN_OFF_G20U B43_PHY_N(0x1C6) /* LTRN offset gain 20U */ 603 #define B43_NPHY_LTRN_OFF_20U B43_PHY_N(0x1C7) /* LTRN offset 20U */ 604 #define B43_NPHY_DSSSCCK_GAINSL B43_PHY_N(0x1C8) /* DSSS/CCK gain settle length */ 605 #define B43_NPHY_GPIO_LOOUT B43_PHY_N(0x1C9) /* GPIO low out */ 606 #define B43_NPHY_GPIO_HIOUT B43_PHY_N(0x1CA) /* GPIO high out */ 607 #define B43_NPHY_CRS_CHECK B43_PHY_N(0x1CB) /* CRS check */ 608 #define B43_NPHY_ML_LOGSS_RAT B43_PHY_N(0x1CC) /* ML/logss ratio */ 609 #define B43_NPHY_DUPSCALE B43_PHY_N(0x1CD) /* Dup scale */ 610 #define B43_NPHY_BW1A B43_PHY_N(0x1CE) /* BW 1A */ 611 #define B43_NPHY_BW2 B43_PHY_N(0x1CF) /* BW 2 */ 612 #define B43_NPHY_BW3 B43_PHY_N(0x1D0) /* BW 3 */ 613 #define B43_NPHY_BW4 B43_PHY_N(0x1D1) /* BW 4 */ 614 #define B43_NPHY_BW5 B43_PHY_N(0x1D2) /* BW 5 */ 615 #define B43_NPHY_BW6 B43_PHY_N(0x1D3) /* BW 6 */ 616 #define B43_NPHY_COALEN0 B43_PHY_N(0x1D4) /* Coarse length 0 */ 617 #define B43_NPHY_COALEN1 B43_PHY_N(0x1D5) /* Coarse length 1 */ 618 #define B43_NPHY_CRSTHRES_1U B43_PHY_N(0x1D6) /* CRS threshold 1 U */ 619 #define B43_NPHY_CRSTHRES_2U B43_PHY_N(0x1D7) /* CRS threshold 2 U */ 620 #define B43_NPHY_CRSTHRES_3U B43_PHY_N(0x1D8) /* CRS threshold 3 U */ 621 #define B43_NPHY_CRSCTL_U B43_PHY_N(0x1D9) /* CRS control U */ 622 #define B43_NPHY_CRSTHRES_1L B43_PHY_N(0x1DA) /* CRS threshold 1 L */ 623 #define B43_NPHY_CRSTHRES_2L B43_PHY_N(0x1DB) /* CRS threshold 2 L */ 624 #define B43_NPHY_CRSTHRES_3L B43_PHY_N(0x1DC) /* CRS threshold 3 L */ 625 #define B43_NPHY_CRSCTL_L B43_PHY_N(0x1DD) /* CRS control L */ 626 #define B43_NPHY_STRA_1U B43_PHY_N(0x1DE) /* STR address 1 U */ 627 #define B43_NPHY_STRA_2U B43_PHY_N(0x1DF) /* STR address 2 U */ 628 #define B43_NPHY_STRA_1L B43_PHY_N(0x1E0) /* STR address 1 L */ 629 #define B43_NPHY_STRA_2L B43_PHY_N(0x1E1) /* STR address 2 L */ 630 #define B43_NPHY_CRSCHECK1 B43_PHY_N(0x1E2) /* CRS check 1 */ 631 #define B43_NPHY_CRSCHECK2 B43_PHY_N(0x1E3) /* CRS check 2 */ 632 #define B43_NPHY_CRSCHECK3 B43_PHY_N(0x1E4) /* CRS check 3 */ 633 #define B43_NPHY_JMPSTP0 B43_PHY_N(0x1E5) /* Jump step 0 */ 634 #define B43_NPHY_JMPSTP1 B43_PHY_N(0x1E6) /* Jump step 1 */ 635 #define B43_NPHY_TXPCTL_CMD B43_PHY_N(0x1E7) /* TX power control command */ 636 #define B43_NPHY_TXPCTL_CMD_INIT 0x007F /* Init */ 637 #define B43_NPHY_TXPCTL_CMD_INIT_SHIFT 0 638 #define B43_NPHY_TXPCTL_CMD_COEFF 0x2000 /* Power control coefficients */ 639 #define B43_NPHY_TXPCTL_CMD_HWPCTLEN 0x4000 /* Hardware TX power control enable */ 640 #define B43_NPHY_TXPCTL_CMD_PCTLEN 0x8000 /* TX power control enable */ 641 #define B43_NPHY_TXPCTL_N B43_PHY_N(0x1E8) /* TX power control N num */ 642 #define B43_NPHY_TXPCTL_N_TSSID 0x00FF /* N TSSI delay */ 643 #define B43_NPHY_TXPCTL_N_TSSID_SHIFT 0 644 #define B43_NPHY_TXPCTL_N_NPTIL2 0x0700 /* N PT integer log2 */ 645 #define B43_NPHY_TXPCTL_N_NPTIL2_SHIFT 8 646 #define B43_NPHY_TXPCTL_ITSSI B43_PHY_N(0x1E9) /* TX power control idle TSSI */ 647 #define B43_NPHY_TXPCTL_ITSSI_0 0x003F /* Idle TSSI 0 */ 648 #define B43_NPHY_TXPCTL_ITSSI_0_SHIFT 0 649 #define B43_NPHY_TXPCTL_ITSSI_1 0x3F00 /* Idle TSSI 1 */ 650 #define B43_NPHY_TXPCTL_ITSSI_1_SHIFT 8 651 #define B43_NPHY_TXPCTL_ITSSI_BINF 0x8000 /* Raw TSSI offset bin format */ 652 #define B43_NPHY_TXPCTL_TPWR B43_PHY_N(0x1EA) /* TX power control target power */ 653 #define B43_NPHY_TXPCTL_TPWR_0 0x00FF /* Power 0 */ 654 #define B43_NPHY_TXPCTL_TPWR_0_SHIFT 0 655 #define B43_NPHY_TXPCTL_TPWR_1 0xFF00 /* Power 1 */ 656 #define B43_NPHY_TXPCTL_TPWR_1_SHIFT 8 657 #define B43_NPHY_TXPCTL_BIDX B43_PHY_N(0x1EB) /* TX power control base index */ 658 #define B43_NPHY_TXPCTL_BIDX_0 0x007F /* uC base index 0 */ 659 #define B43_NPHY_TXPCTL_BIDX_0_SHIFT 0 660 #define B43_NPHY_TXPCTL_BIDX_1 0x7F00 /* uC base index 1 */ 661 #define B43_NPHY_TXPCTL_BIDX_1_SHIFT 8 662 #define B43_NPHY_TXPCTL_BIDX_LOAD 0x8000 /* Load base index */ 663 #define B43_NPHY_TXPCTL_PIDX B43_PHY_N(0x1EC) /* TX power control power index */ 664 #define B43_NPHY_TXPCTL_PIDX_0 0x007F /* uC power index 0 */ 665 #define B43_NPHY_TXPCTL_PIDX_0_SHIFT 0 666 #define B43_NPHY_TXPCTL_PIDX_1 0x7F00 /* uC power index 1 */ 667 #define B43_NPHY_TXPCTL_PIDX_1_SHIFT 8 668 #define B43_NPHY_C1_TXPCTL_STAT B43_PHY_N(0x1ED) /* Core 1 TX power control status */ 669 #define B43_NPHY_C2_TXPCTL_STAT B43_PHY_N(0x1EE) /* Core 2 TX power control status */ 670 #define B43_NPHY_TXPCTL_STAT_EST 0x00FF /* Estimated power */ 671 #define B43_NPHY_TXPCTL_STAT_EST_SHIFT 0 672 #define B43_NPHY_TXPCTL_STAT_BIDX 0x7F00 /* Base index */ 673 #define B43_NPHY_TXPCTL_STAT_BIDX_SHIFT 8 674 #define B43_NPHY_TXPCTL_STAT_ESTVALID 0x8000 /* Estimated power valid */ 675 #define B43_NPHY_SMALLSGS_LEN B43_PHY_N(0x1EF) /* Small sig gain settle length */ 676 #define B43_NPHY_PHYSTAT_GAIN0 B43_PHY_N(0x1F0) /* PHY stats gain info 0 */ 677 #define B43_NPHY_PHYSTAT_GAIN1 B43_PHY_N(0x1F1) /* PHY stats gain info 1 */ 678 #define B43_NPHY_PHYSTAT_FREQEST B43_PHY_N(0x1F2) /* PHY stats frequency estimate */ 679 #define B43_NPHY_PHYSTAT_ADVRET B43_PHY_N(0x1F3) /* PHY stats ADV retard */ 680 #define B43_NPHY_PHYLB_MODE B43_PHY_N(0x1F4) /* PHY loopback mode */ 681 #define B43_NPHY_TONE_MIDX20_1 B43_PHY_N(0x1F5) /* Tone map index 20/1 */ 682 #define B43_NPHY_TONE_MIDX20_2 B43_PHY_N(0x1F6) /* Tone map index 20/2 */ 683 #define B43_NPHY_TONE_MIDX20_3 B43_PHY_N(0x1F7) /* Tone map index 20/3 */ 684 #define B43_NPHY_TONE_MIDX40_1 B43_PHY_N(0x1F8) /* Tone map index 40/1 */ 685 #define B43_NPHY_TONE_MIDX40_2 B43_PHY_N(0x1F9) /* Tone map index 40/2 */ 686 #define B43_NPHY_TONE_MIDX40_3 B43_PHY_N(0x1FA) /* Tone map index 40/3 */ 687 #define B43_NPHY_TONE_MIDX40_4 B43_PHY_N(0x1FB) /* Tone map index 40/4 */ 688 #define B43_NPHY_PILTONE_MIDX1 B43_PHY_N(0x1FC) /* Pilot tone map index 1 */ 689 #define B43_NPHY_PILTONE_MIDX2 B43_PHY_N(0x1FD) /* Pilot tone map index 2 */ 690 #define B43_NPHY_PILTONE_MIDX3 B43_PHY_N(0x1FE) /* Pilot tone map index 3 */ 691 #define B43_NPHY_TXRIFS_FRDEL B43_PHY_N(0x1FF) /* TX RIFS frame delay */ 692 #define B43_NPHY_AFESEQ_RX2TX_PUD_40M B43_PHY_N(0x200) /* AFE seq rx2tx power up/down delay 40M */ 693 #define B43_NPHY_AFESEQ_TX2RX_PUD_40M B43_PHY_N(0x201) /* AFE seq tx2rx power up/down delay 40M */ 694 #define B43_NPHY_AFESEQ_RX2TX_PUD_20M B43_PHY_N(0x202) /* AFE seq rx2tx power up/down delay 20M */ 695 #define B43_NPHY_AFESEQ_TX2RX_PUD_20M B43_PHY_N(0x203) /* AFE seq tx2rx power up/down delay 20M */ 696 #define B43_NPHY_RX_SIGCTL B43_PHY_N(0x204) /* RX signal control */ 697 #define B43_NPHY_RXPIL_CYCNT0 B43_PHY_N(0x205) /* RX pilot cycle counter 0 */ 698 #define B43_NPHY_RXPIL_CYCNT1 B43_PHY_N(0x206) /* RX pilot cycle counter 1 */ 699 #define B43_NPHY_RXPIL_CYCNT2 B43_PHY_N(0x207) /* RX pilot cycle counter 2 */ 700 #define B43_NPHY_AFESEQ_RX2TX_PUD_10M B43_PHY_N(0x208) /* AFE seq rx2tx power up/down delay 10M */ 701 #define B43_NPHY_AFESEQ_TX2RX_PUD_10M B43_PHY_N(0x209) /* AFE seq tx2rx power up/down delay 10M */ 702 #define B43_NPHY_DSSSCCK_CRSEXTL B43_PHY_N(0x20A) /* DSSS/CCK CRS extension length */ 703 #define B43_NPHY_ML_LOGSS_RATSLOPE B43_PHY_N(0x20B) /* ML/logss ratio slope */ 704 #define B43_NPHY_RIFS_SRCTL B43_PHY_N(0x20C) /* RIFS search timeout length */ 705 #define B43_NPHY_TXREALFD B43_PHY_N(0x20D) /* TX real frame delay */ 706 #define B43_NPHY_HPANT_SWTHRES B43_PHY_N(0x20E) /* High power antenna switch threshold */ 707 #define B43_NPHY_EDCRS_ASSTHRES0 B43_PHY_N(0x210) /* ED CRS assert threshold 0 */ 708 #define B43_NPHY_EDCRS_ASSTHRES1 B43_PHY_N(0x211) /* ED CRS assert threshold 1 */ 709 #define B43_NPHY_EDCRS_DEASSTHRES0 B43_PHY_N(0x212) /* ED CRS deassert threshold 0 */ 710 #define B43_NPHY_EDCRS_DEASSTHRES1 B43_PHY_N(0x213) /* ED CRS deassert threshold 1 */ 711 #define B43_NPHY_STR_WTIME20U B43_PHY_N(0x214) /* STR wait time 20U */ 712 #define B43_NPHY_STR_WTIME20L B43_PHY_N(0x215) /* STR wait time 20L */ 713 #define B43_NPHY_TONE_MIDX657M B43_PHY_N(0x216) /* Tone map index 657M */ 714 #define B43_NPHY_HTSIGTONES B43_PHY_N(0x217) /* HT signal tones */ 715 #define B43_NPHY_RSSI1 B43_PHY_N(0x219) /* RSSI value 1 */ 716 #define B43_NPHY_RSSI2 B43_PHY_N(0x21A) /* RSSI value 2 */ 717 #define B43_NPHY_CHAN_ESTHANG B43_PHY_N(0x21D) /* Channel estimate hang */ 718 #define B43_NPHY_FINERX2_CGC B43_PHY_N(0x221) /* Fine RX 2 clock gate control */ 719 #define B43_NPHY_FINERX2_CGC_DECGC 0x0008 /* Decode gated clocks */ 720 #define B43_NPHY_TXPCTL_INIT B43_PHY_N(0x222) /* TX power control init */ 721 #define B43_NPHY_TXPCTL_INIT_PIDXI1 0x00FF /* Power index init 1 */ 722 #define B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0 723 #define B43_NPHY_ED_CRSEN B43_PHY_N(0x223) 724 #define B43_NPHY_ED_CRS40ASSERTTHRESH0 B43_PHY_N(0x224) 725 #define B43_NPHY_ED_CRS40ASSERTTHRESH1 B43_PHY_N(0x225) 726 #define B43_NPHY_ED_CRS40DEASSERTTHRESH0 B43_PHY_N(0x226) 727 #define B43_NPHY_ED_CRS40DEASSERTTHRESH1 B43_PHY_N(0x227) 728 #define B43_NPHY_ED_CRS20LASSERTTHRESH0 B43_PHY_N(0x228) 729 #define B43_NPHY_ED_CRS20LASSERTTHRESH1 B43_PHY_N(0x229) 730 #define B43_NPHY_ED_CRS20LDEASSERTTHRESH0 B43_PHY_N(0x22A) 731 #define B43_NPHY_ED_CRS20LDEASSERTTHRESH1 B43_PHY_N(0x22B) 732 #define B43_NPHY_ED_CRS20UASSERTTHRESH0 B43_PHY_N(0x22C) 733 #define B43_NPHY_ED_CRS20UASSERTTHRESH1 B43_PHY_N(0x22D) 734 #define B43_NPHY_ED_CRS20UDEASSERTTHRESH0 B43_PHY_N(0x22E) 735 #define B43_NPHY_ED_CRS20UDEASSERTTHRESH1 B43_PHY_N(0x22F) 736 #define B43_NPHY_ED_CRS B43_PHY_N(0x230) 737 #define B43_NPHY_TIMEOUTEN B43_PHY_N(0x231) 738 #define B43_NPHY_OFDMPAYDECODETIMEOUTLEN B43_PHY_N(0x232) 739 #define B43_NPHY_CCKPAYDECODETIMEOUTLEN B43_PHY_N(0x233) 740 #define B43_NPHY_NONPAYDECODETIMEOUTLEN B43_PHY_N(0x234) 741 #define B43_NPHY_TIMEOUTSTATUS B43_PHY_N(0x235) 742 #define B43_NPHY_RFCTRLCORE0GPIO0 B43_PHY_N(0x236) 743 #define B43_NPHY_RFCTRLCORE0GPIO1 B43_PHY_N(0x237) 744 #define B43_NPHY_RFCTRLCORE0GPIO2 B43_PHY_N(0x238) 745 #define B43_NPHY_RFCTRLCORE0GPIO3 B43_PHY_N(0x239) 746 #define B43_NPHY_RFCTRLCORE1GPIO0 B43_PHY_N(0x23A) 747 #define B43_NPHY_RFCTRLCORE1GPIO1 B43_PHY_N(0x23B) 748 #define B43_NPHY_RFCTRLCORE1GPIO2 B43_PHY_N(0x23C) 749 #define B43_NPHY_RFCTRLCORE1GPIO3 B43_PHY_N(0x23D) 750 #define B43_NPHY_BPHYTESTCONTROL B43_PHY_N(0x23E) 751 /* REV3+ */ 752 #define B43_NPHY_FORCEFRONT0 B43_PHY_N(0x23F) 753 #define B43_NPHY_FORCEFRONT1 B43_PHY_N(0x240) 754 #define B43_NPHY_NORMVARHYSTTH B43_PHY_N(0x241) 755 #define B43_NPHY_TXCCKERROR B43_PHY_N(0x242) 756 #define B43_NPHY_AFESEQINITDACGAIN B43_PHY_N(0x243) 757 #define B43_NPHY_TXANTSWLUT B43_PHY_N(0x244) 758 #define B43_NPHY_CORECONFIG B43_PHY_N(0x245) 759 #define B43_NPHY_ANTENNADIVDWELLTIME B43_PHY_N(0x246) 760 #define B43_NPHY_ANTENNACCKDIVDWELLTIME B43_PHY_N(0x247) 761 #define B43_NPHY_ANTENNADIVBACKOFFGAIN B43_PHY_N(0x248) 762 #define B43_NPHY_ANTENNADIVMINGAIN B43_PHY_N(0x249) 763 #define B43_NPHY_BRDSEL_NORMVARHYSTTH B43_PHY_N(0x24A) 764 #define B43_NPHY_RXANTSWITCHCTRL B43_PHY_N(0x24B) 765 #define B43_NPHY_ENERGYDROPTIMEOUTLEN2 B43_PHY_N(0x24C) 766 #define B43_NPHY_ML_LOG_TXEVM0 B43_PHY_N(0x250) 767 #define B43_NPHY_ML_LOG_TXEVM1 B43_PHY_N(0x251) 768 #define B43_NPHY_ML_LOG_TXEVM2 B43_PHY_N(0x252) 769 #define B43_NPHY_ML_LOG_TXEVM3 B43_PHY_N(0x253) 770 #define B43_NPHY_ML_LOG_TXEVM4 B43_PHY_N(0x254) 771 #define B43_NPHY_ML_LOG_TXEVM5 B43_PHY_N(0x255) 772 #define B43_NPHY_ML_LOG_TXEVM6 B43_PHY_N(0x256) 773 #define B43_NPHY_ML_LOG_TXEVM7 B43_PHY_N(0x257) 774 #define B43_NPHY_ML_SCALE_TWEAK B43_PHY_N(0x258) 775 #define B43_NPHY_MLUA B43_PHY_N(0x259) 776 #define B43_NPHY_ZFUA B43_PHY_N(0x25A) 777 #define B43_NPHY_CHANUPSYM01 B43_PHY_N(0x25B) 778 #define B43_NPHY_CHANUPSYM2 B43_PHY_N(0x25C) 779 #define B43_NPHY_RXSTRNFILT20NUM00 B43_PHY_N(0x25D) 780 #define B43_NPHY_RXSTRNFILT20NUM01 B43_PHY_N(0x25E) 781 #define B43_NPHY_RXSTRNFILT20NUM02 B43_PHY_N(0x25F) 782 #define B43_NPHY_RXSTRNFILT20DEN00 B43_PHY_N(0x260) 783 #define B43_NPHY_RXSTRNFILT20DEN01 B43_PHY_N(0x261) 784 #define B43_NPHY_RXSTRNFILT20NUM10 B43_PHY_N(0x262) 785 #define B43_NPHY_RXSTRNFILT20NUM11 B43_PHY_N(0x263) 786 #define B43_NPHY_RXSTRNFILT20NUM12 B43_PHY_N(0x264) 787 #define B43_NPHY_RXSTRNFILT20DEN10 B43_PHY_N(0x265) 788 #define B43_NPHY_RXSTRNFILT20DEN11 B43_PHY_N(0x266) 789 #define B43_NPHY_RXSTRNFILT40NUM00 B43_PHY_N(0x267) 790 #define B43_NPHY_RXSTRNFILT40NUM01 B43_PHY_N(0x268) 791 #define B43_NPHY_RXSTRNFILT40NUM02 B43_PHY_N(0x269) 792 #define B43_NPHY_RXSTRNFILT40DEN00 B43_PHY_N(0x26A) 793 #define B43_NPHY_RXSTRNFILT40DEN01 B43_PHY_N(0x26B) 794 #define B43_NPHY_RXSTRNFILT40NUM10 B43_PHY_N(0x26C) 795 #define B43_NPHY_RXSTRNFILT40NUM11 B43_PHY_N(0x26D) 796 #define B43_NPHY_RXSTRNFILT40NUM12 B43_PHY_N(0x26E) 797 #define B43_NPHY_RXSTRNFILT40DEN10 B43_PHY_N(0x26F) 798 #define B43_NPHY_RXSTRNFILT40DEN11 B43_PHY_N(0x270) 799 #define B43_NPHY_CRSHIGHPOWTHRESHOLD1 B43_PHY_N(0x271) 800 #define B43_NPHY_CRSHIGHPOWTHRESHOLD2 B43_PHY_N(0x272) 801 #define B43_NPHY_CRSHIGHLOWPOWTHRESHOLD B43_PHY_N(0x273) 802 #define B43_NPHY_CRSHIGHPOWTHRESHOLD1L B43_PHY_N(0x274) 803 #define B43_NPHY_CRSHIGHPOWTHRESHOLD2L B43_PHY_N(0x275) 804 #define B43_NPHY_CRSHIGHLOWPOWTHRESHOLDL B43_PHY_N(0x276) 805 #define B43_NPHY_CRSHIGHPOWTHRESHOLD1U B43_PHY_N(0x277) 806 #define B43_NPHY_CRSHIGHPOWTHRESHOLD2U B43_PHY_N(0x278) 807 #define B43_NPHY_CRSHIGHLOWPOWTHRESHOLDU B43_PHY_N(0x279) 808 #define B43_NPHY_CRSACIDETECTTHRESH B43_PHY_N(0x27A) 809 #define B43_NPHY_CRSACIDETECTTHRESHL B43_PHY_N(0x27B) 810 #define B43_NPHY_CRSACIDETECTTHRESHU B43_PHY_N(0x27C) 811 #define B43_NPHY_CRSMINPOWER0 B43_PHY_N(0x27D) 812 #define B43_NPHY_CRSMINPOWER1 B43_PHY_N(0x27E) 813 #define B43_NPHY_CRSMINPOWER2 B43_PHY_N(0x27F) 814 #define B43_NPHY_CRSMINPOWERL0 B43_PHY_N(0x280) 815 #define B43_NPHY_CRSMINPOWERL1 B43_PHY_N(0x281) 816 #define B43_NPHY_CRSMINPOWERL2 B43_PHY_N(0x282) 817 #define B43_NPHY_CRSMINPOWERU0 B43_PHY_N(0x283) 818 #define B43_NPHY_CRSMINPOWERU1 B43_PHY_N(0x284) 819 #define B43_NPHY_CRSMINPOWERU2 B43_PHY_N(0x285) 820 #define B43_NPHY_STRPARAM B43_PHY_N(0x286) 821 #define B43_NPHY_STRPARAML B43_PHY_N(0x287) 822 #define B43_NPHY_STRPARAMU B43_PHY_N(0x288) 823 #define B43_NPHY_BPHYCRSMINPOWER0 B43_PHY_N(0x289) 824 #define B43_NPHY_BPHYCRSMINPOWER1 B43_PHY_N(0x28A) 825 #define B43_NPHY_BPHYCRSMINPOWER2 B43_PHY_N(0x28B) 826 #define B43_NPHY_BPHYFILTDEN0COEF B43_PHY_N(0x28C) 827 #define B43_NPHY_BPHYFILTDEN1COEF B43_PHY_N(0x28D) 828 #define B43_NPHY_BPHYFILTDEN2COEF B43_PHY_N(0x28E) 829 #define B43_NPHY_BPHYFILTNUM0COEF B43_PHY_N(0x28F) 830 #define B43_NPHY_BPHYFILTNUM1COEF B43_PHY_N(0x290) 831 #define B43_NPHY_BPHYFILTNUM2COEF B43_PHY_N(0x291) 832 #define B43_NPHY_BPHYFILTNUM01COEF2 B43_PHY_N(0x292) 833 #define B43_NPHY_BPHYFILTBYPASS B43_PHY_N(0x293) 834 #define B43_NPHY_SGILTRNOFFSET B43_PHY_N(0x294) 835 #define B43_NPHY_RADAR_T2_MIN B43_PHY_N(0x295) 836 #define B43_NPHY_TXPWRCTRLDAMPING B43_PHY_N(0x296) 837 #define B43_NPHY_PAPD_EN0 B43_PHY_N(0x297) /* PAPD Enable0 TBD */ 838 #define B43_NPHY_EPS_TABLE_ADJ0 B43_PHY_N(0x298) /* EPS Table Adj0 TBD */ 839 #define B43_NPHY_EPS_OVERRIDEI_0 B43_PHY_N(0x299) 840 #define B43_NPHY_EPS_OVERRIDEQ_0 B43_PHY_N(0x29A) 841 #define B43_NPHY_PAPD_EN1 B43_PHY_N(0x29B) /* PAPD Enable1 TBD */ 842 #define B43_NPHY_EPS_TABLE_ADJ1 B43_PHY_N(0x29C) /* EPS Table Adj1 TBD */ 843 #define B43_NPHY_EPS_OVERRIDEI_1 B43_PHY_N(0x29D) 844 #define B43_NPHY_EPS_OVERRIDEQ_1 B43_PHY_N(0x29E) 845 #define B43_NPHY_PAPD_CAL_ADDRESS B43_PHY_N(0x29F) 846 #define B43_NPHY_PAPD_CAL_YREFEPSILON B43_PHY_N(0x2A0) 847 #define B43_NPHY_PAPD_CAL_SETTLE B43_PHY_N(0x2A1) 848 #define B43_NPHY_PAPD_CAL_CORRELATE B43_PHY_N(0x2A2) 849 #define B43_NPHY_PAPD_CAL_SHIFTS0 B43_PHY_N(0x2A3) 850 #define B43_NPHY_PAPD_CAL_SHIFTS1 B43_PHY_N(0x2A4) 851 #define B43_NPHY_SAMPLE_START_ADDR B43_PHY_N(0x2A5) 852 #define B43_NPHY_RADAR_ADC_TO_DBM B43_PHY_N(0x2A6) 853 #define B43_NPHY_REV3_C2_INITGAIN_A B43_PHY_N(0x2A7) 854 #define B43_NPHY_REV3_C2_INITGAIN_B B43_PHY_N(0x2A8) 855 #define B43_NPHY_REV3_C2_CLIP_HIGAIN_A B43_PHY_N(0x2A9) 856 #define B43_NPHY_REV3_C2_CLIP_HIGAIN_B B43_PHY_N(0x2AA) 857 #define B43_NPHY_REV3_C2_CLIP_MEDGAIN_A B43_PHY_N(0x2AB) 858 #define B43_NPHY_REV3_C2_CLIP_MEDGAIN_B B43_PHY_N(0x2AC) 859 #define B43_NPHY_REV3_C2_CLIP_LOGAIN_A B43_PHY_N(0x2AD) 860 #define B43_NPHY_REV3_C2_CLIP_LOGAIN_B B43_PHY_N(0x2AE) 861 #define B43_NPHY_REV3_C2_CLIP2_GAIN_A B43_PHY_N(0x2AF) 862 #define B43_NPHY_REV3_C2_CLIP2_GAIN_B B43_PHY_N(0x2B0) 863 864 #define B43_NPHY_REV7_RF_CTL_MISC_REG3 B43_PHY_N(0x340) 865 #define B43_NPHY_REV7_RF_CTL_MISC_REG4 B43_PHY_N(0x341) 866 #define B43_NPHY_REV7_RF_CTL_OVER3 B43_PHY_N(0x342) 867 #define B43_NPHY_REV7_RF_CTL_OVER4 B43_PHY_N(0x343) 868 #define B43_NPHY_REV7_RF_CTL_MISC_REG5 B43_PHY_N(0x344) 869 #define B43_NPHY_REV7_RF_CTL_MISC_REG6 B43_PHY_N(0x345) 870 #define B43_NPHY_REV7_RF_CTL_OVER5 B43_PHY_N(0x346) 871 #define B43_NPHY_REV7_RF_CTL_OVER6 B43_PHY_N(0x347) 872 873 #define B43_PHY_B_BBCFG B43_PHY_N_BMODE(0x001) /* BB config */ 874 #define B43_PHY_B_BBCFG_RSTCCA 0x4000 /* Reset CCA */ 875 #define B43_PHY_B_BBCFG_RSTRX 0x8000 /* Reset RX */ 876 #define B43_PHY_B_TEST B43_PHY_N_BMODE(0x00A) 877 878 struct b43_wldev; 879 880 enum b43_nphy_spur_avoid { 881 B43_SPUR_AVOID_DISABLE, 882 B43_SPUR_AVOID_AUTO, 883 B43_SPUR_AVOID_FORCE, 884 }; 885 886 struct b43_chanspec { 887 u16 center_freq; 888 enum nl80211_channel_type channel_type; 889 }; 890 891 struct b43_phy_n_iq_comp { 892 s16 a0; 893 s16 b0; 894 s16 a1; 895 s16 b1; 896 }; 897 898 struct b43_phy_n_rssical_cache { 899 u16 rssical_radio_regs_2G[2]; 900 u16 rssical_phy_regs_2G[12]; 901 902 u16 rssical_radio_regs_5G[2]; 903 u16 rssical_phy_regs_5G[12]; 904 }; 905 906 struct b43_phy_n_cal_cache { 907 u16 txcal_radio_regs_2G[8]; 908 u16 txcal_coeffs_2G[8]; 909 struct b43_phy_n_iq_comp rxcal_coeffs_2G; 910 911 u16 txcal_radio_regs_5G[8]; 912 u16 txcal_coeffs_5G[8]; 913 struct b43_phy_n_iq_comp rxcal_coeffs_5G; 914 }; 915 916 struct b43_phy_n_txpwrindex { 917 s8 index; 918 s8 index_internal; 919 s8 index_internal_save; 920 u16 AfectrlOverride; 921 u16 AfeCtrlDacGain; 922 u16 rad_gain; 923 u8 bbmult; 924 u16 iqcomp_a; 925 u16 iqcomp_b; 926 u16 locomp; 927 }; 928 929 struct b43_phy_n_pwr_ctl_info { 930 u8 idle_tssi_2g; 931 u8 idle_tssi_5g; 932 }; 933 934 struct b43_phy_n { 935 u8 antsel_type; 936 u8 cal_orig_pwr_idx[2]; 937 u8 measure_hold; 938 u8 phyrxchain; 939 u8 hw_phyrxchain; 940 u8 hw_phytxchain; 941 u8 perical; 942 u32 deaf_count; 943 u32 rxcalparams; 944 bool hang_avoid; 945 bool mute; 946 u16 papd_epsilon_offset[2]; 947 s32 preamble_override; 948 u32 bb_mult_save; 949 950 bool gain_boost; 951 bool elna_gain_config; 952 bool band5g_pwrgain; 953 bool use_int_tx_iq_lo_cal; 954 bool lpf_bw_overrode_for_sample_play; 955 956 u8 mphase_cal_phase_id; 957 u16 mphase_txcal_cmdidx; 958 u16 mphase_txcal_numcmds; 959 u16 mphase_txcal_bestcoeffs[11]; 960 961 bool txpwrctrl; 962 bool pwg_gain_5ghz; 963 u8 tx_pwr_idx[2]; 964 s8 tx_power_offset[101]; 965 u16 adj_pwr_tbl[84]; 966 u16 txcal_bbmult; 967 u16 txiqlocal_bestc[11]; 968 bool txiqlocal_coeffsvalid; 969 struct b43_phy_n_txpwrindex txpwrindex[2]; 970 struct b43_phy_n_pwr_ctl_info pwr_ctl_info[2]; 971 struct b43_chanspec txiqlocal_chanspec; 972 struct b43_ppr tx_pwr_max_ppr; 973 u16 tx_pwr_last_recalc_freq; 974 int tx_pwr_last_recalc_limit; 975 976 u8 txrx_chain; 977 u16 tx_rx_cal_phy_saveregs[11]; 978 u16 tx_rx_cal_radio_saveregs[22]; 979 980 u16 rfctrl_intc1_save; 981 u16 rfctrl_intc2_save; 982 983 u16 classifier_state; 984 u16 clip_state[2]; 985 986 enum b43_nphy_spur_avoid spur_avoid; 987 bool aband_spurwar_en; 988 bool gband_spurwar_en; 989 990 bool ipa2g_on; 991 struct b43_chanspec iqcal_chanspec_2G; 992 struct b43_chanspec rssical_chanspec_2G; 993 994 bool ipa5g_on; 995 struct b43_chanspec iqcal_chanspec_5G; 996 struct b43_chanspec rssical_chanspec_5G; 997 998 struct b43_phy_n_rssical_cache rssical_cache; 999 struct b43_phy_n_cal_cache cal_cache; 1000 bool crsminpwr_adjusted; 1001 bool noisevars_adjusted; 1002 }; 1003 1004 1005 struct b43_phy_operations; 1006 extern const struct b43_phy_operations b43_phyops_n; 1007 1008 #endif /* B43_NPHY_H_ */ 1009