1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // aw883_data_type.h -- The data type of the AW88395 chip 4 // 5 // Copyright (c) 2022-2023 AWINIC Technology CO., LTD 6 // 7 // Author: Bruce zhao <zhaolei@awinic.com> 8 // 9 10 #ifndef __AW88395_DATA_TYPE_H__ 11 #define __AW88395_DATA_TYPE_H__ 12 13 #define PROJECT_NAME_MAX (24) 14 #define CUSTOMER_NAME_MAX (16) 15 #define CFG_VERSION_MAX (4) 16 #define DEV_NAME_MAX (16) 17 #define PROFILE_STR_MAX (32) 18 19 #define ACF_FILE_ID (0xa15f908) 20 21 enum aw_cfg_hdr_version { 22 AW88395_CFG_HDR_VER = 0x00000001, 23 AW88395_CFG_HDR_VER_V1 = 0x01000000, 24 }; 25 26 enum aw_cfg_dde_type { 27 AW88395_DEV_NONE_TYPE_ID = 0xFFFFFFFF, 28 AW88395_DEV_TYPE_ID = 0x00000000, 29 AW88395_SKT_TYPE_ID = 0x00000001, 30 AW88395_DEV_DEFAULT_TYPE_ID = 0x00000002, 31 }; 32 33 enum aw_sec_type { 34 ACF_SEC_TYPE_REG = 0, 35 ACF_SEC_TYPE_DSP, 36 ACF_SEC_TYPE_DSP_CFG, 37 ACF_SEC_TYPE_DSP_FW, 38 ACF_SEC_TYPE_HDR_REG, 39 ACF_SEC_TYPE_HDR_DSP_CFG, 40 ACF_SEC_TYPE_HDR_DSP_FW, 41 ACF_SEC_TYPE_MULTIPLE_BIN, 42 ACF_SEC_TYPE_SKT_PROJECT, 43 ACF_SEC_TYPE_DSP_PROJECT, 44 ACF_SEC_TYPE_MONITOR, 45 ACF_SEC_TYPE_MAX, 46 }; 47 48 enum profile_data_type { 49 AW88395_DATA_TYPE_REG = 0, 50 AW88395_DATA_TYPE_DSP_CFG, 51 AW88395_DATA_TYPE_DSP_FW, 52 AW88395_DATA_TYPE_MAX, 53 }; 54 55 enum aw_prof_type { 56 AW88395_PROFILE_MUSIC = 0, 57 AW88395_PROFILE_VOICE, 58 AW88395_PROFILE_VOIP, 59 AW88395_PROFILE_RINGTONE, 60 AW88395_PROFILE_RINGTONE_HS, 61 AW88395_PROFILE_LOWPOWER, 62 AW88395_PROFILE_BYPASS, 63 AW88395_PROFILE_MMI, 64 AW88395_PROFILE_FM, 65 AW88395_PROFILE_NOTIFICATION, 66 AW88395_PROFILE_RECEIVER, 67 AW88395_PROFILE_MAX, 68 }; 69 70 enum aw_profile_status { 71 AW88395_PROFILE_WAIT = 0, 72 AW88395_PROFILE_OK, 73 }; 74 75 struct aw_cfg_hdr { 76 u32 id; 77 char project[PROJECT_NAME_MAX]; 78 char custom[CUSTOMER_NAME_MAX]; 79 char version[CFG_VERSION_MAX]; 80 u32 author_id; 81 u32 ddt_size; 82 u32 ddt_num; 83 u32 hdr_offset; 84 u32 hdr_version; 85 u32 reserved[3]; 86 }; 87 88 struct aw_cfg_dde { 89 u32 type; 90 char dev_name[DEV_NAME_MAX]; 91 u16 dev_index; 92 u16 dev_bus; 93 u16 dev_addr; 94 u16 dev_profile; 95 u32 data_type; 96 u32 data_size; 97 u32 data_offset; 98 u32 data_crc; 99 u32 reserved[5]; 100 }; 101 102 struct aw_cfg_dde_v1 { 103 u32 type; 104 char dev_name[DEV_NAME_MAX]; 105 u16 dev_index; 106 u16 dev_bus; 107 u16 dev_addr; 108 u16 dev_profile; 109 u32 data_type; 110 u32 data_size; 111 u32 data_offset; 112 u32 data_crc; 113 char dev_profile_str[PROFILE_STR_MAX]; 114 u32 chip_id; 115 u32 reserved[4]; 116 }; 117 118 struct aw_sec_data_desc { 119 u32 len; 120 u8 *data; 121 }; 122 123 struct aw_prof_desc { 124 u32 id; 125 u32 prof_st; 126 char *prf_str; 127 u32 fw_ver; 128 struct aw_sec_data_desc sec_desc[AW88395_DATA_TYPE_MAX]; 129 }; 130 131 struct aw_all_prof_info { 132 struct aw_prof_desc prof_desc[AW88395_PROFILE_MAX]; 133 }; 134 135 struct aw_prof_info { 136 int count; 137 int prof_type; 138 char **prof_name_list; 139 struct aw_prof_desc *prof_desc; 140 }; 141 142 #endif 143