xref: /linux/drivers/gpu/drm/radeon/nid.h (revision 0cce284537fb42d9c28b9b31038ffc9b464555f5)
1 /*
2  * Copyright 2010 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 #ifndef NI_H
25 #define NI_H
26 
27 #define CAYMAN_MAX_SH_GPRS           256
28 #define CAYMAN_MAX_TEMP_GPRS         16
29 #define CAYMAN_MAX_SH_THREADS        256
30 #define CAYMAN_MAX_SH_STACK_ENTRIES  4096
31 #define CAYMAN_MAX_FRC_EOV_CNT       16384
32 #define CAYMAN_MAX_BACKENDS          8
33 #define CAYMAN_MAX_BACKENDS_MASK     0xFF
34 #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF
35 #define CAYMAN_MAX_SIMDS             16
36 #define CAYMAN_MAX_SIMDS_MASK        0xFFFF
37 #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF
38 #define CAYMAN_MAX_PIPES             8
39 #define CAYMAN_MAX_PIPES_MASK        0xFF
40 #define CAYMAN_MAX_LDS_NUM           0xFFFF
41 #define CAYMAN_MAX_TCC               16
42 #define CAYMAN_MAX_TCC_MASK          0xFF
43 
44 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN       0x02011003
45 #define ARUBA_GB_ADDR_CONFIG_GOLDEN        0x12010001
46 
47 #define DMIF_ADDR_CONFIG  				0xBD4
48 
49 /* fusion vce clocks */
50 #define CG_ECLK_CNTL                                    0x620
51 #       define ECLK_DIVIDER_MASK                        0x7f
52 #       define ECLK_DIR_CNTL_EN                         (1 << 8)
53 #define CG_ECLK_STATUS                                  0x624
54 #       define ECLK_STATUS                              (1 << 0)
55 
56 /* DCE6 only */
57 #define DMIF_ADDR_CALC  				0xC00
58 
59 #define	SRBM_GFX_CNTL				        0x0E44
60 #define		RINGID(x)					(((x) & 0x3) << 0)
61 #define		VMID(x)						(((x) & 0x7) << 0)
62 #define	SRBM_STATUS				        0x0E50
63 #define		RLC_RQ_PENDING 				(1 << 3)
64 #define		GRBM_RQ_PENDING 			(1 << 5)
65 #define		VMC_BUSY 				(1 << 8)
66 #define		MCB_BUSY 				(1 << 9)
67 #define		MCB_NON_DISPLAY_BUSY 			(1 << 10)
68 #define		MCC_BUSY 				(1 << 11)
69 #define		MCD_BUSY 				(1 << 12)
70 #define		SEM_BUSY 				(1 << 14)
71 #define		RLC_BUSY 				(1 << 15)
72 #define		IH_BUSY 				(1 << 17)
73 
74 #define	SRBM_SOFT_RESET				        0x0E60
75 #define		SOFT_RESET_BIF				(1 << 1)
76 #define		SOFT_RESET_CG				(1 << 2)
77 #define		SOFT_RESET_DC				(1 << 5)
78 #define		SOFT_RESET_DMA1				(1 << 6)
79 #define		SOFT_RESET_GRBM				(1 << 8)
80 #define		SOFT_RESET_HDP				(1 << 9)
81 #define		SOFT_RESET_IH				(1 << 10)
82 #define		SOFT_RESET_MC				(1 << 11)
83 #define		SOFT_RESET_RLC				(1 << 13)
84 #define		SOFT_RESET_ROM				(1 << 14)
85 #define		SOFT_RESET_SEM				(1 << 15)
86 #define		SOFT_RESET_VMC				(1 << 17)
87 #define		SOFT_RESET_DMA				(1 << 20)
88 #define		SOFT_RESET_TST				(1 << 21)
89 #define		SOFT_RESET_REGBB			(1 << 22)
90 #define		SOFT_RESET_ORB				(1 << 23)
91 
92 #define SRBM_READ_ERROR					0xE98
93 #define SRBM_INT_CNTL					0xEA0
94 #define SRBM_INT_ACK					0xEA8
95 
96 #define	SRBM_STATUS2				        0x0EC4
97 #define		DMA_BUSY 				(1 << 5)
98 #define		DMA1_BUSY 				(1 << 6)
99 
100 #define VM_CONTEXT0_REQUEST_RESPONSE			0x1470
101 #define		REQUEST_TYPE(x)					(((x) & 0xf) << 0)
102 #define		RESPONSE_TYPE_MASK				0x000000F0
103 #define		RESPONSE_TYPE_SHIFT				4
104 #define VM_L2_CNTL					0x1400
105 #define		ENABLE_L2_CACHE					(1 << 0)
106 #define		ENABLE_L2_FRAGMENT_PROCESSING			(1 << 1)
107 #define		ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE		(1 << 9)
108 #define		ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE	(1 << 10)
109 #define		EFFECTIVE_L2_QUEUE_SIZE(x)			(((x) & 7) << 14)
110 #define		CONTEXT1_IDENTITY_ACCESS_MODE(x)		(((x) & 3) << 18)
111 /* CONTEXT1_IDENTITY_ACCESS_MODE
112  * 0 physical = logical
113  * 1 logical via context1 page table
114  * 2 inside identity aperture use translation, outside physical = logical
115  * 3 inside identity aperture physical = logical, outside use translation
116  */
117 #define VM_L2_CNTL2					0x1404
118 #define		INVALIDATE_ALL_L1_TLBS				(1 << 0)
119 #define		INVALIDATE_L2_CACHE				(1 << 1)
120 #define VM_L2_CNTL3					0x1408
121 #define		BANK_SELECT(x)					((x) << 0)
122 #define		CACHE_UPDATE_MODE(x)				((x) << 6)
123 #define		L2_CACHE_BIGK_ASSOCIATIVITY			(1 << 20)
124 #define		L2_CACHE_BIGK_FRAGMENT_SIZE(x)			((x) << 15)
125 #define	VM_L2_STATUS					0x140C
126 #define		L2_BUSY						(1 << 0)
127 #define VM_CONTEXT0_CNTL				0x1410
128 #define		ENABLE_CONTEXT					(1 << 0)
129 #define		PAGE_TABLE_DEPTH(x)				(((x) & 3) << 1)
130 #define		RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 3)
131 #define		RANGE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 4)
132 #define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT	(1 << 6)
133 #define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT	(1 << 7)
134 #define		PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 9)
135 #define		PDE0_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 10)
136 #define		VALID_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 12)
137 #define		VALID_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 13)
138 #define		READ_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 15)
139 #define		READ_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 16)
140 #define		WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 18)
141 #define		WRITE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 19)
142 #define		PAGE_TABLE_BLOCK_SIZE(x)			(((x) & 0xF) << 24)
143 #define VM_CONTEXT1_CNTL				0x1414
144 #define VM_CONTEXT0_CNTL2				0x1430
145 #define VM_CONTEXT1_CNTL2				0x1434
146 #define VM_INVALIDATE_REQUEST				0x1478
147 #define VM_INVALIDATE_RESPONSE				0x147c
148 #define	VM_CONTEXT1_PROTECTION_FAULT_ADDR		0x14FC
149 #define	VM_CONTEXT1_PROTECTION_FAULT_STATUS		0x14DC
150 #define		PROTECTIONS_MASK			(0xf << 0)
151 #define		PROTECTIONS_SHIFT			0
152 		/* bit 0: range
153 		 * bit 2: pde0
154 		 * bit 3: valid
155 		 * bit 4: read
156 		 * bit 5: write
157 		 */
158 #define		MEMORY_CLIENT_ID_MASK			(0xff << 12)
159 #define		MEMORY_CLIENT_ID_SHIFT			12
160 #define		MEMORY_CLIENT_RW_MASK			(1 << 24)
161 #define		MEMORY_CLIENT_RW_SHIFT			24
162 #define		FAULT_VMID_MASK				(0x7 << 25)
163 #define		FAULT_VMID_SHIFT			25
164 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR	0x1518
165 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR	0x151c
166 #define	VM_CONTEXT0_PAGE_TABLE_BASE_ADDR		0x153C
167 #define	VM_CONTEXT0_PAGE_TABLE_START_ADDR		0x155C
168 #define	VM_CONTEXT0_PAGE_TABLE_END_ADDR			0x157C
169 
170 #define MC_SHARED_CHMAP						0x2004
171 #define		NOOFCHAN_SHIFT					12
172 #define		NOOFCHAN_MASK					0x00003000
173 #define MC_SHARED_CHREMAP					0x2008
174 
175 #define	MC_VM_SYSTEM_APERTURE_LOW_ADDR			0x2034
176 #define	MC_VM_SYSTEM_APERTURE_HIGH_ADDR			0x2038
177 #define	MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR		0x203C
178 #define	MC_VM_MX_L1_TLB_CNTL				0x2064
179 #define		ENABLE_L1_TLB					(1 << 0)
180 #define		ENABLE_L1_FRAGMENT_PROCESSING			(1 << 1)
181 #define		SYSTEM_ACCESS_MODE_PA_ONLY			(0 << 3)
182 #define		SYSTEM_ACCESS_MODE_USE_SYS_MAP			(1 << 3)
183 #define		SYSTEM_ACCESS_MODE_IN_SYS			(2 << 3)
184 #define		SYSTEM_ACCESS_MODE_NOT_IN_SYS			(3 << 3)
185 #define		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU	(0 << 5)
186 #define		ENABLE_ADVANCED_DRIVER_MODEL			(1 << 6)
187 #define	FUS_MC_VM_FB_OFFSET				0x2068
188 
189 #define MC_SHARED_BLACKOUT_CNTL           		0x20ac
190 #define	MC_ARB_RAMCFG					0x2760
191 #define		NOOFBANK_SHIFT					0
192 #define		NOOFBANK_MASK					0x00000003
193 #define		NOOFRANK_SHIFT					2
194 #define		NOOFRANK_MASK					0x00000004
195 #define		NOOFROWS_SHIFT					3
196 #define		NOOFROWS_MASK					0x00000038
197 #define		NOOFCOLS_SHIFT					6
198 #define		NOOFCOLS_MASK					0x000000C0
199 #define		CHANSIZE_SHIFT					8
200 #define		CHANSIZE_MASK					0x00000100
201 #define		BURSTLENGTH_SHIFT				9
202 #define		BURSTLENGTH_MASK				0x00000200
203 #define		CHANSIZE_OVERRIDE				(1 << 11)
204 #define MC_SEQ_SUP_CNTL           			0x28c8
205 #define		RUN_MASK      				(1 << 0)
206 #define MC_SEQ_SUP_PGM           			0x28cc
207 #define MC_IO_PAD_CNTL_D0           			0x29d0
208 #define		MEM_FALL_OUT_CMD      			(1 << 8)
209 #define MC_SEQ_MISC0           				0x2a00
210 #define		MC_SEQ_MISC0_GDDR5_SHIFT      		28
211 #define		MC_SEQ_MISC0_GDDR5_MASK      		0xf0000000
212 #define		MC_SEQ_MISC0_GDDR5_VALUE      		5
213 #define MC_SEQ_IO_DEBUG_INDEX           		0x2a44
214 #define MC_SEQ_IO_DEBUG_DATA           			0x2a48
215 
216 #define	HDP_HOST_PATH_CNTL				0x2C00
217 #define	HDP_NONSURFACE_BASE				0x2C04
218 #define	HDP_NONSURFACE_INFO				0x2C08
219 #define	HDP_NONSURFACE_SIZE				0x2C0C
220 #define HDP_ADDR_CONFIG  				0x2F48
221 #define HDP_MISC_CNTL					0x2F4C
222 #define 	HDP_FLUSH_INVALIDATE_CACHE			(1 << 0)
223 
224 #define	CC_SYS_RB_BACKEND_DISABLE			0x3F88
225 #define	GC_USER_SYS_RB_BACKEND_DISABLE			0x3F8C
226 #define	CGTS_SYS_TCC_DISABLE				0x3F90
227 #define	CGTS_USER_SYS_TCC_DISABLE			0x3F94
228 
229 #define RLC_GFX_INDEX           			0x3FC4
230 
231 #define	CONFIG_MEMSIZE					0x5428
232 
233 #define HDP_MEM_COHERENCY_FLUSH_CNTL			0x5480
234 #define HDP_REG_COHERENCY_FLUSH_CNTL			0x54A0
235 
236 #define	GRBM_CNTL					0x8000
237 #define		GRBM_READ_TIMEOUT(x)				((x) << 0)
238 #define	GRBM_STATUS					0x8010
239 #define		CMDFIFO_AVAIL_MASK				0x0000000F
240 #define		RING2_RQ_PENDING				(1 << 4)
241 #define		SRBM_RQ_PENDING					(1 << 5)
242 #define		RING1_RQ_PENDING				(1 << 6)
243 #define		CF_RQ_PENDING					(1 << 7)
244 #define		PF_RQ_PENDING					(1 << 8)
245 #define		GDS_DMA_RQ_PENDING				(1 << 9)
246 #define		GRBM_EE_BUSY					(1 << 10)
247 #define		SX_CLEAN					(1 << 11)
248 #define		DB_CLEAN					(1 << 12)
249 #define		CB_CLEAN					(1 << 13)
250 #define		TA_BUSY 					(1 << 14)
251 #define		GDS_BUSY 					(1 << 15)
252 #define		VGT_BUSY_NO_DMA					(1 << 16)
253 #define		VGT_BUSY					(1 << 17)
254 #define		IA_BUSY_NO_DMA					(1 << 18)
255 #define		IA_BUSY						(1 << 19)
256 #define		SX_BUSY 					(1 << 20)
257 #define		SH_BUSY 					(1 << 21)
258 #define		SPI_BUSY					(1 << 22)
259 #define		SC_BUSY 					(1 << 24)
260 #define		PA_BUSY 					(1 << 25)
261 #define		DB_BUSY 					(1 << 26)
262 #define		CP_COHERENCY_BUSY      				(1 << 28)
263 #define		CP_BUSY 					(1 << 29)
264 #define		CB_BUSY 					(1 << 30)
265 #define		GUI_ACTIVE					(1 << 31)
266 #define	GRBM_STATUS_SE0					0x8014
267 #define	GRBM_STATUS_SE1					0x8018
268 #define		SE_SX_CLEAN					(1 << 0)
269 #define		SE_DB_CLEAN					(1 << 1)
270 #define		SE_CB_CLEAN					(1 << 2)
271 #define		SE_VGT_BUSY					(1 << 23)
272 #define		SE_PA_BUSY					(1 << 24)
273 #define		SE_TA_BUSY					(1 << 25)
274 #define		SE_SX_BUSY					(1 << 26)
275 #define		SE_SPI_BUSY					(1 << 27)
276 #define		SE_SH_BUSY					(1 << 28)
277 #define		SE_SC_BUSY					(1 << 29)
278 #define		SE_DB_BUSY					(1 << 30)
279 #define		SE_CB_BUSY					(1 << 31)
280 #define	GRBM_SOFT_RESET					0x8020
281 #define		SOFT_RESET_CP					(1 << 0)
282 #define		SOFT_RESET_CB					(1 << 1)
283 #define		SOFT_RESET_DB					(1 << 3)
284 #define		SOFT_RESET_GDS					(1 << 4)
285 #define		SOFT_RESET_PA					(1 << 5)
286 #define		SOFT_RESET_SC					(1 << 6)
287 #define		SOFT_RESET_SPI					(1 << 8)
288 #define		SOFT_RESET_SH					(1 << 9)
289 #define		SOFT_RESET_SX					(1 << 10)
290 #define		SOFT_RESET_TC					(1 << 11)
291 #define		SOFT_RESET_TA					(1 << 12)
292 #define		SOFT_RESET_VGT					(1 << 14)
293 #define		SOFT_RESET_IA					(1 << 15)
294 
295 #define GRBM_GFX_INDEX          			0x802C
296 #define		INSTANCE_INDEX(x)			((x) << 0)
297 #define		SE_INDEX(x)     			((x) << 16)
298 #define		INSTANCE_BROADCAST_WRITES      		(1 << 30)
299 #define		SE_BROADCAST_WRITES      		(1 << 31)
300 
301 #define	SCRATCH_REG0					0x8500
302 #define	SCRATCH_REG1					0x8504
303 #define	SCRATCH_REG2					0x8508
304 #define	SCRATCH_REG3					0x850C
305 #define	SCRATCH_REG4					0x8510
306 #define	SCRATCH_REG5					0x8514
307 #define	SCRATCH_REG6					0x8518
308 #define	SCRATCH_REG7					0x851C
309 #define	SCRATCH_UMSK					0x8540
310 #define	SCRATCH_ADDR					0x8544
311 #define	CP_SEM_WAIT_TIMER				0x85BC
312 #define	CP_SEM_INCOMPLETE_TIMER_CNTL			0x85C8
313 #define	CP_COHER_CNTL2					0x85E8
314 #define	CP_STALLED_STAT1			0x8674
315 #define	CP_STALLED_STAT2			0x8678
316 #define	CP_BUSY_STAT				0x867C
317 #define	CP_STAT						0x8680
318 #define CP_ME_CNTL					0x86D8
319 #define		CP_ME_HALT					(1 << 28)
320 #define		CP_PFP_HALT					(1 << 26)
321 #define	CP_RB2_RPTR					0x86f8
322 #define	CP_RB1_RPTR					0x86fc
323 #define	CP_RB0_RPTR					0x8700
324 #define	CP_RB_WPTR_DELAY				0x8704
325 #define CP_MEQ_THRESHOLDS				0x8764
326 #define		MEQ1_START(x)				((x) << 0)
327 #define		MEQ2_START(x)				((x) << 8)
328 #define	CP_PERFMON_CNTL					0x87FC
329 
330 #define	VGT_CACHE_INVALIDATION				0x88C4
331 #define		CACHE_INVALIDATION(x)				((x) << 0)
332 #define			VC_ONLY						0
333 #define			TC_ONLY						1
334 #define			VC_AND_TC					2
335 #define		AUTO_INVLD_EN(x)				((x) << 6)
336 #define			NO_AUTO						0
337 #define			ES_AUTO						1
338 #define			GS_AUTO						2
339 #define			ES_AND_GS_AUTO					3
340 #define	VGT_GS_VERTEX_REUSE				0x88D4
341 
342 #define CC_GC_SHADER_PIPE_CONFIG			0x8950
343 #define	GC_USER_SHADER_PIPE_CONFIG			0x8954
344 #define		INACTIVE_QD_PIPES(x)				((x) << 8)
345 #define		INACTIVE_QD_PIPES_MASK				0x0000FF00
346 #define		INACTIVE_QD_PIPES_SHIFT				8
347 #define		INACTIVE_SIMDS(x)				((x) << 16)
348 #define		INACTIVE_SIMDS_MASK				0xFFFF0000
349 #define		INACTIVE_SIMDS_SHIFT				16
350 
351 #define VGT_PRIMITIVE_TYPE                              0x8958
352 #define	VGT_NUM_INSTANCES				0x8974
353 #define VGT_TF_RING_SIZE				0x8988
354 #define VGT_OFFCHIP_LDS_BASE				0x89b4
355 
356 #define	PA_SC_LINE_STIPPLE_STATE			0x8B10
357 #define	PA_CL_ENHANCE					0x8A14
358 #define		CLIP_VTX_REORDER_ENA				(1 << 0)
359 #define		NUM_CLIP_SEQ(x)					((x) << 1)
360 #define	PA_SC_FIFO_SIZE					0x8BCC
361 #define		SC_PRIM_FIFO_SIZE(x)				((x) << 0)
362 #define		SC_HIZ_TILE_FIFO_SIZE(x)			((x) << 12)
363 #define		SC_EARLYZ_TILE_FIFO_SIZE(x)			((x) << 20)
364 #define	PA_SC_FORCE_EOV_MAX_CNTS			0x8B24
365 #define		FORCE_EOV_MAX_CLK_CNT(x)			((x) << 0)
366 #define		FORCE_EOV_MAX_REZ_CNT(x)			((x) << 16)
367 
368 #define	SQ_CONFIG					0x8C00
369 #define		VC_ENABLE					(1 << 0)
370 #define		EXPORT_SRC_C					(1 << 1)
371 #define		GFX_PRIO(x)					((x) << 2)
372 #define		CS1_PRIO(x)					((x) << 4)
373 #define		CS2_PRIO(x)					((x) << 6)
374 #define	SQ_GPR_RESOURCE_MGMT_1				0x8C04
375 #define		NUM_PS_GPRS(x)					((x) << 0)
376 #define		NUM_VS_GPRS(x)					((x) << 16)
377 #define		NUM_CLAUSE_TEMP_GPRS(x)				((x) << 28)
378 #define SQ_ESGS_RING_SIZE				0x8c44
379 #define SQ_GSVS_RING_SIZE				0x8c4c
380 #define SQ_ESTMP_RING_BASE				0x8c50
381 #define SQ_ESTMP_RING_SIZE				0x8c54
382 #define SQ_GSTMP_RING_BASE				0x8c58
383 #define SQ_GSTMP_RING_SIZE				0x8c5c
384 #define SQ_VSTMP_RING_BASE				0x8c60
385 #define SQ_VSTMP_RING_SIZE				0x8c64
386 #define SQ_PSTMP_RING_BASE				0x8c68
387 #define SQ_PSTMP_RING_SIZE				0x8c6c
388 #define	SQ_MS_FIFO_SIZES				0x8CF0
389 #define		CACHE_FIFO_SIZE(x)				((x) << 0)
390 #define		FETCH_FIFO_HIWATER(x)				((x) << 8)
391 #define		DONE_FIFO_HIWATER(x)				((x) << 16)
392 #define		ALU_UPDATE_FIFO_HIWATER(x)			((x) << 24)
393 #define SQ_LSTMP_RING_BASE				0x8e10
394 #define SQ_LSTMP_RING_SIZE				0x8e14
395 #define SQ_HSTMP_RING_BASE				0x8e18
396 #define SQ_HSTMP_RING_SIZE				0x8e1c
397 #define	SQ_DYN_GPR_CNTL_PS_FLUSH_REQ    		0x8D8C
398 #define		DYN_GPR_ENABLE					(1 << 8)
399 #define SQ_CONST_MEM_BASE				0x8df8
400 
401 #define	SX_EXPORT_BUFFER_SIZES				0x900C
402 #define		COLOR_BUFFER_SIZE(x)				((x) << 0)
403 #define		POSITION_BUFFER_SIZE(x)				((x) << 8)
404 #define		SMX_BUFFER_SIZE(x)				((x) << 16)
405 #define	SX_DEBUG_1					0x9058
406 #define		ENABLE_NEW_SMX_ADDRESS				(1 << 16)
407 
408 #define	SPI_CONFIG_CNTL					0x9100
409 #define		GPR_WRITE_PRIORITY(x)				((x) << 0)
410 #define	SPI_CONFIG_CNTL_1				0x913C
411 #define		VTX_DONE_DELAY(x)				((x) << 0)
412 #define		INTERP_ONE_PRIM_PER_ROW				(1 << 4)
413 #define		CRC_SIMD_ID_WADDR_DISABLE			(1 << 8)
414 
415 #define	CGTS_TCC_DISABLE				0x9148
416 #define	CGTS_USER_TCC_DISABLE				0x914C
417 #define		TCC_DISABLE_MASK				0xFFFF0000
418 #define		TCC_DISABLE_SHIFT				16
419 #define	CGTS_SM_CTRL_REG				0x9150
420 #define		OVERRIDE				(1 << 21)
421 
422 #define	TA_CNTL_AUX					0x9508
423 #define		DISABLE_CUBE_WRAP				(1 << 0)
424 #define		DISABLE_CUBE_ANISO				(1 << 1)
425 
426 #define	TCP_CHAN_STEER_LO				0x960c
427 #define	TCP_CHAN_STEER_HI				0x9610
428 
429 #define CC_RB_BACKEND_DISABLE				0x98F4
430 #define		BACKEND_DISABLE(x)     			((x) << 16)
431 #define GB_ADDR_CONFIG  				0x98F8
432 #define		NUM_PIPES(x)				((x) << 0)
433 #define		NUM_PIPES_MASK				0x00000007
434 #define		NUM_PIPES_SHIFT				0
435 #define		PIPE_INTERLEAVE_SIZE(x)			((x) << 4)
436 #define		PIPE_INTERLEAVE_SIZE_MASK		0x00000070
437 #define		PIPE_INTERLEAVE_SIZE_SHIFT		4
438 #define		BANK_INTERLEAVE_SIZE(x)			((x) << 8)
439 #define		NUM_SHADER_ENGINES(x)			((x) << 12)
440 #define		NUM_SHADER_ENGINES_MASK			0x00003000
441 #define		NUM_SHADER_ENGINES_SHIFT		12
442 #define		SHADER_ENGINE_TILE_SIZE(x)     		((x) << 16)
443 #define		SHADER_ENGINE_TILE_SIZE_MASK		0x00070000
444 #define		SHADER_ENGINE_TILE_SIZE_SHIFT		16
445 #define		NUM_GPUS(x)     			((x) << 20)
446 #define		NUM_GPUS_MASK				0x00700000
447 #define		NUM_GPUS_SHIFT				20
448 #define		MULTI_GPU_TILE_SIZE(x)     		((x) << 24)
449 #define		MULTI_GPU_TILE_SIZE_MASK		0x03000000
450 #define		MULTI_GPU_TILE_SIZE_SHIFT		24
451 #define		ROW_SIZE(x)             		((x) << 28)
452 #define		ROW_SIZE_MASK				0x30000000
453 #define		ROW_SIZE_SHIFT				28
454 #define		NUM_LOWER_PIPES(x)			((x) << 30)
455 #define		NUM_LOWER_PIPES_MASK			0x40000000
456 #define		NUM_LOWER_PIPES_SHIFT			30
457 #define GB_BACKEND_MAP  				0x98FC
458 
459 #define CB_PERF_CTR0_SEL_0				0x9A20
460 #define CB_PERF_CTR0_SEL_1				0x9A24
461 #define CB_PERF_CTR1_SEL_0				0x9A28
462 #define CB_PERF_CTR1_SEL_1				0x9A2C
463 #define CB_PERF_CTR2_SEL_0				0x9A30
464 #define CB_PERF_CTR2_SEL_1				0x9A34
465 #define CB_PERF_CTR3_SEL_0				0x9A38
466 #define CB_PERF_CTR3_SEL_1				0x9A3C
467 
468 #define	GC_USER_RB_BACKEND_DISABLE			0x9B7C
469 #define		BACKEND_DISABLE_MASK			0x00FF0000
470 #define		BACKEND_DISABLE_SHIFT			16
471 
472 #define	SMX_DC_CTL0					0xA020
473 #define		USE_HASH_FUNCTION				(1 << 0)
474 #define		NUMBER_OF_SETS(x)				((x) << 1)
475 #define		FLUSH_ALL_ON_EVENT				(1 << 10)
476 #define		STALL_ON_EVENT					(1 << 11)
477 #define	SMX_EVENT_CTL					0xA02C
478 #define		ES_FLUSH_CTL(x)					((x) << 0)
479 #define		GS_FLUSH_CTL(x)					((x) << 3)
480 #define		ACK_FLUSH_CTL(x)				((x) << 6)
481 #define		SYNC_FLUSH_CTL					(1 << 8)
482 
483 #define	CP_RB0_BASE					0xC100
484 #define	CP_RB0_CNTL					0xC104
485 #define		RB_BUFSZ(x)					((x) << 0)
486 #define		RB_BLKSZ(x)					((x) << 8)
487 #define		RB_NO_UPDATE					(1 << 27)
488 #define		RB_RPTR_WR_ENA					(1 << 31)
489 #define		BUF_SWAP_32BIT					(2 << 16)
490 #define	CP_RB0_RPTR_ADDR				0xC10C
491 #define	CP_RB0_RPTR_ADDR_HI				0xC110
492 #define	CP_RB0_WPTR					0xC114
493 
494 #define CP_INT_CNTL                                     0xC124
495 #       define CNTX_BUSY_INT_ENABLE                     (1 << 19)
496 #       define CNTX_EMPTY_INT_ENABLE                    (1 << 20)
497 #       define TIME_STAMP_INT_ENABLE                    (1 << 26)
498 
499 #define	CP_RB1_BASE					0xC180
500 #define	CP_RB1_CNTL					0xC184
501 #define	CP_RB1_RPTR_ADDR				0xC188
502 #define	CP_RB1_RPTR_ADDR_HI				0xC18C
503 #define	CP_RB1_WPTR					0xC190
504 #define	CP_RB2_BASE					0xC194
505 #define	CP_RB2_CNTL					0xC198
506 #define	CP_RB2_RPTR_ADDR				0xC19C
507 #define	CP_RB2_RPTR_ADDR_HI				0xC1A0
508 #define	CP_RB2_WPTR					0xC1A4
509 #define	CP_PFP_UCODE_ADDR				0xC150
510 #define	CP_PFP_UCODE_DATA				0xC154
511 #define	CP_ME_RAM_RADDR					0xC158
512 #define	CP_ME_RAM_WADDR					0xC15C
513 #define	CP_ME_RAM_DATA					0xC160
514 #define	CP_DEBUG					0xC1FC
515 
516 #define VGT_EVENT_INITIATOR                             0x28a90
517 #       define CACHE_FLUSH_AND_INV_EVENT_TS                     (0x14 << 0)
518 #       define CACHE_FLUSH_AND_INV_EVENT                        (0x16 << 0)
519 
520 /* TN SMU registers */
521 #define	TN_CURRENT_GNB_TEMP				0x1F390
522 
523 /* pm registers */
524 #define	SMC_MSG						0x20c
525 #define		HOST_SMC_MSG(x)				((x) << 0)
526 #define		HOST_SMC_MSG_MASK			(0xff << 0)
527 #define		HOST_SMC_MSG_SHIFT			0
528 #define		HOST_SMC_RESP(x)			((x) << 8)
529 #define		HOST_SMC_RESP_MASK			(0xff << 8)
530 #define		HOST_SMC_RESP_SHIFT			8
531 #define		SMC_HOST_MSG(x)				((x) << 16)
532 #define		SMC_HOST_MSG_MASK			(0xff << 16)
533 #define		SMC_HOST_MSG_SHIFT			16
534 #define		SMC_HOST_RESP(x)			((x) << 24)
535 #define		SMC_HOST_RESP_MASK			(0xff << 24)
536 #define		SMC_HOST_RESP_SHIFT			24
537 
538 #define	CG_SPLL_FUNC_CNTL				0x600
539 #define		SPLL_RESET				(1 << 0)
540 #define		SPLL_SLEEP				(1 << 1)
541 #define		SPLL_BYPASS_EN				(1 << 3)
542 #define		SPLL_REF_DIV(x)				((x) << 4)
543 #define		SPLL_REF_DIV_MASK			(0x3f << 4)
544 #define		SPLL_PDIV_A(x)				((x) << 20)
545 #define		SPLL_PDIV_A_MASK			(0x7f << 20)
546 #define		SPLL_PDIV_A_SHIFT			20
547 #define	CG_SPLL_FUNC_CNTL_2				0x604
548 #define		SCLK_MUX_SEL(x)				((x) << 0)
549 #define		SCLK_MUX_SEL_MASK			(0x1ff << 0)
550 #define	CG_SPLL_FUNC_CNTL_3				0x608
551 #define		SPLL_FB_DIV(x)				((x) << 0)
552 #define		SPLL_FB_DIV_MASK			(0x3ffffff << 0)
553 #define		SPLL_FB_DIV_SHIFT			0
554 #define		SPLL_DITHEN				(1 << 28)
555 
556 #define MPLL_CNTL_MODE                                  0x61c
557 #       define SS_SSEN                                  (1 << 24)
558 #       define SS_DSMODE_EN                             (1 << 25)
559 
560 #define	MPLL_AD_FUNC_CNTL				0x624
561 #define		CLKF(x)					((x) << 0)
562 #define		CLKF_MASK				(0x7f << 0)
563 #define		CLKR(x)					((x) << 7)
564 #define		CLKR_MASK				(0x1f << 7)
565 #define		CLKFRAC(x)				((x) << 12)
566 #define		CLKFRAC_MASK				(0x1f << 12)
567 #define		YCLK_POST_DIV(x)			((x) << 17)
568 #define		YCLK_POST_DIV_MASK			(3 << 17)
569 #define		IBIAS(x)				((x) << 20)
570 #define		IBIAS_MASK				(0x3ff << 20)
571 #define		RESET					(1 << 30)
572 #define		PDNB					(1 << 31)
573 #define	MPLL_AD_FUNC_CNTL_2				0x628
574 #define		BYPASS					(1 << 19)
575 #define		BIAS_GEN_PDNB				(1 << 24)
576 #define		RESET_EN				(1 << 25)
577 #define		VCO_MODE				(1 << 29)
578 #define	MPLL_DQ_FUNC_CNTL				0x62c
579 #define	MPLL_DQ_FUNC_CNTL_2				0x630
580 
581 #define GENERAL_PWRMGT                                  0x63c
582 #       define GLOBAL_PWRMGT_EN                         (1 << 0)
583 #       define STATIC_PM_EN                             (1 << 1)
584 #       define THERMAL_PROTECTION_DIS                   (1 << 2)
585 #       define THERMAL_PROTECTION_TYPE                  (1 << 3)
586 #       define ENABLE_GEN2PCIE                          (1 << 4)
587 #       define ENABLE_GEN2XSP                           (1 << 5)
588 #       define SW_SMIO_INDEX(x)                         ((x) << 6)
589 #       define SW_SMIO_INDEX_MASK                       (3 << 6)
590 #       define SW_SMIO_INDEX_SHIFT                      6
591 #       define LOW_VOLT_D2_ACPI                         (1 << 8)
592 #       define LOW_VOLT_D3_ACPI                         (1 << 9)
593 #       define VOLT_PWRMGT_EN                           (1 << 10)
594 #       define BACKBIAS_PAD_EN                          (1 << 18)
595 #       define BACKBIAS_VALUE                           (1 << 19)
596 #       define DYN_SPREAD_SPECTRUM_EN                   (1 << 23)
597 #       define AC_DC_SW                                 (1 << 24)
598 
599 #define SCLK_PWRMGT_CNTL                                  0x644
600 #       define SCLK_PWRMGT_OFF                            (1 << 0)
601 #       define SCLK_LOW_D1                                (1 << 1)
602 #       define FIR_RESET                                  (1 << 4)
603 #       define FIR_FORCE_TREND_SEL                        (1 << 5)
604 #       define FIR_TREND_MODE                             (1 << 6)
605 #       define DYN_GFX_CLK_OFF_EN                         (1 << 7)
606 #       define GFX_CLK_FORCE_ON                           (1 << 8)
607 #       define GFX_CLK_REQUEST_OFF                        (1 << 9)
608 #       define GFX_CLK_FORCE_OFF                          (1 << 10)
609 #       define GFX_CLK_OFF_ACPI_D1                        (1 << 11)
610 #       define GFX_CLK_OFF_ACPI_D2                        (1 << 12)
611 #       define GFX_CLK_OFF_ACPI_D3                        (1 << 13)
612 #       define DYN_LIGHT_SLEEP_EN                         (1 << 14)
613 #define	MCLK_PWRMGT_CNTL				0x648
614 #       define DLL_SPEED(x)				((x) << 0)
615 #       define DLL_SPEED_MASK				(0x1f << 0)
616 #       define MPLL_PWRMGT_OFF                          (1 << 5)
617 #       define DLL_READY                                (1 << 6)
618 #       define MC_INT_CNTL                              (1 << 7)
619 #       define MRDCKA0_PDNB                             (1 << 8)
620 #       define MRDCKA1_PDNB                             (1 << 9)
621 #       define MRDCKB0_PDNB                             (1 << 10)
622 #       define MRDCKB1_PDNB                             (1 << 11)
623 #       define MRDCKC0_PDNB                             (1 << 12)
624 #       define MRDCKC1_PDNB                             (1 << 13)
625 #       define MRDCKD0_PDNB                             (1 << 14)
626 #       define MRDCKD1_PDNB                             (1 << 15)
627 #       define MRDCKA0_RESET                            (1 << 16)
628 #       define MRDCKA1_RESET                            (1 << 17)
629 #       define MRDCKB0_RESET                            (1 << 18)
630 #       define MRDCKB1_RESET                            (1 << 19)
631 #       define MRDCKC0_RESET                            (1 << 20)
632 #       define MRDCKC1_RESET                            (1 << 21)
633 #       define MRDCKD0_RESET                            (1 << 22)
634 #       define MRDCKD1_RESET                            (1 << 23)
635 #       define DLL_READY_READ                           (1 << 24)
636 #       define USE_DISPLAY_GAP                          (1 << 25)
637 #       define USE_DISPLAY_URGENT_NORMAL                (1 << 26)
638 #       define MPLL_TURNOFF_D2                          (1 << 28)
639 #define	DLL_CNTL					0x64c
640 #       define MRDCKA0_BYPASS                           (1 << 24)
641 #       define MRDCKA1_BYPASS                           (1 << 25)
642 #       define MRDCKB0_BYPASS                           (1 << 26)
643 #       define MRDCKB1_BYPASS                           (1 << 27)
644 #       define MRDCKC0_BYPASS                           (1 << 28)
645 #       define MRDCKC1_BYPASS                           (1 << 29)
646 #       define MRDCKD0_BYPASS                           (1 << 30)
647 #       define MRDCKD1_BYPASS                           (1 << 31)
648 
649 #define TARGET_AND_CURRENT_PROFILE_INDEX                  0x66c
650 #       define CURRENT_STATE_INDEX_MASK                   (0xf << 4)
651 #       define CURRENT_STATE_INDEX_SHIFT                  4
652 
653 #define CG_AT                                           0x6d4
654 #       define CG_R(x)					((x) << 0)
655 #       define CG_R_MASK				(0xffff << 0)
656 #       define CG_L(x)					((x) << 16)
657 #       define CG_L_MASK				(0xffff << 16)
658 
659 #define	CG_BIF_REQ_AND_RSP				0x7f4
660 #define		CG_CLIENT_REQ(x)			((x) << 0)
661 #define		CG_CLIENT_REQ_MASK			(0xff << 0)
662 #define		CG_CLIENT_REQ_SHIFT			0
663 #define		CG_CLIENT_RESP(x)			((x) << 8)
664 #define		CG_CLIENT_RESP_MASK			(0xff << 8)
665 #define		CG_CLIENT_RESP_SHIFT			8
666 #define		CLIENT_CG_REQ(x)			((x) << 16)
667 #define		CLIENT_CG_REQ_MASK			(0xff << 16)
668 #define		CLIENT_CG_REQ_SHIFT			16
669 #define		CLIENT_CG_RESP(x)			((x) << 24)
670 #define		CLIENT_CG_RESP_MASK			(0xff << 24)
671 #define		CLIENT_CG_RESP_SHIFT			24
672 
673 #define	CG_SPLL_SPREAD_SPECTRUM				0x790
674 #define		SSEN					(1 << 0)
675 #define		CLK_S(x)				((x) << 4)
676 #define		CLK_S_MASK				(0xfff << 4)
677 #define		CLK_S_SHIFT				4
678 #define	CG_SPLL_SPREAD_SPECTRUM_2			0x794
679 #define		CLK_V(x)				((x) << 0)
680 #define		CLK_V_MASK				(0x3ffffff << 0)
681 #define		CLK_V_SHIFT				0
682 
683 #define SMC_SCRATCH0                                    0x81c
684 
685 #define	CG_SPLL_FUNC_CNTL_4				0x850
686 
687 #define	MPLL_SS1					0x85c
688 #define		CLKV(x)					((x) << 0)
689 #define		CLKV_MASK				(0x3ffffff << 0)
690 #define	MPLL_SS2					0x860
691 #define		CLKS(x)					((x) << 0)
692 #define		CLKS_MASK				(0xfff << 0)
693 
694 #define	CG_CAC_CTRL					0x88c
695 #define		TID_CNT(x)				((x) << 0)
696 #define		TID_CNT_MASK				(0x3fff << 0)
697 #define		TID_UNIT(x)				((x) << 14)
698 #define		TID_UNIT_MASK				(0xf << 14)
699 
700 #define	CG_IND_ADDR					0x8f8
701 #define	CG_IND_DATA					0x8fc
702 /* CGIND regs */
703 #define	CG_CGTT_LOCAL_0					0x00
704 #define	CG_CGTT_LOCAL_1					0x01
705 
706 #define MC_CG_CONFIG                                    0x25bc
707 #define         MCDW_WR_ENABLE                          (1 << 0)
708 #define         MCDX_WR_ENABLE                          (1 << 1)
709 #define         MCDY_WR_ENABLE                          (1 << 2)
710 #define         MCDZ_WR_ENABLE                          (1 << 3)
711 #define		MC_RD_ENABLE(x)				((x) << 4)
712 #define		MC_RD_ENABLE_MASK			(3 << 4)
713 #define		INDEX(x)				((x) << 6)
714 #define		INDEX_MASK				(0xfff << 6)
715 #define		INDEX_SHIFT				6
716 
717 #define	MC_ARB_CAC_CNTL					0x2750
718 #define         ENABLE                                  (1 << 0)
719 #define		READ_WEIGHT(x)				((x) << 1)
720 #define		READ_WEIGHT_MASK			(0x3f << 1)
721 #define		READ_WEIGHT_SHIFT			1
722 #define		WRITE_WEIGHT(x)				((x) << 7)
723 #define		WRITE_WEIGHT_MASK			(0x3f << 7)
724 #define		WRITE_WEIGHT_SHIFT			7
725 #define         ALLOW_OVERFLOW                          (1 << 13)
726 
727 #define	MC_ARB_DRAM_TIMING				0x2774
728 #define	MC_ARB_DRAM_TIMING2				0x2778
729 
730 #define	MC_ARB_RFSH_RATE				0x27b0
731 #define		POWERMODE0(x)				((x) << 0)
732 #define		POWERMODE0_MASK				(0xff << 0)
733 #define		POWERMODE0_SHIFT			0
734 #define		POWERMODE1(x)				((x) << 8)
735 #define		POWERMODE1_MASK				(0xff << 8)
736 #define		POWERMODE1_SHIFT			8
737 #define		POWERMODE2(x)				((x) << 16)
738 #define		POWERMODE2_MASK				(0xff << 16)
739 #define		POWERMODE2_SHIFT			16
740 #define		POWERMODE3(x)				((x) << 24)
741 #define		POWERMODE3_MASK				(0xff << 24)
742 #define		POWERMODE3_SHIFT			24
743 
744 #define MC_ARB_CG                                       0x27e8
745 #define		CG_ARB_REQ(x)				((x) << 0)
746 #define		CG_ARB_REQ_MASK				(0xff << 0)
747 #define		CG_ARB_REQ_SHIFT			0
748 #define		CG_ARB_RESP(x)				((x) << 8)
749 #define		CG_ARB_RESP_MASK			(0xff << 8)
750 #define		CG_ARB_RESP_SHIFT			8
751 #define		ARB_CG_REQ(x)				((x) << 16)
752 #define		ARB_CG_REQ_MASK				(0xff << 16)
753 #define		ARB_CG_REQ_SHIFT			16
754 #define		ARB_CG_RESP(x)				((x) << 24)
755 #define		ARB_CG_RESP_MASK			(0xff << 24)
756 #define		ARB_CG_RESP_SHIFT			24
757 
758 #define	MC_ARB_DRAM_TIMING_1				0x27f0
759 #define	MC_ARB_DRAM_TIMING_2				0x27f4
760 #define	MC_ARB_DRAM_TIMING_3				0x27f8
761 #define	MC_ARB_DRAM_TIMING2_1				0x27fc
762 #define	MC_ARB_DRAM_TIMING2_2				0x2800
763 #define	MC_ARB_DRAM_TIMING2_3				0x2804
764 #define MC_ARB_BURST_TIME                               0x2808
765 #define		STATE0(x)				((x) << 0)
766 #define		STATE0_MASK				(0x1f << 0)
767 #define		STATE0_SHIFT				0
768 #define		STATE1(x)				((x) << 5)
769 #define		STATE1_MASK				(0x1f << 5)
770 #define		STATE1_SHIFT				5
771 #define		STATE2(x)				((x) << 10)
772 #define		STATE2_MASK				(0x1f << 10)
773 #define		STATE2_SHIFT				10
774 #define		STATE3(x)				((x) << 15)
775 #define		STATE3_MASK				(0x1f << 15)
776 #define		STATE3_SHIFT				15
777 
778 #define MC_CG_DATAPORT                                  0x2884
779 
780 #define MC_SEQ_RAS_TIMING                               0x28a0
781 #define MC_SEQ_CAS_TIMING                               0x28a4
782 #define MC_SEQ_MISC_TIMING                              0x28a8
783 #define MC_SEQ_MISC_TIMING2                             0x28ac
784 #define MC_SEQ_PMG_TIMING                               0x28b0
785 #define MC_SEQ_RD_CTL_D0                                0x28b4
786 #define MC_SEQ_RD_CTL_D1                                0x28b8
787 #define MC_SEQ_WR_CTL_D0                                0x28bc
788 #define MC_SEQ_WR_CTL_D1                                0x28c0
789 
790 #define MC_SEQ_MISC0                                    0x2a00
791 #define         MC_SEQ_MISC0_GDDR5_SHIFT                28
792 #define         MC_SEQ_MISC0_GDDR5_MASK                 0xf0000000
793 #define         MC_SEQ_MISC0_GDDR5_VALUE                5
794 #define MC_SEQ_MISC1                                    0x2a04
795 #define MC_SEQ_RESERVE_M                                0x2a08
796 #define MC_PMG_CMD_EMRS                                 0x2a0c
797 
798 #define MC_SEQ_MISC3                                    0x2a2c
799 
800 #define MC_SEQ_MISC5                                    0x2a54
801 #define MC_SEQ_MISC6                                    0x2a58
802 
803 #define MC_SEQ_MISC7                                    0x2a64
804 
805 #define MC_SEQ_RAS_TIMING_LP                            0x2a6c
806 #define MC_SEQ_CAS_TIMING_LP                            0x2a70
807 #define MC_SEQ_MISC_TIMING_LP                           0x2a74
808 #define MC_SEQ_MISC_TIMING2_LP                          0x2a78
809 #define MC_SEQ_WR_CTL_D0_LP                             0x2a7c
810 #define MC_SEQ_WR_CTL_D1_LP                             0x2a80
811 #define MC_SEQ_PMG_CMD_EMRS_LP                          0x2a84
812 #define MC_SEQ_PMG_CMD_MRS_LP                           0x2a88
813 
814 #define MC_PMG_CMD_MRS                                  0x2aac
815 
816 #define MC_SEQ_RD_CTL_D0_LP                             0x2b1c
817 #define MC_SEQ_RD_CTL_D1_LP                             0x2b20
818 
819 #define MC_PMG_CMD_MRS1                                 0x2b44
820 #define MC_SEQ_PMG_CMD_MRS1_LP                          0x2b48
821 #define MC_SEQ_PMG_TIMING_LP                            0x2b4c
822 
823 #define MC_PMG_CMD_MRS2                                 0x2b5c
824 #define MC_SEQ_PMG_CMD_MRS2_LP                          0x2b60
825 
826 #define AUX_CONTROL					0x6200
827 #define 	AUX_EN					(1 << 0)
828 #define 	AUX_LS_READ_EN				(1 << 8)
829 #define 	AUX_LS_UPDATE_DISABLE(x)		(((x) & 0x1) << 12)
830 #define 	AUX_HPD_DISCON(x)			(((x) & 0x1) << 16)
831 #define 	AUX_DET_EN				(1 << 18)
832 #define 	AUX_HPD_SEL(x)				(((x) & 0x7) << 20)
833 #define 	AUX_IMPCAL_REQ_EN			(1 << 24)
834 #define 	AUX_TEST_MODE				(1 << 28)
835 #define 	AUX_DEGLITCH_EN				(1 << 29)
836 #define AUX_SW_CONTROL					0x6204
837 #define 	AUX_SW_GO				(1 << 0)
838 #define 	AUX_LS_READ_TRIG			(1 << 2)
839 #define 	AUX_SW_START_DELAY(x)			(((x) & 0xf) << 4)
840 #define 	AUX_SW_WR_BYTES(x)			(((x) & 0x1f) << 16)
841 
842 #define AUX_SW_INTERRUPT_CONTROL			0x620c
843 #define 	AUX_SW_DONE_INT				(1 << 0)
844 #define 	AUX_SW_DONE_ACK				(1 << 1)
845 #define 	AUX_SW_DONE_MASK			(1 << 2)
846 #define 	AUX_SW_LS_DONE_INT			(1 << 4)
847 #define 	AUX_SW_LS_DONE_MASK			(1 << 6)
848 #define AUX_SW_STATUS					0x6210
849 #define 	AUX_SW_DONE				(1 << 0)
850 #define 	AUX_SW_REQ				(1 << 1)
851 #define 	AUX_SW_RX_TIMEOUT_STATE(x)		(((x) & 0x7) << 4)
852 #define 	AUX_SW_RX_TIMEOUT			(1 << 7)
853 #define 	AUX_SW_RX_OVERFLOW			(1 << 8)
854 #define 	AUX_SW_RX_HPD_DISCON			(1 << 9)
855 #define 	AUX_SW_RX_PARTIAL_BYTE			(1 << 10)
856 #define 	AUX_SW_NON_AUX_MODE			(1 << 11)
857 #define 	AUX_SW_RX_MIN_COUNT_VIOL		(1 << 12)
858 #define 	AUX_SW_RX_INVALID_STOP			(1 << 14)
859 #define 	AUX_SW_RX_SYNC_INVALID_L		(1 << 17)
860 #define 	AUX_SW_RX_SYNC_INVALID_H		(1 << 18)
861 #define 	AUX_SW_RX_INVALID_START			(1 << 19)
862 #define 	AUX_SW_RX_RECV_NO_DET			(1 << 20)
863 #define 	AUX_SW_RX_RECV_INVALID_H		(1 << 22)
864 #define 	AUX_SW_RX_RECV_INVALID_V		(1 << 23)
865 
866 #define AUX_SW_DATA					0x6218
867 #define AUX_SW_DATA_RW					(1 << 0)
868 #define AUX_SW_DATA_MASK(x)				(((x) & 0xff) << 8)
869 #define AUX_SW_DATA_INDEX(x)				(((x) & 0x1f) << 16)
870 #define AUX_SW_AUTOINCREMENT_DISABLE			(1 << 31)
871 
872 #define	LB_SYNC_RESET_SEL				0x6b28
873 #define		LB_SYNC_RESET_SEL_MASK			(3 << 0)
874 #define		LB_SYNC_RESET_SEL_SHIFT			0
875 
876 #define	DC_STUTTER_CNTL					0x6b30
877 #define		DC_STUTTER_ENABLE_A			(1 << 0)
878 #define		DC_STUTTER_ENABLE_B			(1 << 1)
879 
880 #define SQ_CAC_THRESHOLD                                0x8e4c
881 #define		VSP(x)					((x) << 0)
882 #define		VSP_MASK				(0xff << 0)
883 #define		VSP_SHIFT				0
884 #define		VSP0(x)					((x) << 8)
885 #define		VSP0_MASK				(0xff << 8)
886 #define		VSP0_SHIFT				8
887 #define		GPR(x)					((x) << 16)
888 #define		GPR_MASK				(0xff << 16)
889 #define		GPR_SHIFT				16
890 
891 #define SQ_POWER_THROTTLE                               0x8e58
892 #define		MIN_POWER(x)				((x) << 0)
893 #define		MIN_POWER_MASK				(0x3fff << 0)
894 #define		MIN_POWER_SHIFT				0
895 #define		MAX_POWER(x)				((x) << 16)
896 #define		MAX_POWER_MASK				(0x3fff << 16)
897 #define		MAX_POWER_SHIFT				0
898 #define SQ_POWER_THROTTLE2                              0x8e5c
899 #define		MAX_POWER_DELTA(x)			((x) << 0)
900 #define		MAX_POWER_DELTA_MASK			(0x3fff << 0)
901 #define		MAX_POWER_DELTA_SHIFT			0
902 #define		STI_SIZE(x)				((x) << 16)
903 #define		STI_SIZE_MASK				(0x3ff << 16)
904 #define		STI_SIZE_SHIFT				16
905 #define		LTI_RATIO(x)				((x) << 27)
906 #define		LTI_RATIO_MASK				(0xf << 27)
907 #define		LTI_RATIO_SHIFT				27
908 
909 /* CG indirect registers */
910 #define CG_CAC_REGION_1_WEIGHT_0                        0x83
911 #define		WEIGHT_TCP_SIG0(x)			((x) << 0)
912 #define		WEIGHT_TCP_SIG0_MASK			(0x3f << 0)
913 #define		WEIGHT_TCP_SIG0_SHIFT			0
914 #define		WEIGHT_TCP_SIG1(x)			((x) << 6)
915 #define		WEIGHT_TCP_SIG1_MASK			(0x3f << 6)
916 #define		WEIGHT_TCP_SIG1_SHIFT			6
917 #define		WEIGHT_TA_SIG(x)			((x) << 12)
918 #define		WEIGHT_TA_SIG_MASK			(0x3f << 12)
919 #define		WEIGHT_TA_SIG_SHIFT			12
920 #define CG_CAC_REGION_1_WEIGHT_1                        0x84
921 #define		WEIGHT_TCC_EN0(x)			((x) << 0)
922 #define		WEIGHT_TCC_EN0_MASK			(0x3f << 0)
923 #define		WEIGHT_TCC_EN0_SHIFT			0
924 #define		WEIGHT_TCC_EN1(x)			((x) << 6)
925 #define		WEIGHT_TCC_EN1_MASK			(0x3f << 6)
926 #define		WEIGHT_TCC_EN1_SHIFT			6
927 #define		WEIGHT_TCC_EN2(x)			((x) << 12)
928 #define		WEIGHT_TCC_EN2_MASK			(0x3f << 12)
929 #define		WEIGHT_TCC_EN2_SHIFT			12
930 #define		WEIGHT_TCC_EN3(x)			((x) << 18)
931 #define		WEIGHT_TCC_EN3_MASK			(0x3f << 18)
932 #define		WEIGHT_TCC_EN3_SHIFT			18
933 #define CG_CAC_REGION_2_WEIGHT_0                        0x85
934 #define		WEIGHT_CB_EN0(x)			((x) << 0)
935 #define		WEIGHT_CB_EN0_MASK			(0x3f << 0)
936 #define		WEIGHT_CB_EN0_SHIFT			0
937 #define		WEIGHT_CB_EN1(x)			((x) << 6)
938 #define		WEIGHT_CB_EN1_MASK			(0x3f << 6)
939 #define		WEIGHT_CB_EN1_SHIFT			6
940 #define		WEIGHT_CB_EN2(x)			((x) << 12)
941 #define		WEIGHT_CB_EN2_MASK			(0x3f << 12)
942 #define		WEIGHT_CB_EN2_SHIFT			12
943 #define		WEIGHT_CB_EN3(x)			((x) << 18)
944 #define		WEIGHT_CB_EN3_MASK			(0x3f << 18)
945 #define		WEIGHT_CB_EN3_SHIFT			18
946 #define CG_CAC_REGION_2_WEIGHT_1                        0x86
947 #define		WEIGHT_DB_SIG0(x)			((x) << 0)
948 #define		WEIGHT_DB_SIG0_MASK			(0x3f << 0)
949 #define		WEIGHT_DB_SIG0_SHIFT			0
950 #define		WEIGHT_DB_SIG1(x)			((x) << 6)
951 #define		WEIGHT_DB_SIG1_MASK			(0x3f << 6)
952 #define		WEIGHT_DB_SIG1_SHIFT			6
953 #define		WEIGHT_DB_SIG2(x)			((x) << 12)
954 #define		WEIGHT_DB_SIG2_MASK			(0x3f << 12)
955 #define		WEIGHT_DB_SIG2_SHIFT			12
956 #define		WEIGHT_DB_SIG3(x)			((x) << 18)
957 #define		WEIGHT_DB_SIG3_MASK			(0x3f << 18)
958 #define		WEIGHT_DB_SIG3_SHIFT			18
959 #define CG_CAC_REGION_2_WEIGHT_2                        0x87
960 #define		WEIGHT_SXM_SIG0(x)			((x) << 0)
961 #define		WEIGHT_SXM_SIG0_MASK			(0x3f << 0)
962 #define		WEIGHT_SXM_SIG0_SHIFT			0
963 #define		WEIGHT_SXM_SIG1(x)			((x) << 6)
964 #define		WEIGHT_SXM_SIG1_MASK			(0x3f << 6)
965 #define		WEIGHT_SXM_SIG1_SHIFT			6
966 #define		WEIGHT_SXM_SIG2(x)			((x) << 12)
967 #define		WEIGHT_SXM_SIG2_MASK			(0x3f << 12)
968 #define		WEIGHT_SXM_SIG2_SHIFT			12
969 #define		WEIGHT_SXS_SIG0(x)			((x) << 18)
970 #define		WEIGHT_SXS_SIG0_MASK			(0x3f << 18)
971 #define		WEIGHT_SXS_SIG0_SHIFT			18
972 #define		WEIGHT_SXS_SIG1(x)			((x) << 24)
973 #define		WEIGHT_SXS_SIG1_MASK			(0x3f << 24)
974 #define		WEIGHT_SXS_SIG1_SHIFT			24
975 #define CG_CAC_REGION_3_WEIGHT_0                        0x88
976 #define		WEIGHT_XBR_0(x)				((x) << 0)
977 #define		WEIGHT_XBR_0_MASK			(0x3f << 0)
978 #define		WEIGHT_XBR_0_SHIFT			0
979 #define		WEIGHT_XBR_1(x)				((x) << 6)
980 #define		WEIGHT_XBR_1_MASK			(0x3f << 6)
981 #define		WEIGHT_XBR_1_SHIFT			6
982 #define		WEIGHT_XBR_2(x)				((x) << 12)
983 #define		WEIGHT_XBR_2_MASK			(0x3f << 12)
984 #define		WEIGHT_XBR_2_SHIFT			12
985 #define		WEIGHT_SPI_SIG0(x)			((x) << 18)
986 #define		WEIGHT_SPI_SIG0_MASK			(0x3f << 18)
987 #define		WEIGHT_SPI_SIG0_SHIFT			18
988 #define CG_CAC_REGION_3_WEIGHT_1                        0x89
989 #define		WEIGHT_SPI_SIG1(x)			((x) << 0)
990 #define		WEIGHT_SPI_SIG1_MASK			(0x3f << 0)
991 #define		WEIGHT_SPI_SIG1_SHIFT			0
992 #define		WEIGHT_SPI_SIG2(x)			((x) << 6)
993 #define		WEIGHT_SPI_SIG2_MASK			(0x3f << 6)
994 #define		WEIGHT_SPI_SIG2_SHIFT			6
995 #define		WEIGHT_SPI_SIG3(x)			((x) << 12)
996 #define		WEIGHT_SPI_SIG3_MASK			(0x3f << 12)
997 #define		WEIGHT_SPI_SIG3_SHIFT			12
998 #define		WEIGHT_SPI_SIG4(x)			((x) << 18)
999 #define		WEIGHT_SPI_SIG4_MASK			(0x3f << 18)
1000 #define		WEIGHT_SPI_SIG4_SHIFT			18
1001 #define		WEIGHT_SPI_SIG5(x)			((x) << 24)
1002 #define		WEIGHT_SPI_SIG5_MASK			(0x3f << 24)
1003 #define		WEIGHT_SPI_SIG5_SHIFT			24
1004 #define CG_CAC_REGION_4_WEIGHT_0                        0x8a
1005 #define		WEIGHT_LDS_SIG0(x)			((x) << 0)
1006 #define		WEIGHT_LDS_SIG0_MASK			(0x3f << 0)
1007 #define		WEIGHT_LDS_SIG0_SHIFT			0
1008 #define		WEIGHT_LDS_SIG1(x)			((x) << 6)
1009 #define		WEIGHT_LDS_SIG1_MASK			(0x3f << 6)
1010 #define		WEIGHT_LDS_SIG1_SHIFT			6
1011 #define		WEIGHT_SC(x)				((x) << 24)
1012 #define		WEIGHT_SC_MASK				(0x3f << 24)
1013 #define		WEIGHT_SC_SHIFT				24
1014 #define CG_CAC_REGION_4_WEIGHT_1                        0x8b
1015 #define		WEIGHT_BIF(x)				((x) << 0)
1016 #define		WEIGHT_BIF_MASK				(0x3f << 0)
1017 #define		WEIGHT_BIF_SHIFT			0
1018 #define		WEIGHT_CP(x)				((x) << 6)
1019 #define		WEIGHT_CP_MASK				(0x3f << 6)
1020 #define		WEIGHT_CP_SHIFT				6
1021 #define		WEIGHT_PA_SIG0(x)			((x) << 12)
1022 #define		WEIGHT_PA_SIG0_MASK			(0x3f << 12)
1023 #define		WEIGHT_PA_SIG0_SHIFT			12
1024 #define		WEIGHT_PA_SIG1(x)			((x) << 18)
1025 #define		WEIGHT_PA_SIG1_MASK			(0x3f << 18)
1026 #define		WEIGHT_PA_SIG1_SHIFT			18
1027 #define		WEIGHT_VGT_SIG0(x)			((x) << 24)
1028 #define		WEIGHT_VGT_SIG0_MASK			(0x3f << 24)
1029 #define		WEIGHT_VGT_SIG0_SHIFT			24
1030 #define CG_CAC_REGION_4_WEIGHT_2                        0x8c
1031 #define		WEIGHT_VGT_SIG1(x)			((x) << 0)
1032 #define		WEIGHT_VGT_SIG1_MASK			(0x3f << 0)
1033 #define		WEIGHT_VGT_SIG1_SHIFT			0
1034 #define		WEIGHT_VGT_SIG2(x)			((x) << 6)
1035 #define		WEIGHT_VGT_SIG2_MASK			(0x3f << 6)
1036 #define		WEIGHT_VGT_SIG2_SHIFT			6
1037 #define		WEIGHT_DC_SIG0(x)			((x) << 12)
1038 #define		WEIGHT_DC_SIG0_MASK			(0x3f << 12)
1039 #define		WEIGHT_DC_SIG0_SHIFT			12
1040 #define		WEIGHT_DC_SIG1(x)			((x) << 18)
1041 #define		WEIGHT_DC_SIG1_MASK			(0x3f << 18)
1042 #define		WEIGHT_DC_SIG1_SHIFT			18
1043 #define		WEIGHT_DC_SIG2(x)			((x) << 24)
1044 #define		WEIGHT_DC_SIG2_MASK			(0x3f << 24)
1045 #define		WEIGHT_DC_SIG2_SHIFT			24
1046 #define CG_CAC_REGION_4_WEIGHT_3                        0x8d
1047 #define		WEIGHT_DC_SIG3(x)			((x) << 0)
1048 #define		WEIGHT_DC_SIG3_MASK			(0x3f << 0)
1049 #define		WEIGHT_DC_SIG3_SHIFT			0
1050 #define		WEIGHT_UVD_SIG0(x)			((x) << 6)
1051 #define		WEIGHT_UVD_SIG0_MASK			(0x3f << 6)
1052 #define		WEIGHT_UVD_SIG0_SHIFT			6
1053 #define		WEIGHT_UVD_SIG1(x)			((x) << 12)
1054 #define		WEIGHT_UVD_SIG1_MASK			(0x3f << 12)
1055 #define		WEIGHT_UVD_SIG1_SHIFT			12
1056 #define		WEIGHT_SPARE0(x)			((x) << 18)
1057 #define		WEIGHT_SPARE0_MASK			(0x3f << 18)
1058 #define		WEIGHT_SPARE0_SHIFT			18
1059 #define		WEIGHT_SPARE1(x)			((x) << 24)
1060 #define		WEIGHT_SPARE1_MASK			(0x3f << 24)
1061 #define		WEIGHT_SPARE1_SHIFT			24
1062 #define CG_CAC_REGION_5_WEIGHT_0                        0x8e
1063 #define		WEIGHT_SQ_VSP(x)			((x) << 0)
1064 #define		WEIGHT_SQ_VSP_MASK			(0x3fff << 0)
1065 #define		WEIGHT_SQ_VSP_SHIFT			0
1066 #define		WEIGHT_SQ_VSP0(x)			((x) << 14)
1067 #define		WEIGHT_SQ_VSP0_MASK			(0x3fff << 14)
1068 #define		WEIGHT_SQ_VSP0_SHIFT			14
1069 #define CG_CAC_REGION_4_OVERRIDE_4                      0xab
1070 #define		OVR_MODE_SPARE_0(x)			((x) << 16)
1071 #define		OVR_MODE_SPARE_0_MASK			(0x1 << 16)
1072 #define		OVR_MODE_SPARE_0_SHIFT			16
1073 #define		OVR_VAL_SPARE_0(x)			((x) << 17)
1074 #define		OVR_VAL_SPARE_0_MASK			(0x1 << 17)
1075 #define		OVR_VAL_SPARE_0_SHIFT			17
1076 #define		OVR_MODE_SPARE_1(x)			((x) << 18)
1077 #define		OVR_MODE_SPARE_1_MASK			(0x3f << 18)
1078 #define		OVR_MODE_SPARE_1_SHIFT			18
1079 #define		OVR_VAL_SPARE_1(x)			((x) << 19)
1080 #define		OVR_VAL_SPARE_1_MASK			(0x3f << 19)
1081 #define		OVR_VAL_SPARE_1_SHIFT			19
1082 #define CG_CAC_REGION_5_WEIGHT_1                        0xb7
1083 #define		WEIGHT_SQ_GPR(x)			((x) << 0)
1084 #define		WEIGHT_SQ_GPR_MASK			(0x3fff << 0)
1085 #define		WEIGHT_SQ_GPR_SHIFT			0
1086 #define		WEIGHT_SQ_LDS(x)			((x) << 14)
1087 #define		WEIGHT_SQ_LDS_MASK			(0x3fff << 14)
1088 #define		WEIGHT_SQ_LDS_SHIFT			14
1089 
1090 /* PCIE link stuff */
1091 #define PCIE_LC_TRAINING_CNTL                             0xa1 /* PCIE_P */
1092 #define PCIE_LC_LINK_WIDTH_CNTL                           0xa2 /* PCIE_P */
1093 #       define LC_LINK_WIDTH_SHIFT                        0
1094 #       define LC_LINK_WIDTH_MASK                         0x7
1095 #       define LC_LINK_WIDTH_X0                           0
1096 #       define LC_LINK_WIDTH_X1                           1
1097 #       define LC_LINK_WIDTH_X2                           2
1098 #       define LC_LINK_WIDTH_X4                           3
1099 #       define LC_LINK_WIDTH_X8                           4
1100 #       define LC_LINK_WIDTH_X16                          6
1101 #       define LC_LINK_WIDTH_RD_SHIFT                     4
1102 #       define LC_LINK_WIDTH_RD_MASK                      0x70
1103 #       define LC_RECONFIG_ARC_MISSING_ESCAPE             (1 << 7)
1104 #       define LC_RECONFIG_NOW                            (1 << 8)
1105 #       define LC_RENEGOTIATION_SUPPORT                   (1 << 9)
1106 #       define LC_RENEGOTIATE_EN                          (1 << 10)
1107 #       define LC_SHORT_RECONFIG_EN                       (1 << 11)
1108 #       define LC_UPCONFIGURE_SUPPORT                     (1 << 12)
1109 #       define LC_UPCONFIGURE_DIS                         (1 << 13)
1110 #define PCIE_LC_SPEED_CNTL                                0xa4 /* PCIE_P */
1111 #       define LC_GEN2_EN_STRAP                           (1 << 0)
1112 #       define LC_TARGET_LINK_SPEED_OVERRIDE_EN           (1 << 1)
1113 #       define LC_FORCE_EN_HW_SPEED_CHANGE                (1 << 5)
1114 #       define LC_FORCE_DIS_HW_SPEED_CHANGE               (1 << 6)
1115 #       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK      (0x3 << 8)
1116 #       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT     3
1117 #       define LC_CURRENT_DATA_RATE                       (1 << 11)
1118 #       define LC_HW_VOLTAGE_IF_CONTROL(x)                ((x) << 12)
1119 #       define LC_HW_VOLTAGE_IF_CONTROL_MASK              (3 << 12)
1120 #       define LC_HW_VOLTAGE_IF_CONTROL_SHIFT             12
1121 #       define LC_VOLTAGE_TIMER_SEL_MASK                  (0xf << 14)
1122 #       define LC_CLR_FAILED_SPD_CHANGE_CNT               (1 << 21)
1123 #       define LC_OTHER_SIDE_EVER_SENT_GEN2               (1 << 23)
1124 #       define LC_OTHER_SIDE_SUPPORTS_GEN2                (1 << 24)
1125 #define MM_CFGREGS_CNTL                                   0x544c
1126 #       define MM_WR_TO_CFG_EN                            (1 << 3)
1127 #define LINK_CNTL2                                        0x88 /* F0 */
1128 #       define TARGET_LINK_SPEED_MASK                     (0xf << 0)
1129 #       define SELECTABLE_DEEMPHASIS                      (1 << 6)
1130 
1131 /*
1132  * UVD
1133  */
1134 #define UVD_SEMA_ADDR_LOW				0xEF00
1135 #define UVD_SEMA_ADDR_HIGH				0xEF04
1136 #define UVD_SEMA_CMD					0xEF08
1137 #define UVD_UDEC_ADDR_CONFIG				0xEF4C
1138 #define UVD_UDEC_DB_ADDR_CONFIG				0xEF50
1139 #define UVD_UDEC_DBW_ADDR_CONFIG			0xEF54
1140 #define UVD_NO_OP					0xEFFC
1141 #define UVD_RBC_RB_RPTR					0xF690
1142 #define UVD_RBC_RB_WPTR					0xF694
1143 #define UVD_STATUS					0xf6bc
1144 
1145 /*
1146  * PM4
1147  */
1148 #define PACKET0(reg, n)	((RADEON_PACKET_TYPE0 << 30) |			\
1149 			 (((reg) >> 2) & 0xFFFF) |			\
1150 			 ((n) & 0x3FFF) << 16)
1151 #define CP_PACKET2			0x80000000
1152 #define		PACKET2_PAD_SHIFT		0
1153 #define		PACKET2_PAD_MASK		(0x3fffffff << 0)
1154 
1155 #define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
1156 
1157 #define PACKET3(op, n)	((RADEON_PACKET_TYPE3 << 30) |			\
1158 			 (((op) & 0xFF) << 8) |				\
1159 			 ((n) & 0x3FFF) << 16)
1160 
1161 /* Packet 3 types */
1162 #define	PACKET3_NOP					0x10
1163 #define	PACKET3_SET_BASE				0x11
1164 #define	PACKET3_CLEAR_STATE				0x12
1165 #define	PACKET3_INDEX_BUFFER_SIZE			0x13
1166 #define	PACKET3_DEALLOC_STATE				0x14
1167 #define	PACKET3_DISPATCH_DIRECT				0x15
1168 #define	PACKET3_DISPATCH_INDIRECT			0x16
1169 #define	PACKET3_INDIRECT_BUFFER_END			0x17
1170 #define	PACKET3_MODE_CONTROL				0x18
1171 #define	PACKET3_SET_PREDICATION				0x20
1172 #define	PACKET3_REG_RMW					0x21
1173 #define	PACKET3_COND_EXEC				0x22
1174 #define	PACKET3_PRED_EXEC				0x23
1175 #define	PACKET3_DRAW_INDIRECT				0x24
1176 #define	PACKET3_DRAW_INDEX_INDIRECT			0x25
1177 #define	PACKET3_INDEX_BASE				0x26
1178 #define	PACKET3_DRAW_INDEX_2				0x27
1179 #define	PACKET3_CONTEXT_CONTROL				0x28
1180 #define	PACKET3_DRAW_INDEX_OFFSET			0x29
1181 #define	PACKET3_INDEX_TYPE				0x2A
1182 #define	PACKET3_DRAW_INDEX				0x2B
1183 #define	PACKET3_DRAW_INDEX_AUTO				0x2D
1184 #define	PACKET3_DRAW_INDEX_IMMD				0x2E
1185 #define	PACKET3_NUM_INSTANCES				0x2F
1186 #define	PACKET3_DRAW_INDEX_MULTI_AUTO			0x30
1187 #define	PACKET3_INDIRECT_BUFFER				0x32
1188 #define	PACKET3_STRMOUT_BUFFER_UPDATE			0x34
1189 #define	PACKET3_DRAW_INDEX_OFFSET_2			0x35
1190 #define	PACKET3_DRAW_INDEX_MULTI_ELEMENT		0x36
1191 #define	PACKET3_WRITE_DATA				0x37
1192 #define	PACKET3_MEM_SEMAPHORE				0x39
1193 #define	PACKET3_MPEG_INDEX				0x3A
1194 #define	PACKET3_WAIT_REG_MEM				0x3C
1195 #define		WAIT_REG_MEM_FUNCTION(x)                ((x) << 0)
1196                 /* 0 - always
1197 		 * 1 - <
1198 		 * 2 - <=
1199 		 * 3 - ==
1200 		 * 4 - !=
1201 		 * 5 - >=
1202 		 * 6 - >
1203 		 */
1204 #define		WAIT_REG_MEM_MEM_SPACE(x)               ((x) << 4)
1205                 /* 0 - reg
1206 		 * 1 - mem
1207 		 */
1208 #define		WAIT_REG_MEM_ENGINE(x)                  ((x) << 8)
1209                 /* 0 - me
1210 		 * 1 - pfp
1211 		 */
1212 #define	PACKET3_MEM_WRITE				0x3D
1213 #define	PACKET3_PFP_SYNC_ME				0x42
1214 #define	PACKET3_SURFACE_SYNC				0x43
1215 #              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
1216 #              define PACKET3_CB1_DEST_BASE_ENA    (1 << 7)
1217 #              define PACKET3_CB2_DEST_BASE_ENA    (1 << 8)
1218 #              define PACKET3_CB3_DEST_BASE_ENA    (1 << 9)
1219 #              define PACKET3_CB4_DEST_BASE_ENA    (1 << 10)
1220 #              define PACKET3_CB5_DEST_BASE_ENA    (1 << 11)
1221 #              define PACKET3_CB6_DEST_BASE_ENA    (1 << 12)
1222 #              define PACKET3_CB7_DEST_BASE_ENA    (1 << 13)
1223 #              define PACKET3_DB_DEST_BASE_ENA     (1 << 14)
1224 #              define PACKET3_CB8_DEST_BASE_ENA    (1 << 15)
1225 #              define PACKET3_CB9_DEST_BASE_ENA    (1 << 16)
1226 #              define PACKET3_CB10_DEST_BASE_ENA   (1 << 17)
1227 #              define PACKET3_CB11_DEST_BASE_ENA   (1 << 18)
1228 #              define PACKET3_FULL_CACHE_ENA       (1 << 20)
1229 #              define PACKET3_TC_ACTION_ENA        (1 << 23)
1230 #              define PACKET3_CB_ACTION_ENA        (1 << 25)
1231 #              define PACKET3_DB_ACTION_ENA        (1 << 26)
1232 #              define PACKET3_SH_ACTION_ENA        (1 << 27)
1233 #              define PACKET3_SX_ACTION_ENA        (1 << 28)
1234 #              define PACKET3_ENGINE_ME            (1 << 31)
1235 #define	PACKET3_ME_INITIALIZE				0x44
1236 #define		PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1237 #define	PACKET3_COND_WRITE				0x45
1238 #define	PACKET3_EVENT_WRITE				0x46
1239 #define		EVENT_TYPE(x)                           ((x) << 0)
1240 #define		EVENT_INDEX(x)                          ((x) << 8)
1241                 /* 0 - any non-TS event
1242 		 * 1 - ZPASS_DONE
1243 		 * 2 - SAMPLE_PIPELINESTAT
1244 		 * 3 - SAMPLE_STREAMOUTSTAT*
1245 		 * 4 - *S_PARTIAL_FLUSH
1246 		 * 5 - TS events
1247 		 */
1248 #define	PACKET3_EVENT_WRITE_EOP				0x47
1249 #define		DATA_SEL(x)                             ((x) << 29)
1250                 /* 0 - discard
1251 		 * 1 - send low 32bit data
1252 		 * 2 - send 64bit data
1253 		 * 3 - send 64bit counter value
1254 		 */
1255 #define		INT_SEL(x)                              ((x) << 24)
1256                 /* 0 - none
1257 		 * 1 - interrupt only (DATA_SEL = 0)
1258 		 * 2 - interrupt when data write is confirmed
1259 		 */
1260 #define	PACKET3_EVENT_WRITE_EOS				0x48
1261 #define	PACKET3_PREAMBLE_CNTL				0x4A
1262 #              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
1263 #              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)
1264 #define	PACKET3_ALU_PS_CONST_BUFFER_COPY		0x4C
1265 #define	PACKET3_ALU_VS_CONST_BUFFER_COPY		0x4D
1266 #define	PACKET3_ALU_PS_CONST_UPDATE		        0x4E
1267 #define	PACKET3_ALU_VS_CONST_UPDATE		        0x4F
1268 #define	PACKET3_ONE_REG_WRITE				0x57
1269 #define	PACKET3_SET_CONFIG_REG				0x68
1270 #define		PACKET3_SET_CONFIG_REG_START			0x00008000
1271 #define		PACKET3_SET_CONFIG_REG_END			0x0000ac00
1272 #define	PACKET3_SET_CONTEXT_REG				0x69
1273 #define		PACKET3_SET_CONTEXT_REG_START			0x00028000
1274 #define		PACKET3_SET_CONTEXT_REG_END			0x00029000
1275 #define	PACKET3_SET_ALU_CONST				0x6A
1276 /* alu const buffers only; no reg file */
1277 #define	PACKET3_SET_BOOL_CONST				0x6B
1278 #define		PACKET3_SET_BOOL_CONST_START			0x0003a500
1279 #define		PACKET3_SET_BOOL_CONST_END			0x0003a518
1280 #define	PACKET3_SET_LOOP_CONST				0x6C
1281 #define		PACKET3_SET_LOOP_CONST_START			0x0003a200
1282 #define		PACKET3_SET_LOOP_CONST_END			0x0003a500
1283 #define	PACKET3_SET_RESOURCE				0x6D
1284 #define		PACKET3_SET_RESOURCE_START			0x00030000
1285 #define		PACKET3_SET_RESOURCE_END			0x00038000
1286 #define	PACKET3_SET_SAMPLER				0x6E
1287 #define		PACKET3_SET_SAMPLER_START			0x0003c000
1288 #define		PACKET3_SET_SAMPLER_END				0x0003c600
1289 #define	PACKET3_SET_CTL_CONST				0x6F
1290 #define		PACKET3_SET_CTL_CONST_START			0x0003cff0
1291 #define		PACKET3_SET_CTL_CONST_END			0x0003ff0c
1292 #define	PACKET3_SET_RESOURCE_OFFSET			0x70
1293 #define	PACKET3_SET_ALU_CONST_VS			0x71
1294 #define	PACKET3_SET_ALU_CONST_DI			0x72
1295 #define	PACKET3_SET_CONTEXT_REG_INDIRECT		0x73
1296 #define	PACKET3_SET_RESOURCE_INDIRECT			0x74
1297 #define	PACKET3_SET_APPEND_CNT			        0x75
1298 #define	PACKET3_ME_WRITE				0x7A
1299 
1300 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
1301 #define DMA0_REGISTER_OFFSET                              0x0 /* not a register */
1302 #define DMA1_REGISTER_OFFSET                              0x800 /* not a register */
1303 
1304 #define DMA_RB_CNTL                                       0xd000
1305 #       define DMA_RB_ENABLE                              (1 << 0)
1306 #       define DMA_RB_SIZE(x)                             ((x) << 1) /* log2 */
1307 #       define DMA_RB_SWAP_ENABLE                         (1 << 9) /* 8IN32 */
1308 #       define DMA_RPTR_WRITEBACK_ENABLE                  (1 << 12)
1309 #       define DMA_RPTR_WRITEBACK_SWAP_ENABLE             (1 << 13)  /* 8IN32 */
1310 #       define DMA_RPTR_WRITEBACK_TIMER(x)                ((x) << 16) /* log2 */
1311 #define DMA_RB_BASE                                       0xd004
1312 #define DMA_RB_RPTR                                       0xd008
1313 #define DMA_RB_WPTR                                       0xd00c
1314 
1315 #define DMA_RB_RPTR_ADDR_HI                               0xd01c
1316 #define DMA_RB_RPTR_ADDR_LO                               0xd020
1317 
1318 #define DMA_IB_CNTL                                       0xd024
1319 #       define DMA_IB_ENABLE                              (1 << 0)
1320 #       define DMA_IB_SWAP_ENABLE                         (1 << 4)
1321 #       define CMD_VMID_FORCE                             (1 << 31)
1322 #define DMA_IB_RPTR                                       0xd028
1323 #define DMA_CNTL                                          0xd02c
1324 #       define TRAP_ENABLE                                (1 << 0)
1325 #       define SEM_INCOMPLETE_INT_ENABLE                  (1 << 1)
1326 #       define SEM_WAIT_INT_ENABLE                        (1 << 2)
1327 #       define DATA_SWAP_ENABLE                           (1 << 3)
1328 #       define FENCE_SWAP_ENABLE                          (1 << 4)
1329 #       define CTXEMPTY_INT_ENABLE                        (1 << 28)
1330 #define DMA_STATUS_REG                                    0xd034
1331 #       define DMA_IDLE                                   (1 << 0)
1332 #define DMA_SEM_INCOMPLETE_TIMER_CNTL                     0xd044
1333 #define DMA_SEM_WAIT_FAIL_TIMER_CNTL                      0xd048
1334 #define DMA_TILING_CONFIG  				  0xd0b8
1335 #define DMA_MODE                                          0xd0bc
1336 
1337 #define DMA_PACKET(cmd, t, s, n)	((((cmd) & 0xF) << 28) |	\
1338 					 (((t) & 0x1) << 23) |		\
1339 					 (((s) & 0x1) << 22) |		\
1340 					 (((n) & 0xFFFFF) << 0))
1341 
1342 #define DMA_IB_PACKET(cmd, vmid, n)	((((cmd) & 0xF) << 28) |	\
1343 					 (((vmid) & 0xF) << 20) |	\
1344 					 (((n) & 0xFFFFF) << 0))
1345 
1346 #define DMA_PTE_PDE_PACKET(n)		((2 << 28) |			\
1347 					 (1 << 26) |			\
1348 					 (1 << 21) |			\
1349 					 (((n) & 0xFFFFF) << 0))
1350 
1351 #define DMA_SRBM_POLL_PACKET		((9 << 28) |			\
1352 					 (1 << 27) |			\
1353 					 (1 << 26))
1354 
1355 #define DMA_SRBM_READ_PACKET		((9 << 28) |			\
1356 					 (1 << 27))
1357 
1358 /* async DMA Packet types */
1359 #define	DMA_PACKET_WRITE				  0x2
1360 #define	DMA_PACKET_COPY					  0x3
1361 #define	DMA_PACKET_INDIRECT_BUFFER			  0x4
1362 #define	DMA_PACKET_SEMAPHORE				  0x5
1363 #define	DMA_PACKET_FENCE				  0x6
1364 #define	DMA_PACKET_TRAP					  0x7
1365 #define	DMA_PACKET_SRBM_WRITE				  0x9
1366 #define	DMA_PACKET_CONSTANT_FILL			  0xd
1367 #define	DMA_PACKET_NOP					  0xf
1368 
1369 #endif
1370