xref: /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_pptable.h (revision a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0)
1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef _VEGA20_PPTABLE_H_
24 #define _VEGA20_PPTABLE_H_
25 
26 #pragma pack(push, 1)
27 
28 #define ATOM_VEGA20_PP_THERMALCONTROLLER_NONE           0
29 #define ATOM_VEGA20_PP_THERMALCONTROLLER_VEGA20     26
30 
31 #define ATOM_VEGA20_PP_PLATFORM_CAP_POWERPLAY                   0x1
32 #define ATOM_VEGA20_PP_PLATFORM_CAP_SBIOSPOWERSOURCE            0x2
33 #define ATOM_VEGA20_PP_PLATFORM_CAP_HARDWAREDC                  0x4
34 #define ATOM_VEGA20_PP_PLATFORM_CAP_BACO                        0x8
35 #define ATOM_VEGA20_PP_PLATFORM_CAP_BAMACO                      0x10
36 #define ATOM_VEGA20_PP_PLATFORM_CAP_ENABLESHADOWPSTATE          0x20
37 
38 #define ATOM_VEGA20_TABLE_REVISION_VEGA20         11
39 #define ATOM_VEGA20_ODFEATURE_MAX_COUNT         32
40 #define ATOM_VEGA20_ODSETTING_MAX_COUNT         32
41 #define ATOM_VEGA20_PPCLOCK_MAX_COUNT           16
42 
43 enum ATOM_VEGA20_ODFEATURE_ID {
44   ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS = 0,
45   ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE,
46   ATOM_VEGA20_ODFEATURE_UCLK_MAX,
47   ATOM_VEGA20_ODFEATURE_POWER_LIMIT,
48   ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT,    //FanMaximumRpm
49   ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN,         //FanMinimumPwm
50   ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN,       //FanTargetTemperature
51   ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM,    //MaxOpTemp
52   ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE,
53   ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL,
54   ATOM_VEGA20_ODFEATURE_COUNT,
55 };
56 
57 enum ATOM_VEGA20_ODSETTING_ID {
58   ATOM_VEGA20_ODSETTING_GFXCLKFMAX = 0,
59   ATOM_VEGA20_ODSETTING_GFXCLKFMIN,
60   ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P1,
61   ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P1,
62   ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P2,
63   ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P2,
64   ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P3,
65   ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P3,
66   ATOM_VEGA20_ODSETTING_UCLKFMAX,
67   ATOM_VEGA20_ODSETTING_POWERPERCENTAGE,
68   ATOM_VEGA20_ODSETTING_FANRPMMIN,
69   ATOM_VEGA20_ODSETTING_FANRPMACOUSTICLIMIT,
70   ATOM_VEGA20_ODSETTING_FANTARGETTEMPERATURE,
71   ATOM_VEGA20_ODSETTING_OPERATINGTEMPMAX,
72   ATOM_VEGA20_ODSETTING_COUNT,
73 };
74 typedef enum ATOM_VEGA20_ODSETTING_ID ATOM_VEGA20_ODSETTING_ID;
75 
76 typedef struct _ATOM_VEGA20_OVERDRIVE8_RECORD {
77   UCHAR ucODTableRevision;
78   ULONG ODFeatureCount;
79   UCHAR ODFeatureCapabilities[ATOM_VEGA20_ODFEATURE_MAX_COUNT];   //OD feature support flags
80   ULONG ODSettingCount;
81   ULONG ODSettingsMax[ATOM_VEGA20_ODSETTING_MAX_COUNT];           //Upper Limit for each OD Setting
82   ULONG ODSettingsMin[ATOM_VEGA20_ODSETTING_MAX_COUNT];           //Lower Limit for each OD Setting
83 } ATOM_VEGA20_OVERDRIVE8_RECORD;
84 
85 enum ATOM_VEGA20_PPCLOCK_ID {
86   ATOM_VEGA20_PPCLOCK_GFXCLK = 0,
87   ATOM_VEGA20_PPCLOCK_VCLK,
88   ATOM_VEGA20_PPCLOCK_DCLK,
89   ATOM_VEGA20_PPCLOCK_ECLK,
90   ATOM_VEGA20_PPCLOCK_SOCCLK,
91   ATOM_VEGA20_PPCLOCK_UCLK,
92   ATOM_VEGA20_PPCLOCK_FCLK,
93   ATOM_VEGA20_PPCLOCK_DCEFCLK,
94   ATOM_VEGA20_PPCLOCK_DISPCLK,
95   ATOM_VEGA20_PPCLOCK_PIXCLK,
96   ATOM_VEGA20_PPCLOCK_PHYCLK,
97   ATOM_VEGA20_PPCLOCK_COUNT,
98 };
99 typedef enum ATOM_VEGA20_PPCLOCK_ID ATOM_VEGA20_PPCLOCK_ID;
100 
101 typedef struct _ATOM_VEGA20_POWER_SAVING_CLOCK_RECORD {
102   UCHAR ucTableRevision;
103   ULONG PowerSavingClockCount;                                 // Count of PowerSavingClock Mode
104   ULONG PowerSavingClockMax[ATOM_VEGA20_PPCLOCK_MAX_COUNT];      // PowerSavingClock Mode Clock Maximum array In MHz
105   ULONG PowerSavingClockMin[ATOM_VEGA20_PPCLOCK_MAX_COUNT];      // PowerSavingClock Mode Clock Minimum array In MHz
106 } ATOM_VEGA20_POWER_SAVING_CLOCK_RECORD;
107 
108 typedef struct _ATOM_VEGA20_POWERPLAYTABLE {
109       struct atom_common_table_header sHeader;
110       UCHAR  ucTableRevision;
111       USHORT usTableSize;
112       ULONG  ulGoldenPPID;
113       ULONG  ulGoldenRevision;
114       USHORT usFormatID;
115 
116       ULONG  ulPlatformCaps;
117 
118       UCHAR  ucThermalControllerType;
119 
120       USHORT usSmallPowerLimit1;
121       USHORT usSmallPowerLimit2;
122       USHORT usBoostPowerLimit;
123       USHORT usODTurboPowerLimit;
124       USHORT usODPowerSavePowerLimit;
125       USHORT usSoftwareShutdownTemp;
126 
127       ATOM_VEGA20_POWER_SAVING_CLOCK_RECORD PowerSavingClockTable;    //PowerSavingClock Mode Clock Min/Max array
128 
129       ATOM_VEGA20_OVERDRIVE8_RECORD OverDrive8Table;       //OverDrive8 Feature capabilities and Settings Range (Max and Min)
130 
131       USHORT usReserve[5];
132 
133       PPTable_t smcPPTable;
134 
135 } ATOM_Vega20_POWERPLAYTABLE;
136 
137 #pragma pack(pop)
138 
139 #endif
140