1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for the ADC present in the Atmel AT91 evaluation boards.
4 *
5 * Copyright 2011 Free Electrons
6 */
7
8 #include <linux/bitmap.h>
9 #include <linux/bitops.h>
10 #include <linux/cleanup.h>
11 #include <linux/clk.h>
12 #include <linux/err.h>
13 #include <linux/io.h>
14 #include <linux/input.h>
15 #include <linux/interrupt.h>
16 #include <linux/jiffies.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/platform_device.h>
21 #include <linux/sched.h>
22 #include <linux/slab.h>
23 #include <linux/wait.h>
24
25 #include <linux/iio/iio.h>
26 #include <linux/iio/buffer.h>
27 #include <linux/iio/trigger.h>
28 #include <linux/iio/trigger_consumer.h>
29 #include <linux/iio/triggered_buffer.h>
30 #include <linux/pinctrl/consumer.h>
31
32 /* Registers */
33 #define AT91_ADC_CR 0x00 /* Control Register */
34 #define AT91_ADC_SWRST (1 << 0) /* Software Reset */
35 #define AT91_ADC_START (1 << 1) /* Start Conversion */
36
37 #define AT91_ADC_MR 0x04 /* Mode Register */
38 #define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */
39 #define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */
40 #define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */
41 #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */
42 #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */
43 #define AT91_ADC_TRGSEL_TC0 (0 << 1)
44 #define AT91_ADC_TRGSEL_TC1 (1 << 1)
45 #define AT91_ADC_TRGSEL_TC2 (2 << 1)
46 #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
47 #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */
48 #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */
49 #define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */
50 #define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */
51 #define AT91_ADC_PRESCAL_9G45 (0xff << 8)
52 #define AT91_ADC_PRESCAL_(x) ((x) << 8)
53 #define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */
54 #define AT91_ADC_STARTUP_9G45 (0x7f << 16)
55 #define AT91_ADC_STARTUP_9X5 (0xf << 16)
56 #define AT91_ADC_STARTUP_(x) ((x) << 16)
57 #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */
58 #define AT91_ADC_SHTIM_(x) ((x) << 24)
59 #define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */
60 #define AT91_ADC_PENDBC_(x) ((x) << 28)
61
62 #define AT91_ADC_TSR 0x0C
63 #define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */
64 #define AT91_ADC_TSR_SHTIM_(x) ((x) << 24)
65
66 #define AT91_ADC_CHER 0x10 /* Channel Enable Register */
67 #define AT91_ADC_CHDR 0x14 /* Channel Disable Register */
68 #define AT91_ADC_CHSR 0x18 /* Channel Status Register */
69 #define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */
70
71 #define AT91_ADC_SR 0x1C /* Status Register */
72 #define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */
73 #define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */
74 #define AT91_ADC_DRDY (1 << 16) /* Data Ready */
75 #define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */
76 #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */
77 #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */
78
79 #define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */
80 #define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */
81
82 #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */
83 #define AT91_ADC_LDATA (0x3ff)
84
85 #define AT91_ADC_IER 0x24 /* Interrupt Enable Register */
86 #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */
87 #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */
88 #define AT91RL_ADC_IER_PEN (1 << 20)
89 #define AT91RL_ADC_IER_NOPEN (1 << 21)
90 #define AT91_ADC_IER_PEN (1 << 29)
91 #define AT91_ADC_IER_NOPEN (1 << 30)
92 #define AT91_ADC_IER_XRDY (1 << 20)
93 #define AT91_ADC_IER_YRDY (1 << 21)
94 #define AT91_ADC_IER_PRDY (1 << 22)
95 #define AT91_ADC_ISR_PENS (1 << 31)
96
97 #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */
98 #define AT91_ADC_DATA (0x3ff)
99
100 #define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */
101
102 #define AT91_ADC_ACR 0x94 /* Analog Control Register */
103 #define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */
104
105 #define AT91_ADC_TSMR 0xB0
106 #define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */
107 #define AT91_ADC_TSMR_TSMODE_NONE (0 << 0)
108 #define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0)
109 #define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0)
110 #define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0)
111 #define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */
112 #define AT91_ADC_TSMR_TSAV_(x) ((x) << 4)
113 #define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */
114 #define AT91_ADC_TSMR_SCTIM_(x) ((x) << 16)
115 #define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */
116 #define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28)
117 #define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */
118 #define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */
119 #define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */
120
121 #define AT91_ADC_TSXPOSR 0xB4
122 #define AT91_ADC_TSYPOSR 0xB8
123 #define AT91_ADC_TSPRESSR 0xBC
124
125 #define AT91_ADC_TRGR_9260 AT91_ADC_MR
126 #define AT91_ADC_TRGR_9G45 0x08
127 #define AT91_ADC_TRGR_9X5 0xC0
128
129 /* Trigger Register bit field */
130 #define AT91_ADC_TRGR_TRGPER (0xffff << 16)
131 #define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16)
132 #define AT91_ADC_TRGR_TRGMOD (0x7 << 0)
133 #define AT91_ADC_TRGR_NONE (0 << 0)
134 #define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0)
135
136 #define AT91_ADC_CHAN(st, ch) \
137 (st->registers->channel_base + (ch * 4))
138 #define at91_adc_readl(st, reg) \
139 (readl_relaxed(st->reg_base + reg))
140 #define at91_adc_writel(st, reg, val) \
141 (writel_relaxed(val, st->reg_base + reg))
142
143 #define DRIVER_NAME "at91_adc"
144 #define MAX_POS_BITS 12
145
146 #define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
147 #define TOUCH_PEN_DETECT_DEBOUNCE_US 200
148
149 #define MAX_RLPOS_BITS 10
150 #define TOUCH_SAMPLE_PERIOD_US_RL 10000 /* 10ms, the SoC can't keep up with 2ms */
151 #define TOUCH_SHTIM 0xa
152 #define TOUCH_SCTIM_US 10 /* 10us for the Touchscreen Switches Closure Time */
153
154 enum atmel_adc_ts_type {
155 ATMEL_ADC_TOUCHSCREEN_NONE = 0,
156 ATMEL_ADC_TOUCHSCREEN_4WIRE = 4,
157 ATMEL_ADC_TOUCHSCREEN_5WIRE = 5,
158 };
159
160 /**
161 * struct at91_adc_trigger - description of triggers
162 * @name: name of the trigger advertised to the user
163 * @value: value to set in the ADC's trigger setup register
164 * to enable the trigger
165 * @is_external: Does the trigger rely on an external pin?
166 */
167 struct at91_adc_trigger {
168 const char *name;
169 u8 value;
170 bool is_external;
171 };
172
173 /**
174 * struct at91_adc_reg_desc - Various information relative to registers
175 * @channel_base: Base offset for the channel data registers
176 * @drdy_mask: Mask of the DRDY field in the relevant registers
177 * (Interruptions registers mostly)
178 * @status_register: Offset of the Interrupt Status Register
179 * @trigger_register: Offset of the Trigger setup register
180 * @mr_prescal_mask: Mask of the PRESCAL field in the adc MR register
181 * @mr_startup_mask: Mask of the STARTUP field in the adc MR register
182 */
183 struct at91_adc_reg_desc {
184 u8 channel_base;
185 u32 drdy_mask;
186 u8 status_register;
187 u8 trigger_register;
188 u32 mr_prescal_mask;
189 u32 mr_startup_mask;
190 };
191
192 struct at91_adc_caps {
193 bool has_ts; /* Support touch screen */
194 bool has_tsmr; /* only at91sam9x5, sama5d3 have TSMR reg */
195 /*
196 * Numbers of sampling data will be averaged. Can be 0~3.
197 * Hardware can average (2 ^ ts_filter_average) sample data.
198 */
199 u8 ts_filter_average;
200 /* Pen Detection input pull-up resistor, can be 0~3 */
201 u8 ts_pen_detect_sensitivity;
202
203 /* startup time calculate function */
204 u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz);
205
206 u8 num_channels;
207
208 u8 low_res_bits;
209 u8 high_res_bits;
210 u32 trigger_number;
211 const struct at91_adc_trigger *triggers;
212 struct at91_adc_reg_desc registers;
213 };
214
215 struct at91_adc_state {
216 struct clk *adc_clk;
217 u16 *buffer;
218 unsigned long channels_mask;
219 struct clk *clk;
220 bool done;
221 int irq;
222 u16 last_value;
223 int chnb;
224 struct mutex lock;
225 u8 num_channels;
226 void __iomem *reg_base;
227 const struct at91_adc_reg_desc *registers;
228 u32 startup_time;
229 u8 sample_hold_time;
230 bool sleep_mode;
231 struct iio_trigger **trig;
232 bool use_external;
233 u32 vref_mv;
234 u32 res; /* resolution used for conversions */
235 wait_queue_head_t wq_data_avail;
236 const struct at91_adc_caps *caps;
237
238 /*
239 * Following ADC channels are shared by touchscreen:
240 *
241 * CH0 -- Touch screen XP/UL
242 * CH1 -- Touch screen XM/UR
243 * CH2 -- Touch screen YP/LL
244 * CH3 -- Touch screen YM/Sense
245 * CH4 -- Touch screen LR(5-wire only)
246 *
247 * The bitfields below represents the reserved channel in the
248 * touchscreen mode.
249 */
250 #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0)
251 #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0)
252 enum atmel_adc_ts_type touchscreen_type;
253 struct input_dev *ts_input;
254
255 u16 ts_sample_period_val;
256 u32 ts_pressure_threshold;
257 u16 ts_pendbc;
258
259 bool ts_bufferedmeasure;
260 u32 ts_prev_absx;
261 u32 ts_prev_absy;
262 };
263
at91_adc_trigger_handler(int irq,void * p)264 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
265 {
266 struct iio_poll_func *pf = p;
267 struct iio_dev *idev = pf->indio_dev;
268 struct at91_adc_state *st = iio_priv(idev);
269 struct iio_chan_spec const *chan;
270 int i, j = 0;
271
272 iio_for_each_active_channel(idev, i) {
273 chan = idev->channels + i;
274 st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, chan->channel));
275 j++;
276 }
277
278 iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp);
279
280 iio_trigger_notify_done(idev->trig);
281
282 /* Needed to ACK the DRDY interruption */
283 at91_adc_readl(st, AT91_ADC_LCDR);
284
285 enable_irq(st->irq);
286
287 return IRQ_HANDLED;
288 }
289
290 /* Handler for classic adc channel eoc trigger */
handle_adc_eoc_trigger(int irq,struct iio_dev * idev)291 static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev)
292 {
293 struct at91_adc_state *st = iio_priv(idev);
294
295 if (iio_buffer_enabled(idev)) {
296 disable_irq_nosync(irq);
297 iio_trigger_poll(idev->trig);
298 } else {
299 st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb));
300 /* Needed to ACK the DRDY interruption */
301 at91_adc_readl(st, AT91_ADC_LCDR);
302 st->done = true;
303 wake_up_interruptible(&st->wq_data_avail);
304 }
305 }
306
at91_ts_sample(struct iio_dev * idev)307 static void at91_ts_sample(struct iio_dev *idev)
308 {
309 struct at91_adc_state *st = iio_priv(idev);
310 unsigned int xscale, yscale, reg, z1, z2;
311 unsigned int x, y, pres, xpos, ypos;
312 unsigned int rxp = 1;
313 unsigned int factor = 1000;
314
315 unsigned int xyz_mask_bits = st->res;
316 unsigned int xyz_mask = (1 << xyz_mask_bits) - 1;
317
318 /* calculate position */
319 /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */
320 reg = at91_adc_readl(st, AT91_ADC_TSXPOSR);
321 xpos = reg & xyz_mask;
322 x = (xpos << MAX_POS_BITS) - xpos;
323 xscale = (reg >> 16) & xyz_mask;
324 if (xscale == 0) {
325 dev_err(&idev->dev, "Error: xscale == 0!\n");
326 return;
327 }
328 x /= xscale;
329
330 /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */
331 reg = at91_adc_readl(st, AT91_ADC_TSYPOSR);
332 ypos = reg & xyz_mask;
333 y = (ypos << MAX_POS_BITS) - ypos;
334 yscale = (reg >> 16) & xyz_mask;
335 if (yscale == 0) {
336 dev_err(&idev->dev, "Error: yscale == 0!\n");
337 return;
338 }
339 y /= yscale;
340
341 /* calculate the pressure */
342 reg = at91_adc_readl(st, AT91_ADC_TSPRESSR);
343 z1 = reg & xyz_mask;
344 z2 = (reg >> 16) & xyz_mask;
345
346 if (z1 != 0)
347 pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor)
348 / factor;
349 else
350 pres = st->ts_pressure_threshold; /* no pen contacted */
351
352 dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n",
353 xpos, xscale, ypos, yscale, z1, z2, pres);
354
355 if (pres < st->ts_pressure_threshold) {
356 dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n",
357 x, y, pres / factor);
358 input_report_abs(st->ts_input, ABS_X, x);
359 input_report_abs(st->ts_input, ABS_Y, y);
360 input_report_abs(st->ts_input, ABS_PRESSURE, pres);
361 input_report_key(st->ts_input, BTN_TOUCH, 1);
362 input_sync(st->ts_input);
363 } else {
364 dev_dbg(&idev->dev, "pressure too low: not reporting\n");
365 }
366 }
367
at91_adc_rl_interrupt(int irq,void * private)368 static irqreturn_t at91_adc_rl_interrupt(int irq, void *private)
369 {
370 struct iio_dev *idev = private;
371 struct at91_adc_state *st = iio_priv(idev);
372 u32 status = at91_adc_readl(st, st->registers->status_register);
373 unsigned int reg;
374
375 status &= at91_adc_readl(st, AT91_ADC_IMR);
376 if (status & GENMASK(st->num_channels - 1, 0))
377 handle_adc_eoc_trigger(irq, idev);
378
379 if (status & AT91RL_ADC_IER_PEN) {
380 /* Disabling pen debounce is required to get a NOPEN irq */
381 reg = at91_adc_readl(st, AT91_ADC_MR);
382 reg &= ~AT91_ADC_PENDBC;
383 at91_adc_writel(st, AT91_ADC_MR, reg);
384
385 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
386 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN
387 | AT91_ADC_EOC(3));
388 /* Set up period trigger for sampling */
389 at91_adc_writel(st, st->registers->trigger_register,
390 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
391 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
392 } else if (status & AT91RL_ADC_IER_NOPEN) {
393 reg = at91_adc_readl(st, AT91_ADC_MR);
394 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
395 at91_adc_writel(st, AT91_ADC_MR, reg);
396 at91_adc_writel(st, st->registers->trigger_register,
397 AT91_ADC_TRGR_NONE);
398
399 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN
400 | AT91_ADC_EOC(3));
401 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
402 st->ts_bufferedmeasure = false;
403 input_report_key(st->ts_input, BTN_TOUCH, 0);
404 input_sync(st->ts_input);
405 } else if (status & AT91_ADC_EOC(3) && st->ts_input) {
406 /* Conversion finished and we've a touchscreen */
407 if (st->ts_bufferedmeasure) {
408 /*
409 * Last measurement is always discarded, since it can
410 * be erroneous.
411 * Always report previous measurement
412 */
413 input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx);
414 input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy);
415 input_report_key(st->ts_input, BTN_TOUCH, 1);
416 input_sync(st->ts_input);
417 } else
418 st->ts_bufferedmeasure = true;
419
420 /* Now make new measurement */
421 st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3))
422 << MAX_RLPOS_BITS;
423 st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2));
424
425 st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1))
426 << MAX_RLPOS_BITS;
427 st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0));
428 }
429
430 return IRQ_HANDLED;
431 }
432
at91_adc_9x5_interrupt(int irq,void * private)433 static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private)
434 {
435 struct iio_dev *idev = private;
436 struct at91_adc_state *st = iio_priv(idev);
437 u32 status = at91_adc_readl(st, st->registers->status_register);
438 const uint32_t ts_data_irq_mask =
439 AT91_ADC_IER_XRDY |
440 AT91_ADC_IER_YRDY |
441 AT91_ADC_IER_PRDY;
442
443 if (status & GENMASK(st->num_channels - 1, 0))
444 handle_adc_eoc_trigger(irq, idev);
445
446 if (status & AT91_ADC_IER_PEN) {
447 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
448 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN |
449 ts_data_irq_mask);
450 /* Set up period trigger for sampling */
451 at91_adc_writel(st, st->registers->trigger_register,
452 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
453 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
454 } else if (status & AT91_ADC_IER_NOPEN) {
455 at91_adc_writel(st, st->registers->trigger_register, 0);
456 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN |
457 ts_data_irq_mask);
458 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
459
460 input_report_key(st->ts_input, BTN_TOUCH, 0);
461 input_sync(st->ts_input);
462 } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) {
463 /* Now all touchscreen data is ready */
464
465 if (status & AT91_ADC_ISR_PENS) {
466 /* validate data by pen contact */
467 at91_ts_sample(idev);
468 } else {
469 /* triggered by event that is no pen contact, just read
470 * them to clean the interrupt and discard all.
471 */
472 at91_adc_readl(st, AT91_ADC_TSXPOSR);
473 at91_adc_readl(st, AT91_ADC_TSYPOSR);
474 at91_adc_readl(st, AT91_ADC_TSPRESSR);
475 }
476 }
477
478 return IRQ_HANDLED;
479 }
480
at91_adc_channel_init(struct iio_dev * idev)481 static int at91_adc_channel_init(struct iio_dev *idev)
482 {
483 struct at91_adc_state *st = iio_priv(idev);
484 struct iio_chan_spec *chan_array, *timestamp;
485 int bit, idx = 0;
486 unsigned long rsvd_mask = 0;
487
488 /* If touchscreen is enable, then reserve the adc channels */
489 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
490 rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE;
491 else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE)
492 rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE;
493
494 /* set up the channel mask to reserve touchscreen channels */
495 st->channels_mask &= ~rsvd_mask;
496
497 idev->num_channels = bitmap_weight(&st->channels_mask,
498 st->num_channels) + 1;
499
500 chan_array = devm_kzalloc(&idev->dev,
501 ((idev->num_channels + 1) *
502 sizeof(struct iio_chan_spec)),
503 GFP_KERNEL);
504
505 if (!chan_array)
506 return -ENOMEM;
507
508 for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
509 struct iio_chan_spec *chan = chan_array + idx;
510
511 chan->type = IIO_VOLTAGE;
512 chan->indexed = 1;
513 chan->channel = bit;
514 chan->scan_index = idx;
515 chan->scan_type.sign = 'u';
516 chan->scan_type.realbits = st->res;
517 chan->scan_type.storagebits = 16;
518 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
519 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
520 idx++;
521 }
522 timestamp = chan_array + idx;
523
524 timestamp->type = IIO_TIMESTAMP;
525 timestamp->channel = -1;
526 timestamp->scan_index = idx;
527 timestamp->scan_type.sign = 's';
528 timestamp->scan_type.realbits = 64;
529 timestamp->scan_type.storagebits = 64;
530
531 idev->channels = chan_array;
532 return idev->num_channels;
533 }
534
at91_adc_get_trigger_value_by_name(struct iio_dev * idev,const struct at91_adc_trigger * triggers,const char * trigger_name)535 static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
536 const struct at91_adc_trigger *triggers,
537 const char *trigger_name)
538 {
539 struct at91_adc_state *st = iio_priv(idev);
540 int i;
541
542 for (i = 0; i < st->caps->trigger_number; i++) {
543 char *name __free(kfree) = kasprintf(GFP_KERNEL, "%s-dev%d-%s",
544 idev->name,
545 iio_device_id(idev),
546 triggers[i].name);
547 if (!name)
548 return -ENOMEM;
549
550 if (strcmp(trigger_name, name) == 0) {
551 if (triggers[i].value == 0)
552 return -EINVAL;
553 return triggers[i].value;
554 }
555 }
556
557 return -EINVAL;
558 }
559
at91_adc_configure_trigger(struct iio_trigger * trig,bool state)560 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
561 {
562 struct iio_dev *idev = iio_trigger_get_drvdata(trig);
563 struct at91_adc_state *st = iio_priv(idev);
564 const struct at91_adc_reg_desc *reg = st->registers;
565 u32 status = at91_adc_readl(st, reg->trigger_register);
566 int value;
567 u8 bit;
568
569 value = at91_adc_get_trigger_value_by_name(idev,
570 st->caps->triggers,
571 idev->trig->name);
572 if (value < 0)
573 return value;
574
575 if (state) {
576 st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
577 if (st->buffer == NULL)
578 return -ENOMEM;
579
580 at91_adc_writel(st, reg->trigger_register,
581 status | value);
582
583 for_each_set_bit(bit, idev->active_scan_mask,
584 st->num_channels) {
585 struct iio_chan_spec const *chan = idev->channels + bit;
586 at91_adc_writel(st, AT91_ADC_CHER,
587 AT91_ADC_CH(chan->channel));
588 }
589
590 at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
591
592 } else {
593 at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
594
595 at91_adc_writel(st, reg->trigger_register,
596 status & ~value);
597
598 for_each_set_bit(bit, idev->active_scan_mask,
599 st->num_channels) {
600 struct iio_chan_spec const *chan = idev->channels + bit;
601 at91_adc_writel(st, AT91_ADC_CHDR,
602 AT91_ADC_CH(chan->channel));
603 }
604 kfree(st->buffer);
605 }
606
607 return 0;
608 }
609
610 static const struct iio_trigger_ops at91_adc_trigger_ops = {
611 .set_trigger_state = &at91_adc_configure_trigger,
612 };
613
at91_adc_allocate_trigger(struct iio_dev * idev,const struct at91_adc_trigger * trigger)614 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
615 const struct at91_adc_trigger *trigger)
616 {
617 struct iio_trigger *trig;
618 int ret;
619
620 trig = iio_trigger_alloc(idev->dev.parent, "%s-dev%d-%s", idev->name,
621 iio_device_id(idev), trigger->name);
622 if (trig == NULL)
623 return NULL;
624
625 iio_trigger_set_drvdata(trig, idev);
626 trig->ops = &at91_adc_trigger_ops;
627
628 ret = iio_trigger_register(trig);
629 if (ret) {
630 iio_trigger_free(trig);
631 return NULL;
632 }
633
634 return trig;
635 }
636
at91_adc_trigger_init(struct iio_dev * idev)637 static int at91_adc_trigger_init(struct iio_dev *idev)
638 {
639 struct at91_adc_state *st = iio_priv(idev);
640 int i, ret;
641
642 st->trig = devm_kcalloc(&idev->dev,
643 st->caps->trigger_number, sizeof(*st->trig),
644 GFP_KERNEL);
645
646 if (st->trig == NULL) {
647 ret = -ENOMEM;
648 goto error_ret;
649 }
650
651 for (i = 0; i < st->caps->trigger_number; i++) {
652 if (st->caps->triggers[i].is_external && !(st->use_external))
653 continue;
654
655 st->trig[i] = at91_adc_allocate_trigger(idev,
656 st->caps->triggers + i);
657 if (st->trig[i] == NULL) {
658 dev_err(&idev->dev,
659 "Could not allocate trigger %d\n", i);
660 ret = -ENOMEM;
661 goto error_trigger;
662 }
663 }
664
665 return 0;
666
667 error_trigger:
668 for (i--; i >= 0; i--) {
669 iio_trigger_unregister(st->trig[i]);
670 iio_trigger_free(st->trig[i]);
671 }
672 error_ret:
673 return ret;
674 }
675
at91_adc_trigger_remove(struct iio_dev * idev)676 static void at91_adc_trigger_remove(struct iio_dev *idev)
677 {
678 struct at91_adc_state *st = iio_priv(idev);
679 int i;
680
681 for (i = 0; i < st->caps->trigger_number; i++) {
682 iio_trigger_unregister(st->trig[i]);
683 iio_trigger_free(st->trig[i]);
684 }
685 }
686
at91_adc_buffer_init(struct iio_dev * idev)687 static int at91_adc_buffer_init(struct iio_dev *idev)
688 {
689 return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
690 &at91_adc_trigger_handler, NULL);
691 }
692
at91_adc_buffer_remove(struct iio_dev * idev)693 static void at91_adc_buffer_remove(struct iio_dev *idev)
694 {
695 iio_triggered_buffer_cleanup(idev);
696 }
697
at91_adc_read_raw(struct iio_dev * idev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)698 static int at91_adc_read_raw(struct iio_dev *idev,
699 struct iio_chan_spec const *chan,
700 int *val, int *val2, long mask)
701 {
702 struct at91_adc_state *st = iio_priv(idev);
703 int ret;
704
705 switch (mask) {
706 case IIO_CHAN_INFO_RAW:
707 mutex_lock(&st->lock);
708
709 st->chnb = chan->channel;
710 at91_adc_writel(st, AT91_ADC_CHER,
711 AT91_ADC_CH(chan->channel));
712 at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel));
713 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
714
715 ret = wait_event_interruptible_timeout(st->wq_data_avail,
716 st->done,
717 msecs_to_jiffies(1000));
718
719 /* Disable interrupts, regardless if adc conversion was
720 * successful or not
721 */
722 at91_adc_writel(st, AT91_ADC_CHDR,
723 AT91_ADC_CH(chan->channel));
724 at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel));
725
726 if (ret > 0) {
727 /* a valid conversion took place */
728 *val = st->last_value;
729 st->last_value = 0;
730 st->done = false;
731 ret = IIO_VAL_INT;
732 } else if (ret == 0) {
733 /* conversion timeout */
734 dev_err(&idev->dev, "ADC Channel %d timeout.\n",
735 chan->channel);
736 ret = -ETIMEDOUT;
737 }
738
739 mutex_unlock(&st->lock);
740 return ret;
741
742 case IIO_CHAN_INFO_SCALE:
743 *val = st->vref_mv;
744 *val2 = chan->scan_type.realbits;
745 return IIO_VAL_FRACTIONAL_LOG2;
746 default:
747 break;
748 }
749 return -EINVAL;
750 }
751
752
calc_startup_ticks_9260(u32 startup_time,u32 adc_clk_khz)753 static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz)
754 {
755 /*
756 * Number of ticks needed to cover the startup time of the ADC
757 * as defined in the electrical characteristics of the board,
758 * divided by 8. The formula thus is :
759 * Startup Time = (ticks + 1) * 8 / ADC Clock
760 */
761 return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8;
762 }
763
calc_startup_ticks_9x5(u32 startup_time,u32 adc_clk_khz)764 static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz)
765 {
766 /*
767 * For sama5d3x and at91sam9x5, the formula changes to:
768 * Startup Time = <lookup_table_value> / ADC Clock
769 */
770 static const int startup_lookup[] = {
771 0, 8, 16, 24,
772 64, 80, 96, 112,
773 512, 576, 640, 704,
774 768, 832, 896, 960
775 };
776 int i, size = ARRAY_SIZE(startup_lookup);
777 unsigned int ticks;
778
779 ticks = startup_time * adc_clk_khz / 1000;
780 for (i = 0; i < size; i++)
781 if (ticks < startup_lookup[i])
782 break;
783
784 ticks = i;
785 if (ticks == size)
786 /* Reach the end of lookup table */
787 ticks = size - 1;
788
789 return ticks;
790 }
791
at91_adc_probe_dt_ts(struct device_node * node,struct at91_adc_state * st,struct device * dev)792 static int at91_adc_probe_dt_ts(struct device_node *node,
793 struct at91_adc_state *st, struct device *dev)
794 {
795 int ret;
796 u32 prop;
797
798 ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop);
799 if (ret) {
800 dev_info(dev, "ADC Touch screen is disabled.\n");
801 return 0;
802 }
803
804 switch (prop) {
805 case 4:
806 case 5:
807 st->touchscreen_type = prop;
808 break;
809 default:
810 dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop);
811 return -EINVAL;
812 }
813
814 if (!st->caps->has_tsmr)
815 return 0;
816 prop = 0;
817 of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop);
818 st->ts_pressure_threshold = prop;
819 if (st->ts_pressure_threshold) {
820 return 0;
821 } else {
822 dev_err(dev, "Invalid pressure threshold for the touchscreen\n");
823 return -EINVAL;
824 }
825 }
826
827 static const struct iio_info at91_adc_info = {
828 .read_raw = &at91_adc_read_raw,
829 };
830
831 /* Touchscreen related functions */
atmel_ts_open(struct input_dev * dev)832 static int atmel_ts_open(struct input_dev *dev)
833 {
834 struct at91_adc_state *st = input_get_drvdata(dev);
835
836 if (st->caps->has_tsmr)
837 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
838 else
839 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
840 return 0;
841 }
842
atmel_ts_close(struct input_dev * dev)843 static void atmel_ts_close(struct input_dev *dev)
844 {
845 struct at91_adc_state *st = input_get_drvdata(dev);
846
847 if (st->caps->has_tsmr)
848 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
849 else
850 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
851 }
852
at91_ts_hw_init(struct iio_dev * idev,u32 adc_clk_khz)853 static int at91_ts_hw_init(struct iio_dev *idev, u32 adc_clk_khz)
854 {
855 struct at91_adc_state *st = iio_priv(idev);
856 u32 reg = 0;
857 u32 tssctim = 0;
858 int i = 0;
859
860 /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid
861 * pen detect noise.
862 * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock
863 */
864 st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz /
865 1000, 1);
866
867 while (st->ts_pendbc >> ++i)
868 ; /* Empty! Find the shift offset */
869 if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1))))
870 st->ts_pendbc = i;
871 else
872 st->ts_pendbc = i - 1;
873
874 if (!st->caps->has_tsmr) {
875 reg = at91_adc_readl(st, AT91_ADC_MR);
876 reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET;
877
878 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
879 at91_adc_writel(st, AT91_ADC_MR, reg);
880
881 reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM;
882 at91_adc_writel(st, AT91_ADC_TSR, reg);
883
884 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL *
885 adc_clk_khz / 1000) - 1, 1);
886
887 return 0;
888 }
889
890 /* Touchscreen Switches Closure time needed for allowing the value to
891 * stabilize.
892 * Switch Closure Time = (TSSCTIM * 4) ADCClock periods
893 */
894 tssctim = DIV_ROUND_UP(TOUCH_SCTIM_US * adc_clk_khz / 1000, 4);
895 dev_dbg(&idev->dev, "adc_clk at: %d KHz, tssctim at: %d\n",
896 adc_clk_khz, tssctim);
897
898 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
899 reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS;
900 else
901 reg = AT91_ADC_TSMR_TSMODE_5WIRE;
902
903 reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM;
904 reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average)
905 & AT91_ADC_TSMR_TSAV;
906 reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC;
907 reg |= AT91_ADC_TSMR_NOTSDMA;
908 reg |= AT91_ADC_TSMR_PENDET_ENA;
909 reg |= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */
910
911 at91_adc_writel(st, AT91_ADC_TSMR, reg);
912
913 /* Change adc internal resistor value for better pen detection,
914 * default value is 100 kOhm.
915 * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm
916 * option only available on ES2 and higher
917 */
918 at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity
919 & AT91_ADC_ACR_PENDETSENS);
920
921 /* Sample Period Time = (TRGPER + 1) / ADCClock */
922 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US *
923 adc_clk_khz / 1000) - 1, 1);
924
925 return 0;
926 }
927
at91_ts_register(struct iio_dev * idev,struct platform_device * pdev)928 static int at91_ts_register(struct iio_dev *idev,
929 struct platform_device *pdev)
930 {
931 struct at91_adc_state *st = iio_priv(idev);
932 struct input_dev *input;
933 int ret;
934
935 input = input_allocate_device();
936 if (!input) {
937 dev_err(&idev->dev, "Failed to allocate TS device!\n");
938 return -ENOMEM;
939 }
940
941 input->name = DRIVER_NAME;
942 input->id.bustype = BUS_HOST;
943 input->dev.parent = &pdev->dev;
944 input->open = atmel_ts_open;
945 input->close = atmel_ts_close;
946
947 __set_bit(EV_ABS, input->evbit);
948 __set_bit(EV_KEY, input->evbit);
949 __set_bit(BTN_TOUCH, input->keybit);
950 if (st->caps->has_tsmr) {
951 input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1,
952 0, 0);
953 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1,
954 0, 0);
955 input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0);
956 } else {
957 if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) {
958 dev_err(&pdev->dev,
959 "This touchscreen controller only support 4 wires\n");
960 ret = -EINVAL;
961 goto err;
962 }
963
964 input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1,
965 0, 0);
966 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1,
967 0, 0);
968 }
969
970 st->ts_input = input;
971 input_set_drvdata(input, st);
972
973 ret = input_register_device(input);
974 if (ret)
975 goto err;
976
977 return ret;
978
979 err:
980 input_free_device(input);
981 return ret;
982 }
983
at91_ts_unregister(struct at91_adc_state * st)984 static void at91_ts_unregister(struct at91_adc_state *st)
985 {
986 input_unregister_device(st->ts_input);
987 }
988
at91_adc_probe(struct platform_device * pdev)989 static int at91_adc_probe(struct platform_device *pdev)
990 {
991 unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
992 struct device_node *node = pdev->dev.of_node;
993 int ret;
994 struct iio_dev *idev;
995 struct at91_adc_state *st;
996 u32 reg, prop;
997 char *s;
998
999 idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state));
1000 if (!idev)
1001 return -ENOMEM;
1002
1003 st = iio_priv(idev);
1004
1005 st->caps = of_device_get_match_data(&pdev->dev);
1006
1007 st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
1008
1009 if (of_property_read_u32(node, "atmel,adc-channels-used", &prop))
1010 return dev_err_probe(&idev->dev, -EINVAL,
1011 "Missing adc-channels-used property in the DT.\n");
1012 st->channels_mask = prop;
1013
1014 st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode");
1015
1016 if (of_property_read_u32(node, "atmel,adc-startup-time", &prop))
1017 return dev_err_probe(&idev->dev, -EINVAL,
1018 "Missing adc-startup-time property in the DT.\n");
1019 st->startup_time = prop;
1020
1021 prop = 0;
1022 of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop);
1023 st->sample_hold_time = prop;
1024
1025 if (of_property_read_u32(node, "atmel,adc-vref", &prop))
1026 return dev_err_probe(&idev->dev, -EINVAL,
1027 "Missing adc-vref property in the DT.\n");
1028 st->vref_mv = prop;
1029
1030 st->res = st->caps->high_res_bits;
1031 if (st->caps->low_res_bits &&
1032 !of_property_read_string(node, "atmel,adc-use-res", (const char **)&s)
1033 && !strcmp(s, "lowres"))
1034 st->res = st->caps->low_res_bits;
1035
1036 dev_info(&idev->dev, "Resolution used: %u bits\n", st->res);
1037
1038 st->registers = &st->caps->registers;
1039 st->num_channels = st->caps->num_channels;
1040
1041 /* Check if touchscreen is supported. */
1042 if (st->caps->has_ts) {
1043 ret = at91_adc_probe_dt_ts(node, st, &idev->dev);
1044 if (ret)
1045 return ret;
1046 }
1047
1048 platform_set_drvdata(pdev, idev);
1049
1050 idev->name = dev_name(&pdev->dev);
1051 idev->modes = INDIO_DIRECT_MODE;
1052 idev->info = &at91_adc_info;
1053
1054 st->irq = platform_get_irq(pdev, 0);
1055 if (st->irq < 0)
1056 return -ENODEV;
1057
1058 st->reg_base = devm_platform_ioremap_resource(pdev, 0);
1059 if (IS_ERR(st->reg_base))
1060 return PTR_ERR(st->reg_base);
1061
1062 /*
1063 * Disable all IRQs before setting up the handler
1064 */
1065 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
1066 at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
1067
1068 if (st->caps->has_tsmr)
1069 ret = devm_request_irq(&pdev->dev, st->irq,
1070 at91_adc_9x5_interrupt, 0,
1071 pdev->dev.driver->name, idev);
1072 else
1073 ret = devm_request_irq(&pdev->dev, st->irq,
1074 at91_adc_rl_interrupt, 0,
1075 pdev->dev.driver->name, idev);
1076 if (ret)
1077 return dev_err_probe(&pdev->dev, ret,
1078 "Failed to allocate IRQ.\n");
1079
1080 st->clk = devm_clk_get_enabled(&pdev->dev, "adc_clk");
1081 if (IS_ERR(st->clk))
1082 return dev_err_probe(&pdev->dev, PTR_ERR(st->clk),
1083 "Could not prepare or enable the clock.\n");
1084
1085 st->adc_clk = devm_clk_get_enabled(&pdev->dev, "adc_op_clk");
1086 if (IS_ERR(st->adc_clk))
1087 return dev_err_probe(&pdev->dev, PTR_ERR(st->adc_clk),
1088 "Could not prepare or enable the ADC clock.\n");
1089
1090 /*
1091 * Prescaler rate computation using the formula from the Atmel's
1092 * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being
1093 * specified by the electrical characteristics of the board.
1094 */
1095 mstrclk = clk_get_rate(st->clk);
1096 adc_clk = clk_get_rate(st->adc_clk);
1097 adc_clk_khz = adc_clk / 1000;
1098
1099 dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n",
1100 mstrclk, adc_clk);
1101
1102 prsc = (mstrclk / (2 * adc_clk)) - 1;
1103
1104 if (!st->startup_time)
1105 return dev_err_probe(&pdev->dev, -EINVAL,
1106 "No startup time available.\n");
1107 ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz);
1108
1109 /*
1110 * a minimal Sample and Hold Time is necessary for the ADC to guarantee
1111 * the best converted final value between two channels selection
1112 * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
1113 */
1114 if (st->sample_hold_time > 0)
1115 shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000)
1116 - 1, 1);
1117 else
1118 shtim = 0;
1119
1120 reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
1121 reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;
1122 if (st->res == st->caps->low_res_bits)
1123 reg |= AT91_ADC_LOWRES;
1124 if (st->sleep_mode)
1125 reg |= AT91_ADC_SLEEP;
1126 reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM;
1127 at91_adc_writel(st, AT91_ADC_MR, reg);
1128
1129 /* Setup the ADC channels available on the board */
1130 ret = at91_adc_channel_init(idev);
1131 if (ret < 0)
1132 return dev_err_probe(&pdev->dev, ret,
1133 "Couldn't initialize the channels.\n");
1134
1135 init_waitqueue_head(&st->wq_data_avail);
1136 mutex_init(&st->lock);
1137
1138 /*
1139 * Since touch screen will set trigger register as period trigger. So
1140 * when touch screen is enabled, then we have to disable hardware
1141 * trigger for classic adc.
1142 */
1143 if (!st->touchscreen_type) {
1144 ret = at91_adc_buffer_init(idev);
1145 if (ret < 0)
1146 return dev_err_probe(&pdev->dev, ret,
1147 "Couldn't initialize the buffer.\n");
1148
1149 ret = at91_adc_trigger_init(idev);
1150 if (ret < 0) {
1151 dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
1152 at91_adc_buffer_remove(idev);
1153 return ret;
1154 }
1155 } else {
1156 ret = at91_ts_register(idev, pdev);
1157 if (ret)
1158 return ret;
1159
1160 at91_ts_hw_init(idev, adc_clk_khz);
1161 }
1162
1163 ret = iio_device_register(idev);
1164 if (ret < 0) {
1165 dev_err(&pdev->dev, "Couldn't register the device.\n");
1166 goto error_iio_device_register;
1167 }
1168
1169 return 0;
1170
1171 error_iio_device_register:
1172 if (!st->touchscreen_type) {
1173 at91_adc_trigger_remove(idev);
1174 at91_adc_buffer_remove(idev);
1175 } else {
1176 at91_ts_unregister(st);
1177 }
1178 return ret;
1179 }
1180
at91_adc_remove(struct platform_device * pdev)1181 static void at91_adc_remove(struct platform_device *pdev)
1182 {
1183 struct iio_dev *idev = platform_get_drvdata(pdev);
1184 struct at91_adc_state *st = iio_priv(idev);
1185
1186 iio_device_unregister(idev);
1187 if (!st->touchscreen_type) {
1188 at91_adc_trigger_remove(idev);
1189 at91_adc_buffer_remove(idev);
1190 } else {
1191 at91_ts_unregister(st);
1192 }
1193 }
1194
at91_adc_suspend(struct device * dev)1195 static int at91_adc_suspend(struct device *dev)
1196 {
1197 struct iio_dev *idev = dev_get_drvdata(dev);
1198 struct at91_adc_state *st = iio_priv(idev);
1199
1200 pinctrl_pm_select_sleep_state(dev);
1201 clk_disable_unprepare(st->clk);
1202
1203 return 0;
1204 }
1205
at91_adc_resume(struct device * dev)1206 static int at91_adc_resume(struct device *dev)
1207 {
1208 struct iio_dev *idev = dev_get_drvdata(dev);
1209 struct at91_adc_state *st = iio_priv(idev);
1210
1211 clk_prepare_enable(st->clk);
1212 pinctrl_pm_select_default_state(dev);
1213
1214 return 0;
1215 }
1216
1217 static DEFINE_SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend,
1218 at91_adc_resume);
1219
1220 static const struct at91_adc_trigger at91sam9260_triggers[] = {
1221 { .name = "timer-counter-0", .value = 0x1 },
1222 { .name = "timer-counter-1", .value = 0x3 },
1223 { .name = "timer-counter-2", .value = 0x5 },
1224 { .name = "external", .value = 0xd, .is_external = true },
1225 };
1226
1227 static const struct at91_adc_caps at91sam9260_caps = {
1228 .calc_startup_ticks = calc_startup_ticks_9260,
1229 .num_channels = 4,
1230 .low_res_bits = 8,
1231 .high_res_bits = 10,
1232 .registers = {
1233 .channel_base = AT91_ADC_CHR(0),
1234 .drdy_mask = AT91_ADC_DRDY,
1235 .status_register = AT91_ADC_SR,
1236 .trigger_register = AT91_ADC_TRGR_9260,
1237 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1238 .mr_startup_mask = AT91_ADC_STARTUP_9260,
1239 },
1240 .triggers = at91sam9260_triggers,
1241 .trigger_number = ARRAY_SIZE(at91sam9260_triggers),
1242 };
1243
1244 static const struct at91_adc_trigger at91sam9x5_triggers[] = {
1245 { .name = "external-rising", .value = 0x1, .is_external = true },
1246 { .name = "external-falling", .value = 0x2, .is_external = true },
1247 { .name = "external-any", .value = 0x3, .is_external = true },
1248 { .name = "continuous", .value = 0x6 },
1249 };
1250
1251 static const struct at91_adc_caps at91sam9rl_caps = {
1252 .has_ts = true,
1253 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
1254 .num_channels = 6,
1255 .low_res_bits = 8,
1256 .high_res_bits = 10,
1257 .registers = {
1258 .channel_base = AT91_ADC_CHR(0),
1259 .drdy_mask = AT91_ADC_DRDY,
1260 .status_register = AT91_ADC_SR,
1261 .trigger_register = AT91_ADC_TRGR_9G45,
1262 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1263 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1264 },
1265 .triggers = at91sam9x5_triggers,
1266 .trigger_number = ARRAY_SIZE(at91sam9x5_triggers),
1267 };
1268
1269 static const struct at91_adc_caps at91sam9g45_caps = {
1270 .has_ts = true,
1271 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
1272 .num_channels = 8,
1273 .low_res_bits = 8,
1274 .high_res_bits = 10,
1275 .registers = {
1276 .channel_base = AT91_ADC_CHR(0),
1277 .drdy_mask = AT91_ADC_DRDY,
1278 .status_register = AT91_ADC_SR,
1279 .trigger_register = AT91_ADC_TRGR_9G45,
1280 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1281 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1282 },
1283 .triggers = at91sam9x5_triggers,
1284 .trigger_number = ARRAY_SIZE(at91sam9x5_triggers),
1285 };
1286
1287 static const struct at91_adc_caps at91sam9x5_caps = {
1288 .has_ts = true,
1289 .has_tsmr = true,
1290 .ts_filter_average = 3,
1291 .ts_pen_detect_sensitivity = 2,
1292 .calc_startup_ticks = calc_startup_ticks_9x5,
1293 .num_channels = 12,
1294 .low_res_bits = 8,
1295 .high_res_bits = 10,
1296 .registers = {
1297 .channel_base = AT91_ADC_CDR0_9X5,
1298 .drdy_mask = AT91_ADC_SR_DRDY_9X5,
1299 .status_register = AT91_ADC_SR_9X5,
1300 .trigger_register = AT91_ADC_TRGR_9X5,
1301 /* prescal mask is same as 9G45 */
1302 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1303 .mr_startup_mask = AT91_ADC_STARTUP_9X5,
1304 },
1305 .triggers = at91sam9x5_triggers,
1306 .trigger_number = ARRAY_SIZE(at91sam9x5_triggers),
1307 };
1308
1309 static const struct at91_adc_caps sama5d3_caps = {
1310 .has_ts = true,
1311 .has_tsmr = true,
1312 .ts_filter_average = 3,
1313 .ts_pen_detect_sensitivity = 2,
1314 .calc_startup_ticks = calc_startup_ticks_9x5,
1315 .num_channels = 12,
1316 .low_res_bits = 0,
1317 .high_res_bits = 12,
1318 .registers = {
1319 .channel_base = AT91_ADC_CDR0_9X5,
1320 .drdy_mask = AT91_ADC_SR_DRDY_9X5,
1321 .status_register = AT91_ADC_SR_9X5,
1322 .trigger_register = AT91_ADC_TRGR_9X5,
1323 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1324 .mr_startup_mask = AT91_ADC_STARTUP_9X5,
1325 },
1326 .triggers = at91sam9x5_triggers,
1327 .trigger_number = ARRAY_SIZE(at91sam9x5_triggers),
1328 };
1329
1330 static const struct of_device_id at91_adc_dt_ids[] = {
1331 { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps },
1332 { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps },
1333 { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps },
1334 { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps },
1335 { .compatible = "atmel,sama5d3-adc", .data = &sama5d3_caps },
1336 { }
1337 };
1338 MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
1339
1340 static struct platform_driver at91_adc_driver = {
1341 .probe = at91_adc_probe,
1342 .remove = at91_adc_remove,
1343 .driver = {
1344 .name = DRIVER_NAME,
1345 .of_match_table = at91_adc_dt_ids,
1346 .pm = pm_sleep_ptr(&at91_adc_pm_ops),
1347 },
1348 };
1349
1350 module_platform_driver(at91_adc_driver);
1351
1352 MODULE_LICENSE("GPL");
1353 MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
1354 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1355