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Searched refs:ARRAY_MODE (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c79 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) macro
409 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
417 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
425 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
433 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
441 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
444 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
452 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
460 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
467 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); in gfx_v6_0_tiling_mode_table_init()
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H A Dgfx_v8_0.c68 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) macro
2104 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2108 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2112 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2116 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2120 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2124 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2128 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2132 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in gfx_v8_0_tiling_mode_table_init()
2134 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
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H A Dgfx_v7_0.c1022 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1026 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1030 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1034 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1038 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1042 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1045 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1050 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in gfx_v7_0_tiling_mode_table_init()
1052 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1055 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
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H A Dcikd.h189 # define ARRAY_MODE(x) ((x) << 2) macro
H A Dsid.h1177 # define ARRAY_MODE(x) ((x) << 2) macro
H A Ddce_v8_0.c1925 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
1941 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
H A Damdgpu_display.c950 if (AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) == 1) /* LINEAR_ALIGNED */ in check_tiling_flags_gfx6()
H A Ddce_v6_0.c1956 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
1971 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
H A Ddce_v10_0.c1986 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
2006 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
H A Ddce_v11_0.c2036 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
2056 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
/linux/drivers/gpu/drm/radeon/
H A Dcik.c2357 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2361 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2365 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2369 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2373 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2377 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2380 tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2384 tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2388 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in cik_tiling_mode_table_init()
2390 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
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H A Dsi.c2496 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2505 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2514 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2523 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2532 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in si_tiling_mode_table_init()
2541 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2550 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2559 tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2568 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in si_tiling_mode_table_init()
2577 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in si_tiling_mode_table_init()
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H A Dsid.h1180 # define ARRAY_MODE(x) ((x) << 2) macro
H A Dcikd.h1218 # define ARRAY_MODE(x) ((x) << 2) macro
/linux/drivers/gpu/drm/amd/include/
H A Dnavi10_enum.h1673 typedef enum ARRAY_MODE { enum
1690 } ARRAY_MODE; typedef