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Searched refs:ARCMSR_INBOUND_MESG0_FLUSH_CACHE (Results 1 – 4 of 4) sorted by relevance

/titanic_51/usr/src/uts/intel/io/scsi/adapters/arcmsr/
H A Darcmsr.h256 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
494 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 macro
H A Darcmsr.c3706 ARCMSR_INBOUND_MESG0_FLUSH_CACHE); in arcmsr_flush_hba_cache()
3751 ARCMSR_INBOUND_MESG0_FLUSH_CACHE); in arcmsr_flush_hbc_cache()
/freebsd/sys/dev/arcmsr/
H A Darcmsr.h283 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 macro
H A Darcmsr.c469 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); in arcmsr_flush_hba_cache()
504 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); in arcmsr_flush_hbc_cache()
522 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); in arcmsr_flush_hbd_cache()
539 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); in arcmsr_flush_hbe_cache()