1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PERF_EVENT_H
3 #define _ASM_X86_PERF_EVENT_H
4
5 #include <linux/static_call.h>
6
7 /*
8 * Performance event hw details:
9 */
10
11 #define INTEL_PMC_MAX_GENERIC 32
12 #define INTEL_PMC_MAX_FIXED 16
13 #define INTEL_PMC_IDX_FIXED 32
14
15 #define X86_PMC_IDX_MAX 64
16
17 #define MSR_ARCH_PERFMON_PERFCTR0 0xc1
18 #define MSR_ARCH_PERFMON_PERFCTR1 0xc2
19
20 #define MSR_ARCH_PERFMON_EVENTSEL0 0x186
21 #define MSR_ARCH_PERFMON_EVENTSEL1 0x187
22
23 #define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL
24 #define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL
25 #define ARCH_PERFMON_EVENTSEL_USR (1ULL << 16)
26 #define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17)
27 #define ARCH_PERFMON_EVENTSEL_EDGE (1ULL << 18)
28 #define ARCH_PERFMON_EVENTSEL_PIN_CONTROL (1ULL << 19)
29 #define ARCH_PERFMON_EVENTSEL_INT (1ULL << 20)
30 #define ARCH_PERFMON_EVENTSEL_ANY (1ULL << 21)
31 #define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22)
32 #define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23)
33 #define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
34 #define ARCH_PERFMON_EVENTSEL_BR_CNTR (1ULL << 35)
35 #define ARCH_PERFMON_EVENTSEL_EQ (1ULL << 36)
36 #define ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE (1ULL << 37)
37 #define ARCH_PERFMON_EVENTSEL_UMASK2 (0xFFULL << 40)
38
39 #define INTEL_FIXED_BITS_STRIDE 4
40 #define INTEL_FIXED_0_KERNEL (1ULL << 0)
41 #define INTEL_FIXED_0_USER (1ULL << 1)
42 #define INTEL_FIXED_0_ANYTHREAD (1ULL << 2)
43 #define INTEL_FIXED_0_ENABLE_PMI (1ULL << 3)
44 #define INTEL_FIXED_0_RDPMC_USER_DISABLE (1ULL << 33)
45 #define INTEL_FIXED_3_METRICS_CLEAR (1ULL << 2)
46
47 #define HSW_IN_TX (1ULL << 32)
48 #define HSW_IN_TX_CHECKPOINTED (1ULL << 33)
49 #define ICL_EVENTSEL_ADAPTIVE (1ULL << 34)
50 #define ICL_FIXED_0_ADAPTIVE (1ULL << 32)
51
52 #define INTEL_FIXED_BITS_MASK \
53 (INTEL_FIXED_0_KERNEL | INTEL_FIXED_0_USER | \
54 INTEL_FIXED_0_ANYTHREAD | INTEL_FIXED_0_ENABLE_PMI | \
55 ICL_FIXED_0_ADAPTIVE | INTEL_FIXED_0_RDPMC_USER_DISABLE)
56
57 #define intel_fixed_bits_by_idx(_idx, _bits) \
58 ((_bits) << ((_idx) * INTEL_FIXED_BITS_STRIDE))
59
60 #define AMD64_EVENTSEL_INT_CORE_ENABLE (1ULL << 36)
61 #define AMD64_EVENTSEL_GUESTONLY (1ULL << 40)
62 #define AMD64_EVENTSEL_HOSTONLY (1ULL << 41)
63 #define AMD64_EVENTSEL_HOST_GUEST_MASK \
64 (AMD64_EVENTSEL_HOSTONLY | AMD64_EVENTSEL_GUESTONLY)
65
66 #define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT 37
67 #define AMD64_EVENTSEL_INT_CORE_SEL_MASK \
68 (0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
69
70 #define AMD64_EVENTSEL_EVENT \
71 (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
72 #define INTEL_ARCH_EVENT_MASK \
73 (ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)
74
75 #define AMD64_L3_SLICE_SHIFT 48
76 #define AMD64_L3_SLICE_MASK \
77 (0xFULL << AMD64_L3_SLICE_SHIFT)
78 #define AMD64_L3_SLICEID_MASK \
79 (0x7ULL << AMD64_L3_SLICE_SHIFT)
80
81 #define AMD64_L3_THREAD_SHIFT 56
82 #define AMD64_L3_THREAD_MASK \
83 (0xFFULL << AMD64_L3_THREAD_SHIFT)
84 #define AMD64_L3_F19H_THREAD_MASK \
85 (0x3ULL << AMD64_L3_THREAD_SHIFT)
86
87 #define AMD64_L3_EN_ALL_CORES BIT_ULL(47)
88 #define AMD64_L3_EN_ALL_SLICES BIT_ULL(46)
89
90 #define AMD64_L3_COREID_SHIFT 42
91 #define AMD64_L3_COREID_MASK \
92 (0x7ULL << AMD64_L3_COREID_SHIFT)
93
94 #define X86_RAW_EVENT_MASK \
95 (ARCH_PERFMON_EVENTSEL_EVENT | \
96 ARCH_PERFMON_EVENTSEL_UMASK | \
97 ARCH_PERFMON_EVENTSEL_EDGE | \
98 ARCH_PERFMON_EVENTSEL_INV | \
99 ARCH_PERFMON_EVENTSEL_CMASK)
100 #define X86_ALL_EVENT_FLAGS \
101 (ARCH_PERFMON_EVENTSEL_EDGE | \
102 ARCH_PERFMON_EVENTSEL_INV | \
103 ARCH_PERFMON_EVENTSEL_CMASK | \
104 ARCH_PERFMON_EVENTSEL_ANY | \
105 ARCH_PERFMON_EVENTSEL_PIN_CONTROL | \
106 HSW_IN_TX | \
107 HSW_IN_TX_CHECKPOINTED)
108 #define AMD64_RAW_EVENT_MASK \
109 (X86_RAW_EVENT_MASK | \
110 AMD64_EVENTSEL_EVENT)
111 #define AMD64_RAW_EVENT_MASK_NB \
112 (AMD64_EVENTSEL_EVENT | \
113 ARCH_PERFMON_EVENTSEL_UMASK)
114
115 #define AMD64_PERFMON_V2_EVENTSEL_EVENT_NB \
116 (AMD64_EVENTSEL_EVENT | \
117 GENMASK_ULL(37, 36))
118
119 #define AMD64_PERFMON_V2_EVENTSEL_UMASK_NB \
120 (ARCH_PERFMON_EVENTSEL_UMASK | \
121 GENMASK_ULL(27, 24))
122
123 #define AMD64_PERFMON_V2_RAW_EVENT_MASK_NB \
124 (AMD64_PERFMON_V2_EVENTSEL_EVENT_NB | \
125 AMD64_PERFMON_V2_EVENTSEL_UMASK_NB)
126
127 #define AMD64_PERFMON_V2_ENABLE_UMC BIT_ULL(31)
128 #define AMD64_PERFMON_V2_EVENTSEL_EVENT_UMC GENMASK_ULL(7, 0)
129 #define AMD64_PERFMON_V2_EVENTSEL_RDWRMASK_UMC GENMASK_ULL(9, 8)
130 #define AMD64_PERFMON_V2_RAW_EVENT_MASK_UMC \
131 (AMD64_PERFMON_V2_EVENTSEL_EVENT_UMC | \
132 AMD64_PERFMON_V2_EVENTSEL_RDWRMASK_UMC)
133
134 #define AMD64_NUM_COUNTERS 4
135 #define AMD64_NUM_COUNTERS_CORE 6
136 #define AMD64_NUM_COUNTERS_NB 4
137
138 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
139 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
140 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
141 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
142 (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
143
144 #define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
145 #define ARCH_PERFMON_EVENTS_COUNT 7
146
147 #define PEBS_DATACFG_MEMINFO BIT_ULL(0)
148 #define PEBS_DATACFG_GP BIT_ULL(1)
149 #define PEBS_DATACFG_XMMS BIT_ULL(2)
150 #define PEBS_DATACFG_LBRS BIT_ULL(3)
151 #define PEBS_DATACFG_CNTR BIT_ULL(4)
152 #define PEBS_DATACFG_METRICS BIT_ULL(5)
153 #define PEBS_DATACFG_YMMHS BIT_ULL(6)
154 #define PEBS_DATACFG_OPMASKS BIT_ULL(7)
155 #define PEBS_DATACFG_ZMMHS BIT_ULL(8)
156 #define PEBS_DATACFG_H16ZMMS BIT_ULL(9)
157 #define PEBS_DATACFG_EGPRS BIT_ULL(10)
158 #define PEBS_DATACFG_LBR_SHIFT 24
159 #define PEBS_DATACFG_CNTR_SHIFT 32
160 #define PEBS_DATACFG_CNTR_MASK GENMASK_ULL(15, 0)
161 #define PEBS_DATACFG_FIX_SHIFT 48
162 #define PEBS_DATACFG_FIX_MASK GENMASK_ULL(7, 0)
163
164 /* Steal the highest bit of pebs_data_cfg for SW usage */
165 #define PEBS_UPDATE_DS_SW BIT_ULL(63)
166
167 /*
168 * Intel "Architectural Performance Monitoring" CPUID
169 * detection/enumeration details:
170 */
171 union cpuid10_eax {
172 struct {
173 unsigned int version_id:8;
174 unsigned int num_counters:8;
175 unsigned int bit_width:8;
176 unsigned int mask_length:8;
177 } split;
178 unsigned int full;
179 };
180
181 union cpuid10_ebx {
182 struct {
183 unsigned int no_unhalted_core_cycles:1;
184 unsigned int no_instructions_retired:1;
185 unsigned int no_unhalted_reference_cycles:1;
186 unsigned int no_llc_reference:1;
187 unsigned int no_llc_misses:1;
188 unsigned int no_branch_instruction_retired:1;
189 unsigned int no_branch_misses_retired:1;
190 } split;
191 unsigned int full;
192 };
193
194 union cpuid10_edx {
195 struct {
196 unsigned int num_counters_fixed:5;
197 unsigned int bit_width_fixed:8;
198 unsigned int reserved1:2;
199 unsigned int anythread_deprecated:1;
200 unsigned int reserved2:16;
201 } split;
202 unsigned int full;
203 };
204
205 /*
206 * Intel "Architectural Performance Monitoring extension" CPUID
207 * detection/enumeration details:
208 */
209 #define ARCH_PERFMON_EXT_LEAF 0x00000023
210 #define ARCH_PERFMON_NUM_COUNTER_LEAF 0x1
211 #define ARCH_PERFMON_ACR_LEAF 0x2
212 #define ARCH_PERFMON_PEBS_CAP_LEAF 0x4
213 #define ARCH_PERFMON_PEBS_COUNTER_LEAF 0x5
214
215 union cpuid35_eax {
216 struct {
217 unsigned int leaf0:1;
218 /* Counters Sub-Leaf */
219 unsigned int cntr_subleaf:1;
220 /* Auto Counter Reload Sub-Leaf */
221 unsigned int acr_subleaf:1;
222 /* Events Sub-Leaf */
223 unsigned int events_subleaf:1;
224 /* arch-PEBS Sub-Leaves */
225 unsigned int pebs_caps_subleaf:1;
226 unsigned int pebs_cnts_subleaf:1;
227 unsigned int reserved:26;
228 } split;
229 unsigned int full;
230 };
231
232 union cpuid35_ebx {
233 struct {
234 /* UnitMask2 Supported */
235 unsigned int umask2:1;
236 /* EQ-bit Supported */
237 unsigned int eq:1;
238 /* rdpmc user disable Supported */
239 unsigned int rdpmc_user_disable:1;
240 unsigned int reserved:29;
241 } split;
242 unsigned int full;
243 };
244
245 /*
246 * Intel Architectural LBR CPUID detection/enumeration details:
247 */
248 union cpuid28_eax {
249 struct {
250 /* Supported LBR depth values */
251 unsigned int lbr_depth_mask:8;
252 unsigned int reserved:22;
253 /* Deep C-state Reset */
254 unsigned int lbr_deep_c_reset:1;
255 /* IP values contain LIP */
256 unsigned int lbr_lip:1;
257 } split;
258 unsigned int full;
259 };
260
261 union cpuid28_ebx {
262 struct {
263 /* CPL Filtering Supported */
264 unsigned int lbr_cpl:1;
265 /* Branch Filtering Supported */
266 unsigned int lbr_filter:1;
267 /* Call-stack Mode Supported */
268 unsigned int lbr_call_stack:1;
269 } split;
270 unsigned int full;
271 };
272
273 union cpuid28_ecx {
274 struct {
275 /* Mispredict Bit Supported */
276 unsigned int lbr_mispred:1;
277 /* Timed LBRs Supported */
278 unsigned int lbr_timed_lbr:1;
279 /* Branch Type Field Supported */
280 unsigned int lbr_br_type:1;
281 unsigned int reserved:13;
282 /* Branch counters (Event Logging) Supported */
283 unsigned int lbr_counters:4;
284 } split;
285 unsigned int full;
286 };
287
288 /*
289 * AMD "Extended Performance Monitoring and Debug" CPUID
290 * detection/enumeration details:
291 */
292 union cpuid_0x80000022_ebx {
293 struct {
294 /* Number of Core Performance Counters */
295 unsigned int num_core_pmc:4;
296 /* Number of available LBR Stack Entries */
297 unsigned int lbr_v2_stack_sz:6;
298 /* Number of Data Fabric Counters */
299 unsigned int num_df_pmc:6;
300 /* Number of Unified Memory Controller Counters */
301 unsigned int num_umc_pmc:6;
302 } split;
303 unsigned int full;
304 };
305
306 struct x86_pmu_capability {
307 int version;
308 int num_counters_gp;
309 int num_counters_fixed;
310 int bit_width_gp;
311 int bit_width_fixed;
312 unsigned int events_mask;
313 int events_mask_len;
314 unsigned int pebs_ept :1;
315 unsigned int mediated :1;
316 };
317
318 /*
319 * Fixed-purpose performance events:
320 */
321
322 /* RDPMC offset for Fixed PMCs */
323 #define INTEL_PMC_FIXED_RDPMC_BASE (1 << 30)
324 #define INTEL_PMC_FIXED_RDPMC_METRICS (1 << 29)
325
326 /*
327 * All the fixed-mode PMCs are configured via this single MSR:
328 */
329 #define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
330
331 /*
332 * There is no event-code assigned to the fixed-mode PMCs.
333 *
334 * For a fixed-mode PMC, which has an equivalent event on a general-purpose
335 * PMC, the event-code of the equivalent event is used for the fixed-mode PMC,
336 * e.g., Instr_Retired.Any and CPU_CLK_Unhalted.Core.
337 *
338 * For a fixed-mode PMC, which doesn't have an equivalent event, a
339 * pseudo-encoding is used, e.g., CPU_CLK_Unhalted.Ref and TOPDOWN.SLOTS.
340 * The pseudo event-code for a fixed-mode PMC must be 0x00.
341 * The pseudo umask-code is 0xX. The X equals the index of the fixed
342 * counter + 1, e.g., the fixed counter 2 has the pseudo-encoding 0x0300.
343 *
344 * The counts are available in separate MSRs:
345 */
346
347 /* Instr_Retired.Any: */
348 #define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
349 #define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0)
350
351 /* CPU_CLK_Unhalted.Core: */
352 #define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
353 #define INTEL_PMC_IDX_FIXED_CPU_CYCLES (INTEL_PMC_IDX_FIXED + 1)
354
355 /* CPU_CLK_Unhalted.Ref: event=0x00,umask=0x3 (pseudo-encoding) */
356 #define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
357 #define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2)
358 #define INTEL_PMC_MSK_FIXED_REF_CYCLES (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)
359
360 /* TOPDOWN.SLOTS: event=0x00,umask=0x4 (pseudo-encoding) */
361 #define MSR_ARCH_PERFMON_FIXED_CTR3 0x30c
362 #define INTEL_PMC_IDX_FIXED_SLOTS (INTEL_PMC_IDX_FIXED + 3)
363 #define INTEL_PMC_MSK_FIXED_SLOTS (1ULL << INTEL_PMC_IDX_FIXED_SLOTS)
364
365 /* TOPDOWN_BAD_SPECULATION.ALL: fixed counter 4 (Atom only) */
366 /* TOPDOWN_FE_BOUND.ALL: fixed counter 5 (Atom only) */
367 /* TOPDOWN_RETIRING.ALL: fixed counter 6 (Atom only) */
368
use_fixed_pseudo_encoding(u64 code)369 static inline bool use_fixed_pseudo_encoding(u64 code)
370 {
371 return !(code & 0xff);
372 }
373
374 /*
375 * We model BTS tracing as another fixed-mode PMC.
376 *
377 * We choose the value 47 for the fixed index of BTS, since lower
378 * values are used by actual fixed events and higher values are used
379 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
380 */
381 #define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 15)
382
383 /*
384 * The PERF_METRICS MSR is modeled as several magic fixed-mode PMCs, one for
385 * each TopDown metric event.
386 *
387 * Internally the TopDown metric events are mapped to the FxCtr 3 (SLOTS).
388 */
389 #define INTEL_PMC_IDX_METRIC_BASE (INTEL_PMC_IDX_FIXED + 16)
390 #define INTEL_PMC_IDX_TD_RETIRING (INTEL_PMC_IDX_METRIC_BASE + 0)
391 #define INTEL_PMC_IDX_TD_BAD_SPEC (INTEL_PMC_IDX_METRIC_BASE + 1)
392 #define INTEL_PMC_IDX_TD_FE_BOUND (INTEL_PMC_IDX_METRIC_BASE + 2)
393 #define INTEL_PMC_IDX_TD_BE_BOUND (INTEL_PMC_IDX_METRIC_BASE + 3)
394 #define INTEL_PMC_IDX_TD_HEAVY_OPS (INTEL_PMC_IDX_METRIC_BASE + 4)
395 #define INTEL_PMC_IDX_TD_BR_MISPREDICT (INTEL_PMC_IDX_METRIC_BASE + 5)
396 #define INTEL_PMC_IDX_TD_FETCH_LAT (INTEL_PMC_IDX_METRIC_BASE + 6)
397 #define INTEL_PMC_IDX_TD_MEM_BOUND (INTEL_PMC_IDX_METRIC_BASE + 7)
398 #define INTEL_PMC_IDX_METRIC_END INTEL_PMC_IDX_TD_MEM_BOUND
399 #define INTEL_PMC_MSK_TOPDOWN ((0xffull << INTEL_PMC_IDX_METRIC_BASE) | \
400 INTEL_PMC_MSK_FIXED_SLOTS)
401
402 /*
403 * There is no event-code assigned to the TopDown events.
404 *
405 * For the slots event, use the pseudo code of the fixed counter 3.
406 *
407 * For the metric events, the pseudo event-code is 0x00.
408 * The pseudo umask-code starts from the middle of the pseudo event
409 * space, 0x80.
410 */
411 #define INTEL_TD_SLOTS 0x0400 /* TOPDOWN.SLOTS */
412 /* Level 1 metrics */
413 #define INTEL_TD_METRIC_RETIRING 0x8000 /* Retiring metric */
414 #define INTEL_TD_METRIC_BAD_SPEC 0x8100 /* Bad speculation metric */
415 #define INTEL_TD_METRIC_FE_BOUND 0x8200 /* FE bound metric */
416 #define INTEL_TD_METRIC_BE_BOUND 0x8300 /* BE bound metric */
417 /* Level 2 metrics */
418 #define INTEL_TD_METRIC_HEAVY_OPS 0x8400 /* Heavy Operations metric */
419 #define INTEL_TD_METRIC_BR_MISPREDICT 0x8500 /* Branch Mispredict metric */
420 #define INTEL_TD_METRIC_FETCH_LAT 0x8600 /* Fetch Latency metric */
421 #define INTEL_TD_METRIC_MEM_BOUND 0x8700 /* Memory bound metric */
422
423 #define INTEL_TD_METRIC_MAX INTEL_TD_METRIC_MEM_BOUND
424 #define INTEL_TD_METRIC_NUM 8
425
426 #define INTEL_TD_CFG_METRIC_CLEAR_BIT 0
427 #define INTEL_TD_CFG_METRIC_CLEAR BIT_ULL(INTEL_TD_CFG_METRIC_CLEAR_BIT)
428
is_metric_idx(int idx)429 static inline bool is_metric_idx(int idx)
430 {
431 return (unsigned)(idx - INTEL_PMC_IDX_METRIC_BASE) < INTEL_TD_METRIC_NUM;
432 }
433
is_topdown_idx(int idx)434 static inline bool is_topdown_idx(int idx)
435 {
436 return is_metric_idx(idx) || idx == INTEL_PMC_IDX_FIXED_SLOTS;
437 }
438
439 #define INTEL_PMC_OTHER_TOPDOWN_BITS(bit) \
440 (~(0x1ull << bit) & INTEL_PMC_MSK_TOPDOWN)
441
442 #define GLOBAL_STATUS_COND_CHG BIT_ULL(63)
443 #define GLOBAL_STATUS_BUFFER_OVF_BIT 62
444 #define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(GLOBAL_STATUS_BUFFER_OVF_BIT)
445 #define GLOBAL_STATUS_UNC_OVF BIT_ULL(61)
446 #define GLOBAL_STATUS_ASIF BIT_ULL(60)
447 #define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59)
448 #define GLOBAL_STATUS_LBRS_FROZEN_BIT 58
449 #define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(GLOBAL_STATUS_LBRS_FROZEN_BIT)
450 #define GLOBAL_STATUS_TRACE_TOPAPMI_BIT 55
451 #define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(GLOBAL_STATUS_TRACE_TOPAPMI_BIT)
452 #define GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT 54
453 #define GLOBAL_STATUS_ARCH_PEBS_THRESHOLD BIT_ULL(GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT)
454 #define GLOBAL_STATUS_PERF_METRICS_OVF_BIT 48
455
456 #define GLOBAL_CTRL_EN_PERF_METRICS BIT_ULL(48)
457 /*
458 * We model guest LBR event tracing as another fixed-mode PMC like BTS.
459 *
460 * We choose bit 58 because it's used to indicate LBR stack frozen state
461 * for architectural perfmon v4, also we unconditionally mask that bit in
462 * the handle_pmi_common(), so it'll never be set in the overflow handling.
463 *
464 * With this fake counter assigned, the guest LBR event user (such as KVM),
465 * can program the LBR registers on its own, and we don't actually do anything
466 * with then in the host context.
467 */
468 #define INTEL_PMC_IDX_FIXED_VLBR (GLOBAL_STATUS_LBRS_FROZEN_BIT)
469
470 /*
471 * Pseudo-encoding the guest LBR event as event=0x00,umask=0x1b,
472 * since it would claim bit 58 which is effectively Fixed26.
473 */
474 #define INTEL_FIXED_VLBR_EVENT 0x1b00
475
476 /*
477 * Adaptive PEBS v4
478 */
479
480 struct pebs_basic {
481 u64 format_group:32,
482 retire_latency:16,
483 format_size:16;
484 u64 ip;
485 u64 applicable_counters;
486 u64 tsc;
487 };
488
489 struct pebs_meminfo {
490 u64 address;
491 u64 aux;
492 union {
493 /* pre Alder Lake */
494 u64 mem_latency;
495 /* Alder Lake and later */
496 struct {
497 u64 instr_latency:16;
498 u64 pad2:16;
499 u64 cache_latency:16;
500 u64 pad3:16;
501 };
502 };
503 u64 tsx_tuning;
504 };
505
506 struct pebs_gprs {
507 u64 flags, ip, ax, cx, dx, bx, sp, bp, si, di;
508 u64 r8, r9, r10, r11, r12, r13, r14, r15;
509 };
510
511 struct pebs_xmm {
512 u64 xmm[16*2]; /* two entries for each register */
513 };
514
515 struct pebs_cntr_header {
516 u32 cntr;
517 u32 fixed;
518 u32 metrics;
519 u32 reserved;
520 };
521
522 #define INTEL_CNTR_METRICS 0x3
523
524 /*
525 * Arch PEBS
526 */
527 union arch_pebs_index {
528 struct {
529 u64 rsvd:4,
530 wr:23,
531 rsvd2:4,
532 full:1,
533 en:1,
534 rsvd3:3,
535 thresh:23,
536 rsvd4:5;
537 };
538 u64 whole;
539 };
540
541 struct arch_pebs_header {
542 union {
543 u64 format;
544 struct {
545 u64 size:16, /* Record size */
546 rsvd:14,
547 mode:1, /* 64BIT_MODE */
548 cont:1,
549 rsvd2:3,
550 cntr:5,
551 lbr:2,
552 rsvd3:7,
553 xmm:1,
554 ymmh:1,
555 egpr:1,
556 rsvd4:1,
557 opmask:1,
558 zmmh:1,
559 h16zmm:1,
560 rsvd5:5,
561 gpr:1,
562 aux:1,
563 basic:1;
564 };
565 };
566 u64 rsvd6;
567 };
568
569 struct arch_pebs_basic {
570 u64 ip;
571 u64 applicable_counters;
572 u64 tsc;
573 u64 retire :16, /* Retire Latency */
574 valid :1,
575 rsvd :47;
576 u64 rsvd2;
577 u64 rsvd3;
578 };
579
580 struct arch_pebs_aux {
581 u64 address;
582 u64 rsvd;
583 u64 rsvd2;
584 u64 rsvd3;
585 u64 rsvd4;
586 u64 aux;
587 u64 instr_latency :16,
588 pad2 :16,
589 cache_latency :16,
590 pad3 :16;
591 u64 tsx_tuning;
592 };
593
594 struct arch_pebs_gprs {
595 u64 flags, ip, ax, cx, dx, bx, sp, bp, si, di;
596 u64 r8, r9, r10, r11, r12, r13, r14, r15, ssp;
597 u64 rsvd;
598 };
599
600 struct arch_pebs_xer_header {
601 u64 xstate;
602 u64 rsvd;
603 };
604
605 #define ARCH_PEBS_LBR_NAN 0x0
606 #define ARCH_PEBS_LBR_NUM_8 0x1
607 #define ARCH_PEBS_LBR_NUM_16 0x2
608 #define ARCH_PEBS_LBR_NUM_VAR 0x3
609 #define ARCH_PEBS_BASE_LBR_ENTRIES 8
610 struct arch_pebs_lbr_header {
611 u64 rsvd;
612 u64 ctl;
613 u64 depth;
614 u64 ler_from;
615 u64 ler_to;
616 u64 ler_info;
617 };
618
619 struct arch_pebs_cntr_header {
620 u32 cntr;
621 u32 fixed;
622 u32 metrics;
623 u32 reserved;
624 };
625
626 /*
627 * AMD Extended Performance Monitoring and Debug cpuid feature detection
628 */
629 #define EXT_PERFMON_DEBUG_FEATURES 0x80000022
630
631 /*
632 * IBS cpuid feature detection
633 */
634
635 #define IBS_CPUID_FEATURES 0x8000001b
636
637 /*
638 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
639 * bit 0 is used to indicate the existence of IBS.
640 */
641 #define IBS_CAPS_AVAIL (1U<<0)
642 #define IBS_CAPS_FETCHSAM (1U<<1)
643 #define IBS_CAPS_OPSAM (1U<<2)
644 #define IBS_CAPS_RDWROPCNT (1U<<3)
645 #define IBS_CAPS_OPCNT (1U<<4)
646 #define IBS_CAPS_BRNTRGT (1U<<5)
647 #define IBS_CAPS_OPCNTEXT (1U<<6)
648 #define IBS_CAPS_RIPINVALIDCHK (1U<<7)
649 #define IBS_CAPS_OPBRNFUSE (1U<<8)
650 #define IBS_CAPS_FETCHCTLEXTD (1U<<9)
651 #define IBS_CAPS_OPDATA4 (1U<<10)
652 #define IBS_CAPS_ZEN4 (1U<<11)
653 #define IBS_CAPS_OPLDLAT (1U<<12)
654 #define IBS_CAPS_DIS (1U<<13)
655 #define IBS_CAPS_FETCHLAT (1U<<14)
656 #define IBS_CAPS_BIT63_FILTER (1U<<15)
657 #define IBS_CAPS_STRMST_RMTSOCKET (1U<<16)
658 #define IBS_CAPS_OPDTLBPGSIZE (1U<<19)
659
660 #define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \
661 | IBS_CAPS_FETCHSAM \
662 | IBS_CAPS_OPSAM)
663
664 /*
665 * IBS APIC setup
666 */
667 #define IBSCTL 0x1cc
668 #define IBSCTL_LVT_OFFSET_VALID (1ULL<<8)
669 #define IBSCTL_LVT_OFFSET_MASK 0x0F
670
671 /* IBS fetch bits/masks */
672 #define IBS_FETCH_L3MISSONLY (1ULL << 59)
673 #define IBS_FETCH_RAND_EN (1ULL << 57)
674 #define IBS_FETCH_VAL (1ULL << 49)
675 #define IBS_FETCH_ENABLE (1ULL << 48)
676 #define IBS_FETCH_CNT 0xFFFF0000ULL
677 #define IBS_FETCH_MAX_CNT 0x0000FFFFULL
678
679 #define IBS_FETCH_2_DIS (1ULL << 0)
680 #define IBS_FETCH_2_FETCHLAT_FILTER (0xFULL << 1)
681 #define IBS_FETCH_2_FETCHLAT_FILTER_SHIFT (1)
682 #define IBS_FETCH_2_EXCL_RIP_63_EQ_1 (1ULL << 5)
683 #define IBS_FETCH_2_EXCL_RIP_63_EQ_0 (1ULL << 6)
684
685 /*
686 * IBS op bits/masks
687 * The lower 7 bits of the current count are random bits
688 * preloaded by hardware and ignored in software
689 */
690 #define IBS_OP_LDLAT_EN (1ULL << 63)
691 #define IBS_OP_LDLAT_THRSH (0xFULL << 59)
692 #define IBS_OP_LDLAT_THRSH_SHIFT (59)
693 #define IBS_OP_CUR_CNT (0xFFF80ULL << 32)
694 #define IBS_OP_CUR_CNT_RAND (0x0007FULL << 32)
695 #define IBS_OP_CUR_CNT_EXT_MASK (0x7FULL << 52)
696 #define IBS_OP_CNT_CTL (1ULL << 19)
697 #define IBS_OP_VAL (1ULL << 18)
698 #define IBS_OP_ENABLE (1ULL << 17)
699 #define IBS_OP_L3MISSONLY (1ULL << 16)
700 #define IBS_OP_MAX_CNT 0x0000FFFFULL
701 #define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */
702 #define IBS_OP_MAX_CNT_EXT_MASK (0x7FULL << 20) /* separate upper 7 bits */
703 #define IBS_RIP_INVALID (1ULL << 38)
704
705 #define IBS_OP_2_DIS (1ULL << 0)
706 #define IBS_OP_2_EXCL_RIP_63_EQ_0 (1ULL << 1)
707 #define IBS_OP_2_EXCL_RIP_63_EQ_1 (1ULL << 2)
708 #define IBS_OP_2_STRM_ST_FILTER (1ULL << 3)
709 #define IBS_OP_2_STRM_ST_FILTER_SHIFT (3)
710
711 #ifdef CONFIG_X86_LOCAL_APIC
712 extern u32 get_ibs_caps(void);
713 extern int forward_event_to_ibs(struct perf_event *event);
714 #else
get_ibs_caps(void)715 static inline u32 get_ibs_caps(void) { return 0; }
forward_event_to_ibs(struct perf_event * event)716 static inline int forward_event_to_ibs(struct perf_event *event) { return -ENOENT; }
717 #endif
718
719 #ifdef CONFIG_PERF_EVENTS
720 extern void perf_events_lapic_init(void);
721
722 /*
723 * Abuse bits {3,5} of the cpu eflags register. These flags are otherwise
724 * unused and ABI specified to be 0, so nobody should care what we do with
725 * them.
726 *
727 * EXACT - the IP points to the exact instruction that triggered the
728 * event (HW bugs exempt).
729 * VM - original X86_VM_MASK; see set_linear_ip().
730 */
731 #define PERF_EFLAGS_EXACT (1UL << 3)
732 #define PERF_EFLAGS_VM (1UL << 5)
733
734 struct pt_regs;
735 struct x86_perf_regs {
736 struct pt_regs regs;
737 u64 abi;
738 union {
739 u64 *xmm_regs;
740 u32 *xmm_space; /* for xsaves */
741 };
742 union {
743 u64 *ymmh_regs;
744 struct ymmh_struct *ymmh;
745 };
746 union {
747 u64 *zmmh_regs;
748 struct avx_512_zmm_uppers_state *zmmh;
749 };
750 union {
751 u64 *h16zmm_regs;
752 struct avx_512_hi16_state *h16zmm;
753 };
754 union {
755 u64 *opmask_regs;
756 struct avx_512_opmask_state *opmask;
757 };
758 union {
759 u64 *egpr_regs;
760 struct apx_state *egpr;
761 };
762 u64 *ssp;
763 };
764
765 extern unsigned long perf_arch_instruction_pointer(struct pt_regs *regs);
766 extern unsigned long perf_arch_misc_flags(struct pt_regs *regs);
767 extern unsigned long perf_arch_guest_misc_flags(struct pt_regs *regs);
768 #define perf_arch_misc_flags(regs) perf_arch_misc_flags(regs)
769 #define perf_arch_guest_misc_flags(regs) perf_arch_guest_misc_flags(regs)
770
771 #include <asm/stacktrace.h>
772
773 /*
774 * We abuse bit 3 from flags to pass exact information, see
775 * perf_arch_misc_flags() and the comment with PERF_EFLAGS_EXACT.
776 */
777 #define perf_arch_fetch_caller_regs(regs, __ip) { \
778 (regs)->ip = (__ip); \
779 (regs)->sp = (unsigned long)__builtin_frame_address(0); \
780 (regs)->cs = __KERNEL_CS; \
781 regs->flags = 0; \
782 }
783
784 struct perf_guest_switch_msr {
785 unsigned msr;
786 u64 host, guest;
787 };
788
789 struct x86_pmu_lbr {
790 unsigned int nr;
791 unsigned int from;
792 unsigned int to;
793 unsigned int info;
794 bool has_callstack;
795 };
796
797 extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
798 extern u64 perf_get_hw_event_config(int hw_event);
799 extern void perf_check_microcode(void);
800 extern void perf_clear_dirty_counters(void);
801 extern int x86_perf_rdpmc_index(struct perf_event *event);
802 #else
perf_get_x86_pmu_capability(struct x86_pmu_capability * cap)803 static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
804 {
805 memset(cap, 0, sizeof(*cap));
806 }
807
perf_get_hw_event_config(int hw_event)808 static inline u64 perf_get_hw_event_config(int hw_event)
809 {
810 return 0;
811 }
812
perf_events_lapic_init(void)813 static inline void perf_events_lapic_init(void) { }
perf_check_microcode(void)814 static inline void perf_check_microcode(void) { }
815 #endif
816
817 #ifdef CONFIG_PERF_GUEST_MEDIATED_PMU
818 extern void perf_load_guest_lvtpc(u32 guest_lvtpc);
819 extern void perf_put_guest_lvtpc(void);
820 #endif
821
822 struct x86_guest_pebs {
823 u64 enable;
824 u64 ds_area;
825 u64 data_cfg;
826 };
827 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL)
828 extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr,
829 struct x86_guest_pebs *guest_pebs);
830 extern void x86_perf_get_lbr(struct x86_pmu_lbr *lbr);
831 #else
832 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr,
833 struct x86_guest_pebs *guest_pebs);
x86_perf_get_lbr(struct x86_pmu_lbr * lbr)834 static inline void x86_perf_get_lbr(struct x86_pmu_lbr *lbr)
835 {
836 memset(lbr, 0, sizeof(*lbr));
837 }
838 #endif
839
840 #ifdef CONFIG_CPU_SUP_INTEL
841 extern void intel_pt_handle_vmx(int on);
842 #else
intel_pt_handle_vmx(int on)843 static inline void intel_pt_handle_vmx(int on)
844 {
845
846 }
847 #endif
848
849 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
850 extern void amd_pmu_enable_virt(void);
851 extern void amd_pmu_disable_virt(void);
852
853 #if defined(CONFIG_PERF_EVENTS_AMD_BRS)
854
855 #define PERF_NEEDS_LOPWR_CB 1
856
857 /*
858 * architectural low power callback impacts
859 * drivers/acpi/processor_idle.c
860 * drivers/acpi/acpi_pad.c
861 */
862 extern void perf_amd_brs_lopwr_cb(bool lopwr_in);
863
864 DECLARE_STATIC_CALL(perf_lopwr_cb, perf_amd_brs_lopwr_cb);
865
perf_lopwr_cb(bool lopwr_in)866 static __always_inline void perf_lopwr_cb(bool lopwr_in)
867 {
868 static_call_mod(perf_lopwr_cb)(lopwr_in);
869 }
870
871 #endif /* PERF_NEEDS_LOPWR_CB */
872
873 #else
amd_pmu_enable_virt(void)874 static inline void amd_pmu_enable_virt(void) { }
amd_pmu_disable_virt(void)875 static inline void amd_pmu_disable_virt(void) { }
876 #endif
877
878 #define arch_perf_out_copy_user copy_from_user_nmi
879
880 #endif /* _ASM_X86_PERF_EVENT_H */
881