1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_RING_H__ 25 #define __AMDGPU_RING_H__ 26 27 #include <drm/amdgpu_drm.h> 28 #include <drm/gpu_scheduler.h> 29 #include <drm/drm_print.h> 30 #include <drm/drm_suballoc.h> 31 32 struct amdgpu_device; 33 struct amdgpu_ring; 34 struct amdgpu_ib; 35 struct amdgpu_cs_parser; 36 struct amdgpu_job; 37 struct amdgpu_vm; 38 39 /* max number of rings */ 40 #define AMDGPU_MAX_RINGS 149 41 #define AMDGPU_MAX_HWIP_RINGS 64 42 #define AMDGPU_MAX_GFX_RINGS 2 43 #define AMDGPU_MAX_SW_GFX_RINGS 2 44 #define AMDGPU_MAX_COMPUTE_RINGS 8 45 #define AMDGPU_MAX_VCE_RINGS 3 46 #define AMDGPU_MAX_UVD_ENC_RINGS 2 47 #define AMDGPU_MAX_VPE_RINGS 2 48 49 enum amdgpu_ring_priority_level { 50 AMDGPU_RING_PRIO_0, 51 AMDGPU_RING_PRIO_1, 52 AMDGPU_RING_PRIO_DEFAULT = 1, 53 AMDGPU_RING_PRIO_2, 54 AMDGPU_RING_PRIO_MAX 55 }; 56 57 /* some special values for the owner field */ 58 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul) 59 #define AMDGPU_FENCE_OWNER_VM ((void *)1ul) 60 #define AMDGPU_FENCE_OWNER_KFD ((void *)2ul) 61 62 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 63 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 64 #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2) 65 66 /* Ensure the execution in case of preemption or reset */ 67 #define AMDGPU_FENCE_FLAG_EXEC (1 << 3) 68 69 #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched) 70 71 #define AMDGPU_IB_POOL_SIZE (1024 * 1024) 72 73 enum amdgpu_ring_type { 74 AMDGPU_RING_TYPE_GFX = AMDGPU_HW_IP_GFX, 75 AMDGPU_RING_TYPE_COMPUTE = AMDGPU_HW_IP_COMPUTE, 76 AMDGPU_RING_TYPE_SDMA = AMDGPU_HW_IP_DMA, 77 AMDGPU_RING_TYPE_UVD = AMDGPU_HW_IP_UVD, 78 AMDGPU_RING_TYPE_VCE = AMDGPU_HW_IP_VCE, 79 AMDGPU_RING_TYPE_UVD_ENC = AMDGPU_HW_IP_UVD_ENC, 80 AMDGPU_RING_TYPE_VCN_DEC = AMDGPU_HW_IP_VCN_DEC, 81 AMDGPU_RING_TYPE_VCN_ENC = AMDGPU_HW_IP_VCN_ENC, 82 AMDGPU_RING_TYPE_VCN_JPEG = AMDGPU_HW_IP_VCN_JPEG, 83 AMDGPU_RING_TYPE_VPE = AMDGPU_HW_IP_VPE, 84 AMDGPU_RING_TYPE_KIQ, 85 AMDGPU_RING_TYPE_MES, 86 AMDGPU_RING_TYPE_UMSCH_MM, 87 AMDGPU_RING_TYPE_CPER, 88 AMDGPU_RING_TYPE_MAX, 89 }; 90 91 enum amdgpu_ib_pool_type { 92 /* Normal submissions to the top of the pipeline. */ 93 AMDGPU_IB_POOL_DELAYED, 94 /* Immediate submissions to the bottom of the pipeline. */ 95 AMDGPU_IB_POOL_IMMEDIATE, 96 /* Direct submission to the ring buffer during init and reset. */ 97 AMDGPU_IB_POOL_DIRECT, 98 99 AMDGPU_IB_POOL_MAX 100 }; 101 102 struct amdgpu_ib { 103 struct drm_suballoc *sa_bo; 104 uint32_t length_dw; 105 uint64_t gpu_addr; 106 uint32_t *ptr; 107 uint32_t flags; 108 }; 109 110 struct amdgpu_sched { 111 u32 num_scheds; 112 struct drm_gpu_scheduler *sched[AMDGPU_MAX_HWIP_RINGS]; 113 }; 114 115 /* 116 * Fences. 117 */ 118 struct amdgpu_fence_driver { 119 uint64_t gpu_addr; 120 uint32_t *cpu_addr; 121 /* sync_seq is protected by ring emission lock */ 122 uint32_t sync_seq; 123 atomic_t last_seq; 124 u64 signalled_wptr; 125 bool initialized; 126 struct amdgpu_irq_src *irq_src; 127 unsigned irq_type; 128 struct timer_list fallback_timer; 129 unsigned num_fences_mask; 130 spinlock_t lock; 131 struct dma_fence **fences; 132 }; 133 134 /* 135 * Fences mark an event in the GPUs pipeline and are used 136 * for GPU/CPU synchronization. When the fence is written, 137 * it is expected that all buffers associated with that fence 138 * are no longer in use by the associated ring on the GPU and 139 * that the relevant GPU caches have been flushed. 140 */ 141 142 struct amdgpu_fence { 143 struct dma_fence base; 144 145 /* RB, DMA, etc. */ 146 struct amdgpu_ring *ring; 147 ktime_t start_timestamp; 148 149 /* wptr for the total submission for resets */ 150 u64 wptr; 151 /* fence context for resets */ 152 u64 context; 153 /* has this fence been reemitted */ 154 unsigned int reemitted; 155 /* wptr for the fence for the submission */ 156 u64 fence_wptr_start; 157 u64 fence_wptr_end; 158 }; 159 160 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 161 162 void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error); 163 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); 164 void amdgpu_fence_driver_update_timedout_fence_state(struct amdgpu_fence *af); 165 void amdgpu_fence_save_wptr(struct amdgpu_fence *af); 166 167 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); 168 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 169 struct amdgpu_irq_src *irq_src, 170 unsigned irq_type); 171 void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev); 172 void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev); 173 int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev); 174 void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev); 175 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af, 176 unsigned int flags); 177 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s, 178 uint32_t timeout); 179 bool amdgpu_fence_process(struct amdgpu_ring *ring); 180 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 181 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, 182 uint32_t wait_seq, 183 signed long timeout); 184 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 185 186 void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop); 187 188 u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring); 189 void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq, 190 ktime_t timestamp); 191 192 /* 193 * Rings. 194 */ 195 196 /* provided by hw blocks that expose a ring buffer for commands */ 197 struct amdgpu_ring_funcs { 198 /** 199 * @type: 200 * 201 * GFX, Compute, SDMA, UVD, VCE, VCN, VPE, KIQ, MES, UMSCH, and CPER 202 * use ring buffers. The type field just identifies which component the 203 * ring buffer is associated with. 204 */ 205 enum amdgpu_ring_type type; 206 uint32_t align_mask; 207 208 /** 209 * @nop: 210 * 211 * Every block in the amdgpu has no-op instructions (e.g., GFX 10 212 * uses PACKET3(PACKET3_NOP, 0x3FFF), VCN 5 uses VCN_ENC_CMD_NO_OP, 213 * etc). This field receives the specific no-op for the component 214 * that initializes the ring. 215 */ 216 u32 nop; 217 bool support_64bit_ptrs; 218 bool no_user_fence; 219 bool secure_submission_supported; 220 221 /** 222 * @extra_bytes: 223 * 224 * Optional extra space in bytes that is added to the ring size 225 * when allocating the BO that holds the contents of the ring. 226 * This space isn't used for command submission to the ring, 227 * but is just there to satisfy some hardware requirements or 228 * implement workarounds. It's up to the implementation of each 229 * specific ring to initialize this space. 230 */ 231 unsigned extra_bytes; 232 233 /* ring read/write ptr handling */ 234 u64 (*get_rptr)(struct amdgpu_ring *ring); 235 u64 (*get_wptr)(struct amdgpu_ring *ring); 236 void (*set_wptr)(struct amdgpu_ring *ring); 237 /* validating and patching of IBs */ 238 int (*parse_cs)(struct amdgpu_cs_parser *p, 239 struct amdgpu_job *job, 240 struct amdgpu_ib *ib); 241 int (*patch_cs_in_place)(struct amdgpu_cs_parser *p, 242 struct amdgpu_job *job, 243 struct amdgpu_ib *ib); 244 /* constants to calculate how many DW are needed for an emit */ 245 unsigned emit_frame_size; 246 unsigned emit_ib_size; 247 /* command emit functions */ 248 void (*emit_ib)(struct amdgpu_ring *ring, 249 struct amdgpu_job *job, 250 struct amdgpu_ib *ib, 251 uint32_t flags); 252 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 253 uint64_t seq, unsigned flags); 254 void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 255 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid, 256 uint64_t pd_addr); 257 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 258 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 259 uint32_t gds_base, uint32_t gds_size, 260 uint32_t gws_base, uint32_t gws_size, 261 uint32_t oa_base, uint32_t oa_size); 262 /* testing functions */ 263 int (*test_ring)(struct amdgpu_ring *ring); 264 int (*test_ib)(struct amdgpu_ring *ring, long timeout); 265 /* insert NOP packets */ 266 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 267 void (*insert_start)(struct amdgpu_ring *ring); 268 void (*insert_end)(struct amdgpu_ring *ring); 269 /* pad the indirect buffer to the necessary number of dw */ 270 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 271 unsigned (*init_cond_exec)(struct amdgpu_ring *ring, uint64_t addr); 272 /* note usage for clock and power gating */ 273 void (*begin_use)(struct amdgpu_ring *ring); 274 void (*end_use)(struct amdgpu_ring *ring); 275 void (*emit_switch_buffer) (struct amdgpu_ring *ring); 276 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); 277 void (*emit_gfx_shadow)(struct amdgpu_ring *ring, u64 shadow_va, u64 csa_va, 278 u64 gds_va, bool init_shadow, int vmid); 279 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg, 280 uint32_t reg_val_offs); 281 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); 282 void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg, 283 uint32_t val, uint32_t mask); 284 void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring, 285 uint32_t reg0, uint32_t reg1, 286 uint32_t ref, uint32_t mask); 287 void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start, 288 bool secure); 289 /* Try to soft recover the ring to make the fence signal */ 290 void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid); 291 int (*preempt_ib)(struct amdgpu_ring *ring); 292 void (*emit_mem_sync)(struct amdgpu_ring *ring); 293 void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable); 294 void (*patch_cntl)(struct amdgpu_ring *ring, unsigned offset); 295 void (*patch_ce)(struct amdgpu_ring *ring, unsigned offset); 296 void (*patch_de)(struct amdgpu_ring *ring, unsigned offset); 297 int (*reset)(struct amdgpu_ring *ring, unsigned int vmid, 298 struct amdgpu_fence *timedout_fence); 299 void (*emit_cleaner_shader)(struct amdgpu_ring *ring); 300 }; 301 302 /** 303 * amdgpu_ring - Holds ring information 304 */ 305 struct amdgpu_ring { 306 struct amdgpu_device *adev; 307 const struct amdgpu_ring_funcs *funcs; 308 struct amdgpu_fence_driver fence_drv; 309 struct drm_gpu_scheduler sched; 310 311 struct amdgpu_bo *ring_obj; 312 uint32_t *ring; 313 /* backups for resets */ 314 uint32_t *ring_backup; 315 unsigned int ring_backup_entries_to_copy; 316 unsigned rptr_offs; 317 u64 rptr_gpu_addr; 318 u32 *rptr_cpu_addr; 319 320 /** 321 * @wptr: 322 * 323 * This is part of the Ring buffer implementation and represents the 324 * write pointer. The wptr determines where the host has written. 325 */ 326 u64 wptr; 327 328 /** 329 * @wptr_old: 330 * 331 * Before update wptr with the new value, usually the old value is 332 * stored in the wptr_old. 333 */ 334 u64 wptr_old; 335 unsigned ring_size; 336 337 /** 338 * @max_dw: 339 * 340 * Maximum number of DWords for ring allocation. This information is 341 * provided at the ring initialization time, and each IP block can 342 * specify a specific value. Check places that invoke 343 * amdgpu_ring_init() to see the maximum size per block. 344 */ 345 unsigned max_dw; 346 347 /** 348 * @count_dw: 349 * 350 * This value starts with the maximum amount of DWords supported by the 351 * ring. This value is updated based on the ring manipulation. 352 */ 353 int count_dw; 354 uint64_t gpu_addr; 355 356 /** 357 * @ptr_mask: 358 * 359 * Some IPs provide support for 64-bit pointers and others for 32-bit 360 * only; this behavior is component-specific and defined by the field 361 * support_64bit_ptr. If the IP block supports 64-bits, the mask 362 * 0xffffffffffffffff is set; otherwise, this value assumes buf_mask. 363 * Notice that this field is used to keep wptr under a valid range. 364 */ 365 uint64_t ptr_mask; 366 367 /** 368 * @buf_mask: 369 * 370 * Buffer mask is a value used to keep wptr count under its 371 * thresholding. Buffer mask initialized during the ring buffer 372 * initialization time, and it is defined as (ring_size / 4) -1. 373 */ 374 uint32_t buf_mask; 375 u32 idx; 376 u32 xcc_id; 377 u32 xcp_id; 378 u32 me; 379 u32 pipe; 380 u32 queue; 381 struct amdgpu_bo *mqd_obj; 382 uint64_t mqd_gpu_addr; 383 void *mqd_ptr; 384 unsigned mqd_size; 385 uint64_t eop_gpu_addr; 386 u32 doorbell_index; 387 bool use_doorbell; 388 bool use_pollmem; 389 unsigned wptr_offs; 390 u64 wptr_gpu_addr; 391 392 /** 393 * @wptr_cpu_addr: 394 * 395 * This is the CPU address pointer in the writeback slot. This is used 396 * to commit changes to the GPU. 397 */ 398 u32 *wptr_cpu_addr; 399 unsigned fence_offs; 400 u64 fence_gpu_addr; 401 u32 *fence_cpu_addr; 402 uint64_t current_ctx; 403 char name[16]; 404 u32 trail_seq; 405 unsigned trail_fence_offs; 406 u64 trail_fence_gpu_addr; 407 u32 *trail_fence_cpu_addr; 408 unsigned cond_exe_offs; 409 u64 cond_exe_gpu_addr; 410 u32 *cond_exe_cpu_addr; 411 unsigned int set_q_mode_offs; 412 u32 *set_q_mode_ptr; 413 u64 set_q_mode_token; 414 unsigned vm_hub; 415 unsigned vm_inv_eng; 416 struct dma_fence *vmid_wait; 417 bool has_compute_vm_bug; 418 bool no_scheduler; 419 bool no_user_submission; 420 int hw_prio; 421 unsigned num_hw_submission; 422 atomic_t *sched_score; 423 424 bool is_sw_ring; 425 unsigned int entry_index; 426 /* store the cached rptr to restore after reset */ 427 uint64_t cached_rptr; 428 }; 429 430 #define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib))) 431 #define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib))) 432 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 433 #define amdgpu_ring_test_ib(r, t) ((r)->funcs->test_ib ? (r)->funcs->test_ib((r), (t)) : 0) 434 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 435 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 436 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 437 #define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags))) 438 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 439 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 440 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 441 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 442 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 443 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 444 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 445 #define amdgpu_ring_emit_gfx_shadow(r, s, c, g, i, v) ((r)->funcs->emit_gfx_shadow((r), (s), (c), (g), (i), (v))) 446 #define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o)) 447 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 448 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m)) 449 #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m)) 450 #define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s)) 451 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 452 #define amdgpu_ring_init_cond_exec(r, a) (r)->funcs->init_cond_exec((r), (a)) 453 #define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r) 454 #define amdgpu_ring_patch_cntl(r, o) ((r)->funcs->patch_cntl((r), (o))) 455 #define amdgpu_ring_patch_ce(r, o) ((r)->funcs->patch_ce((r), (o))) 456 #define amdgpu_ring_patch_de(r, o) ((r)->funcs->patch_de((r), (o))) 457 #define amdgpu_ring_reset(r, v, f) (r)->funcs->reset((r), (v), (f)) 458 459 unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type); 460 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 461 void amdgpu_ring_ib_begin(struct amdgpu_ring *ring); 462 void amdgpu_ring_ib_end(struct amdgpu_ring *ring); 463 void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring); 464 void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring); 465 void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring); 466 467 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 468 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 469 void amdgpu_ring_commit(struct amdgpu_ring *ring); 470 void amdgpu_ring_undo(struct amdgpu_ring *ring); 471 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 472 unsigned int max_dw, struct amdgpu_irq_src *irq_src, 473 unsigned int irq_type, unsigned int hw_prio, 474 atomic_t *sched_score); 475 void amdgpu_ring_fini(struct amdgpu_ring *ring); 476 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, 477 uint32_t reg0, uint32_t val0, 478 uint32_t reg1, uint32_t val1); 479 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, 480 struct dma_fence *fence); 481 482 static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring, 483 bool cond_exec) 484 { 485 *ring->cond_exe_cpu_addr = cond_exec; 486 } 487 488 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) 489 { 490 memset32(ring->ring, ring->funcs->nop, ring->buf_mask + 1); 491 } 492 493 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 494 { 495 ring->ring[ring->wptr++ & ring->buf_mask] = v; 496 ring->wptr &= ring->ptr_mask; 497 ring->count_dw--; 498 } 499 500 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, 501 void *src, int count_dw) 502 { 503 unsigned occupied, chunk1, chunk2; 504 505 occupied = ring->wptr & ring->buf_mask; 506 chunk1 = ring->buf_mask + 1 - occupied; 507 chunk1 = (chunk1 >= count_dw) ? count_dw : chunk1; 508 chunk2 = count_dw - chunk1; 509 chunk1 <<= 2; 510 chunk2 <<= 2; 511 512 if (chunk1) 513 memcpy(&ring->ring[occupied], src, chunk1); 514 515 if (chunk2) { 516 src += chunk1; 517 memcpy(ring->ring, src, chunk2); 518 } 519 520 ring->wptr += count_dw; 521 ring->wptr &= ring->ptr_mask; 522 ring->count_dw -= count_dw; 523 } 524 525 /** 526 * amdgpu_ring_patch_cond_exec - patch dw count of conditional execute 527 * @ring: amdgpu_ring structure 528 * @offset: offset returned by amdgpu_ring_init_cond_exec 529 * 530 * Calculate the dw count and patch it into a cond_exec command. 531 */ 532 static inline void amdgpu_ring_patch_cond_exec(struct amdgpu_ring *ring, 533 unsigned int offset) 534 { 535 unsigned cur; 536 537 if (!ring->funcs->init_cond_exec) 538 return; 539 540 WARN_ON(offset > ring->buf_mask); 541 WARN_ON(ring->ring[offset] != 0); 542 543 cur = (ring->wptr - 1) & ring->buf_mask; 544 if (cur < offset) 545 cur += ring->ring_size >> 2; 546 ring->ring[offset] = cur - offset; 547 } 548 549 int amdgpu_ring_test_helper(struct amdgpu_ring *ring); 550 551 void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, 552 struct amdgpu_ring *ring); 553 554 int amdgpu_ring_init_mqd(struct amdgpu_ring *ring); 555 556 static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, int idx) 557 { 558 return ib->ptr[idx]; 559 } 560 561 static inline void amdgpu_ib_set_value(struct amdgpu_ib *ib, int idx, 562 uint32_t value) 563 { 564 ib->ptr[idx] = value; 565 } 566 567 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 568 unsigned size, 569 enum amdgpu_ib_pool_type pool, 570 struct amdgpu_ib *ib); 571 void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f); 572 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 573 struct amdgpu_ib *ibs, struct amdgpu_job *job, 574 struct dma_fence **f); 575 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 576 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 577 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 578 bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring); 579 void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring, 580 struct amdgpu_fence *guilty_fence); 581 void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring, 582 struct amdgpu_fence *guilty_fence); 583 int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring, 584 struct amdgpu_fence *guilty_fence); 585 bool amdgpu_ring_is_reset_type_supported(struct amdgpu_ring *ring, 586 u32 reset_type); 587 #endif 588