1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Stuff for AMCC S5933 PCI Controller 4 * 5 * Author: Michal Dobes <dobes@tesnet.cz> 6 * 7 * Inspirated from general-purpose AMCC S5933 PCI Matchmaker driver 8 * made by Andrea Cisternino <acister@pcape1.pi.infn.it> 9 * and as result of espionage from MITE code made by David A. Schleef. 10 * Thanks to AMCC for their on-line documentation and bus master DMA 11 * example. 12 */ 13 14 #ifndef _AMCC_S5933_H_ 15 #define _AMCC_S5933_H_ 16 17 /****************************************************************************/ 18 /* AMCC Operation Register Offsets - PCI */ 19 /****************************************************************************/ 20 21 #define AMCC_OP_REG_OMB1 0x00 22 #define AMCC_OP_REG_OMB2 0x04 23 #define AMCC_OP_REG_OMB3 0x08 24 #define AMCC_OP_REG_OMB4 0x0c 25 #define AMCC_OP_REG_IMB1 0x10 26 #define AMCC_OP_REG_IMB2 0x14 27 #define AMCC_OP_REG_IMB3 0x18 28 #define AMCC_OP_REG_IMB4 0x1c 29 #define AMCC_OP_REG_FIFO 0x20 30 #define AMCC_OP_REG_MWAR 0x24 31 #define AMCC_OP_REG_MWTC 0x28 32 #define AMCC_OP_REG_MRAR 0x2c 33 #define AMCC_OP_REG_MRTC 0x30 34 #define AMCC_OP_REG_MBEF 0x34 35 #define AMCC_OP_REG_INTCSR 0x38 36 #define AMCC_OP_REG_INTCSR_SRC (AMCC_OP_REG_INTCSR + 2) /* INT source */ 37 #define AMCC_OP_REG_INTCSR_FEC (AMCC_OP_REG_INTCSR + 3) /* FIFO ctrl */ 38 #define AMCC_OP_REG_MCSR 0x3c 39 #define AMCC_OP_REG_MCSR_NVDATA (AMCC_OP_REG_MCSR + 2) /* Data in byte 2 */ 40 #define AMCC_OP_REG_MCSR_NVCMD (AMCC_OP_REG_MCSR + 3) /* Command in byte 3 */ 41 42 #define AMCC_FIFO_DEPTH_DWORD 8 43 #define AMCC_FIFO_DEPTH_BYTES (8 * sizeof(u32)) 44 45 /****************************************************************************/ 46 /* AMCC - PCI Interrupt Control/Status Register */ 47 /****************************************************************************/ 48 #define INTCSR_OUTBOX_BYTE(x) ((x) & 0x3) 49 #define INTCSR_OUTBOX_SELECT(x) (((x) & 0x3) << 2) 50 #define INTCSR_OUTBOX_EMPTY_INT 0x10 /* enable outbox empty interrupt */ 51 #define INTCSR_INBOX_BYTE(x) (((x) & 0x3) << 8) 52 #define INTCSR_INBOX_SELECT(x) (((x) & 0x3) << 10) 53 #define INTCSR_INBOX_FULL_INT 0x1000 /* enable inbox full interrupt */ 54 /* read, or write clear inbox full interrupt */ 55 #define INTCSR_INBOX_INTR_STATUS 0x20000 56 /* read only, interrupt asserted */ 57 #define INTCSR_INTR_ASSERTED 0x800000 58 59 /****************************************************************************/ 60 /* AMCC - PCI non-volatile ram command register (byte 3 of AMCC_OP_REG_MCSR) */ 61 /****************************************************************************/ 62 #define MCSR_NV_LOAD_LOW_ADDR 0x0 63 #define MCSR_NV_LOAD_HIGH_ADDR 0x20 64 #define MCSR_NV_WRITE 0x40 65 #define MCSR_NV_READ 0x60 66 #define MCSR_NV_MASK 0x60 67 #define MCSR_NV_ENABLE 0x80 68 #define MCSR_NV_BUSY MCSR_NV_ENABLE 69 70 /****************************************************************************/ 71 /* AMCC Operation Registers Size - PCI */ 72 /****************************************************************************/ 73 74 #define AMCC_OP_REG_SIZE 64 /* in bytes */ 75 76 /****************************************************************************/ 77 /* AMCC Operation Register Offsets - Add-on */ 78 /****************************************************************************/ 79 80 #define AMCC_OP_REG_AIMB1 0x00 81 #define AMCC_OP_REG_AIMB2 0x04 82 #define AMCC_OP_REG_AIMB3 0x08 83 #define AMCC_OP_REG_AIMB4 0x0c 84 #define AMCC_OP_REG_AOMB1 0x10 85 #define AMCC_OP_REG_AOMB2 0x14 86 #define AMCC_OP_REG_AOMB3 0x18 87 #define AMCC_OP_REG_AOMB4 0x1c 88 #define AMCC_OP_REG_AFIFO 0x20 89 #define AMCC_OP_REG_AMWAR 0x24 90 #define AMCC_OP_REG_APTA 0x28 91 #define AMCC_OP_REG_APTD 0x2c 92 #define AMCC_OP_REG_AMRAR 0x30 93 #define AMCC_OP_REG_AMBEF 0x34 94 #define AMCC_OP_REG_AINT 0x38 95 #define AMCC_OP_REG_AGCSTS 0x3c 96 #define AMCC_OP_REG_AMWTC 0x58 97 #define AMCC_OP_REG_AMRTC 0x5c 98 99 /****************************************************************************/ 100 /* AMCC - Add-on General Control/Status Register */ 101 /****************************************************************************/ 102 103 #define AGCSTS_CONTROL_MASK 0xfffff000 104 #define AGCSTS_NV_ACC_MASK 0xe0000000 105 #define AGCSTS_RESET_MASK 0x0e000000 106 #define AGCSTS_NV_DA_MASK 0x00ff0000 107 #define AGCSTS_BIST_MASK 0x0000f000 108 #define AGCSTS_STATUS_MASK 0x000000ff 109 #define AGCSTS_TCZERO_MASK 0x000000c0 110 #define AGCSTS_FIFO_ST_MASK 0x0000003f 111 112 #define AGCSTS_TC_ENABLE 0x10000000 113 114 #define AGCSTS_RESET_MBFLAGS 0x08000000 115 #define AGCSTS_RESET_P2A_FIFO 0x04000000 116 #define AGCSTS_RESET_A2P_FIFO 0x02000000 117 #define AGCSTS_RESET_FIFOS (AGCSTS_RESET_A2P_FIFO | AGCSTS_RESET_P2A_FIFO) 118 119 #define AGCSTS_A2P_TCOUNT 0x00000080 120 #define AGCSTS_P2A_TCOUNT 0x00000040 121 122 #define AGCSTS_FS_P2A_EMPTY 0x00000020 123 #define AGCSTS_FS_P2A_HALF 0x00000010 124 #define AGCSTS_FS_P2A_FULL 0x00000008 125 126 #define AGCSTS_FS_A2P_EMPTY 0x00000004 127 #define AGCSTS_FS_A2P_HALF 0x00000002 128 #define AGCSTS_FS_A2P_FULL 0x00000001 129 130 /****************************************************************************/ 131 /* AMCC - Add-on Interrupt Control/Status Register */ 132 /****************************************************************************/ 133 134 #define AINT_INT_MASK 0x00ff0000 135 #define AINT_SEL_MASK 0x0000ffff 136 #define AINT_IS_ENSEL_MASK 0x00001f1f 137 138 #define AINT_INT_ASSERTED 0x00800000 139 #define AINT_BM_ERROR 0x00200000 140 #define AINT_BIST_INT 0x00100000 141 142 #define AINT_RT_COMPLETE 0x00080000 143 #define AINT_WT_COMPLETE 0x00040000 144 145 #define AINT_OUT_MB_INT 0x00020000 146 #define AINT_IN_MB_INT 0x00010000 147 148 #define AINT_READ_COMPL 0x00008000 149 #define AINT_WRITE_COMPL 0x00004000 150 151 #define AINT_OMB_ENABLE 0x00001000 152 #define AINT_OMB_SELECT 0x00000c00 153 #define AINT_OMB_BYTE 0x00000300 154 155 #define AINT_IMB_ENABLE 0x00000010 156 #define AINT_IMB_SELECT 0x0000000c 157 #define AINT_IMB_BYTE 0x00000003 158 159 /* these are bits from various different registers, needs cleanup XXX */ 160 /* Enable Bus Mastering */ 161 #define EN_A2P_TRANSFERS 0x00000400 162 /* FIFO Flag Reset */ 163 #define RESET_A2P_FLAGS 0x04000000L 164 /* FIFO Relative Priority */ 165 #define A2P_HI_PRIORITY 0x00000100L 166 /* Identify Interrupt Sources */ 167 #define ANY_S593X_INT 0x00800000L 168 #define READ_TC_INT 0x00080000L 169 #define WRITE_TC_INT 0x00040000L 170 #define IN_MB_INT 0x00020000L 171 #define MASTER_ABORT_INT 0x00100000L 172 #define TARGET_ABORT_INT 0x00200000L 173 #define BUS_MASTER_INT 0x00200000L 174 175 #endif 176