1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for the Airoha EN8811H and AN8811HB 2.5 Gigabit PHYs.
4 *
5 * Limitations:
6 * - Only full duplex supported
7 * - Forced speed (AN off) is not supported by hardware (100Mbps)
8 *
9 * Source originated from airoha's en8811h.c and en8811h.h v1.2.1
10 * with AN8811HB bits from air_an8811hb.c v0.0.4
11 *
12 * Copyright (C) 2023, 2026 Airoha Technology Corp.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/phy.h>
18 #include <linux/phy/phy-common-props.h>
19 #include <linux/firmware.h>
20 #include <linux/bitfield.h>
21 #include <linux/property.h>
22 #include <linux/wordpart.h>
23 #include <linux/unaligned.h>
24
25 #define EN8811H_PHY_ID 0x03a2a411
26 #define AN8811HB_PHY_ID 0xc0ff04a0
27
28 #define EN8811H_MD32_DM "airoha/EthMD32.dm.bin"
29 #define EN8811H_MD32_DSP "airoha/EthMD32.DSP.bin"
30 #define AN8811HB_MD32_DM "airoha/an8811hb/EthMD32_CRC.DM.bin"
31 #define AN8811HB_MD32_DSP "airoha/an8811hb/EthMD32_CRC.DSP.bin"
32
33 #define AIR_FW_ADDR_DM 0x00000000
34 #define AIR_FW_ADDR_DSP 0x00100000
35
36 /* MII Registers */
37 #define AIR_AUX_CTRL_STATUS 0x1d
38 #define AIR_AUX_CTRL_STATUS_SPEED_MASK GENMASK(4, 2)
39 #define AIR_AUX_CTRL_STATUS_SPEED_10 0x0
40 #define AIR_AUX_CTRL_STATUS_SPEED_100 0x4
41 #define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8
42 #define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc
43
44 #define AIR_EXT_PAGE_ACCESS 0x1f
45 #define AIR_PHY_PAGE_STANDARD 0x0000
46 #define AIR_PHY_PAGE_EXTENDED_4 0x0004
47
48 /* MII Registers Page 4*/
49 #define AIR_BPBUS_MODE 0x10
50 #define AIR_BPBUS_MODE_ADDR_FIXED 0x0000
51 #define AIR_BPBUS_MODE_ADDR_INCR BIT(15)
52 #define AIR_BPBUS_WR_ADDR_HIGH 0x11
53 #define AIR_BPBUS_WR_ADDR_LOW 0x12
54 #define AIR_BPBUS_WR_DATA_HIGH 0x13
55 #define AIR_BPBUS_WR_DATA_LOW 0x14
56 #define AIR_BPBUS_RD_ADDR_HIGH 0x15
57 #define AIR_BPBUS_RD_ADDR_LOW 0x16
58 #define AIR_BPBUS_RD_DATA_HIGH 0x17
59 #define AIR_BPBUS_RD_DATA_LOW 0x18
60
61 /* Registers on MDIO_MMD_VEND1 */
62 #define EN8811H_PHY_FW_STATUS 0x8009
63 #define EN8811H_PHY_READY 0x02
64
65 #define AIR_PHY_MCU_CMD_0 0x800b
66 #define AIR_PHY_MCU_CMD_1 0x800c
67 #define AIR_PHY_MCU_CMD_1_MODE1 0x0
68 #define AIR_PHY_MCU_CMD_2 0x800d
69 #define AIR_PHY_MCU_CMD_2_MODE1 0x0
70 #define AIR_PHY_MCU_CMD_3 0x800e
71 #define AIR_PHY_MCU_CMD_3_MODE1 0x1101
72 #define AIR_PHY_MCU_CMD_3_DOCMD 0x1100
73 #define AIR_PHY_MCU_CMD_4 0x800f
74 #define AIR_PHY_MCU_CMD_4_MODE1 0x0002
75 #define AIR_PHY_MCU_CMD_4_CABLE_PAIR_A 0x00d7
76 #define AIR_PHY_MCU_CMD_4_CABLE_PAIR_B 0x00d8
77 #define AIR_PHY_MCU_CMD_4_CABLE_PAIR_C 0x00d9
78 #define AIR_PHY_MCU_CMD_4_CABLE_PAIR_D 0x00da
79 #define AIR_PHY_MCU_CMD_4_INTCLR 0x00e4
80
81 /* Registers on MDIO_MMD_VEND2 */
82 #define AIR_PHY_LED_BCR 0x021
83 #define AIR_PHY_LED_BCR_MODE_MASK GENMASK(1, 0)
84 #define AIR_PHY_LED_BCR_TIME_TEST BIT(2)
85 #define AIR_PHY_LED_BCR_CLK_EN BIT(3)
86 #define AIR_PHY_LED_BCR_EXT_CTRL BIT(15)
87
88 #define AIR_PHY_LED_DUR_ON 0x022
89
90 #define AIR_PHY_LED_DUR_BLINK 0x023
91
92 #define AIR_PHY_LED_ON(i) (0x024 + ((i) * 2))
93 #define AIR_PHY_LED_ON_MASK (GENMASK(6, 0) | BIT(8))
94 #define AIR_PHY_LED_ON_LINK1000 BIT(0)
95 #define AIR_PHY_LED_ON_LINK100 BIT(1)
96 #define AIR_PHY_LED_ON_LINK10 BIT(2)
97 #define AIR_PHY_LED_ON_LINKDOWN BIT(3)
98 #define AIR_PHY_LED_ON_FDX BIT(4) /* Full duplex */
99 #define AIR_PHY_LED_ON_HDX BIT(5) /* Half duplex */
100 #define AIR_PHY_LED_ON_FORCE_ON BIT(6)
101 #define AIR_PHY_LED_ON_LINK2500 BIT(8)
102 #define AIR_PHY_LED_ON_POLARITY BIT(14)
103 #define AIR_PHY_LED_ON_ENABLE BIT(15)
104
105 #define AIR_PHY_LED_BLINK(i) (0x025 + ((i) * 2))
106 #define AIR_PHY_LED_BLINK_1000TX BIT(0)
107 #define AIR_PHY_LED_BLINK_1000RX BIT(1)
108 #define AIR_PHY_LED_BLINK_100TX BIT(2)
109 #define AIR_PHY_LED_BLINK_100RX BIT(3)
110 #define AIR_PHY_LED_BLINK_10TX BIT(4)
111 #define AIR_PHY_LED_BLINK_10RX BIT(5)
112 #define AIR_PHY_LED_BLINK_COLLISION BIT(6)
113 #define AIR_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
114 #define AIR_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
115 #define AIR_PHY_LED_BLINK_FORCE_BLINK BIT(9)
116 #define AIR_PHY_LED_BLINK_2500TX BIT(10)
117 #define AIR_PHY_LED_BLINK_2500RX BIT(11)
118
119 /* Registers on BUCKPBUS */
120 #define AIR_PHY_CONTROL 0x3a9c
121 #define AIR_PHY_CONTROL_INTERNAL BIT(11)
122
123 #define EN8811H_2P5G_LPA 0x3b30
124 #define EN8811H_2P5G_LPA_2P5G BIT(0)
125
126 #define EN8811H_FW_VERSION 0x3b3c
127
128 #define EN8811H_POLARITY 0xca0f8
129 #define EN8811H_POLARITY_TX_NORMAL BIT(0)
130 #define EN8811H_POLARITY_RX_REVERSE BIT(1)
131
132 #define EN8811H_GPIO_OUTPUT 0xcf8b8
133 #define EN8811H_GPIO_OUTPUT_345 (BIT(3) | BIT(4) | BIT(5))
134
135 #define EN8811H_HWTRAP1 0xcf914
136 #define EN8811H_HWTRAP1_CKO BIT(12)
137 #define EN8811H_CLK_CGM 0xcf958
138 #define EN8811H_CLK_CGM_CKO BIT(26)
139
140 #define EN8811H_FW_CTRL_1 0x0f0018
141 #define EN8811H_FW_CTRL_1_START 0x0
142 #define EN8811H_FW_CTRL_1_FINISH 0x1
143 #define EN8811H_FW_CTRL_2 0x800000
144 #define EN8811H_FW_CTRL_2_LOADING BIT(11)
145
146 #define AN8811HB_CRC_PM_SET1 0xf020c
147 #define AN8811HB_CRC_PM_MON2 0xf0218
148 #define AN8811HB_CRC_PM_MON3 0xf021c
149 #define AN8811HB_CRC_DM_SET1 0xf0224
150 #define AN8811HB_CRC_DM_MON2 0xf0230
151 #define AN8811HB_CRC_DM_MON3 0xf0234
152 #define AN8811HB_CRC_RD_EN BIT(0)
153 #define AN8811HB_CRC_ST (BIT(0) | BIT(1))
154 #define AN8811HB_CRC_CHECK_PASS BIT(0)
155
156 #define AN8811HB_TX_POLARITY 0x5ce004
157 #define AN8811HB_TX_POLARITY_NORMAL BIT(7)
158 #define AN8811HB_RX_POLARITY 0x5ce61c
159 #define AN8811HB_RX_POLARITY_NORMAL BIT(7)
160
161 #define AN8811HB_GPIO_OUTPUT 0x5cf8b8
162 #define AN8811HB_GPIO_OUTPUT_345 (BIT(3) | BIT(4) | BIT(5))
163
164 #define AN8811HB_HWTRAP1 0x5cf910
165 #define AN8811HB_HWTRAP2 0x5cf914
166 #define AN8811HB_HWTRAP2_CKO BIT(28)
167
168 #define AN8811HB_CLK_DRV 0x5cf9e4
169 #define AN8811HB_CLK_DRV_CKO_MASK GENMASK(14, 12)
170 #define AN8811HB_CLK_DRV_CKOPWD BIT(12)
171 #define AN8811HB_CLK_DRV_CKO_LDPWD BIT(13)
172 #define AN8811HB_CLK_DRV_CKO_LPPWD BIT(14)
173
174 #define AN8811HB_MCU_SW_RST 0x5cf9f8
175 #define AN8811HB_MCU_SW_RST_HOLD BIT(16)
176 #define AN8811HB_MCU_SW_RST_RUN (BIT(16) | BIT(0))
177 #define AN8811HB_MCU_SW_START 0x5cf9fc
178 #define AN8811HB_MCU_SW_START_EN BIT(16)
179
180 /* MII register constants for PBUS access (PHY addr + 8) */
181 #define AIR_PBUS_ADDR_HIGH 0x1c
182 #define AIR_PBUS_DATA_HIGH 0x10
183 #define AIR_PBUS_REG_ADDR_HIGH_MASK GENMASK(15, 6)
184 #define AIR_PBUS_REG_ADDR_LOW_MASK GENMASK(5, 2)
185
186 /* Led definitions */
187 #define EN8811H_LED_COUNT 3
188
189 #define EN8811H_PBUS_ADDR_OFFS 8
190
191 /* Default LED setup:
192 * GPIO5 <-> LED0 On: Link detected, blink Rx/Tx
193 * GPIO4 <-> LED1 On: Link detected at 2500 or 1000 Mbps
194 * GPIO3 <-> LED2 On: Link detected at 2500 or 100 Mbps
195 */
196 #define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK) | \
197 BIT(TRIGGER_NETDEV_RX) | \
198 BIT(TRIGGER_NETDEV_TX))
199 #define AIR_DEFAULT_TRIGGER_LED1 (BIT(TRIGGER_NETDEV_LINK_2500) | \
200 BIT(TRIGGER_NETDEV_LINK_1000))
201 #define AIR_DEFAULT_TRIGGER_LED2 (BIT(TRIGGER_NETDEV_LINK_2500) | \
202 BIT(TRIGGER_NETDEV_LINK_100))
203
204 struct led {
205 unsigned long rules;
206 unsigned long state;
207 };
208
209 #define clk_hw_to_en8811h_priv(_hw) \
210 container_of(_hw, struct en8811h_priv, hw)
211
212 struct en8811h_priv {
213 u32 firmware_version;
214 bool mcu_needs_restart;
215 struct led led[EN8811H_LED_COUNT];
216 struct clk_hw hw;
217 struct phy_device *phydev;
218 unsigned int cko_is_enabled;
219 struct mdio_device *pbusdev;
220 };
221
222 enum {
223 AIR_PHY_LED_STATE_FORCE_ON,
224 AIR_PHY_LED_STATE_FORCE_BLINK,
225 };
226
227 enum {
228 AIR_PHY_LED_DUR_BLINK_32MS,
229 AIR_PHY_LED_DUR_BLINK_64MS,
230 AIR_PHY_LED_DUR_BLINK_128MS,
231 AIR_PHY_LED_DUR_BLINK_256MS,
232 AIR_PHY_LED_DUR_BLINK_512MS,
233 AIR_PHY_LED_DUR_BLINK_1024MS,
234 };
235
236 enum {
237 AIR_LED_DISABLE,
238 AIR_LED_ENABLE,
239 };
240
241 enum {
242 AIR_ACTIVE_LOW,
243 AIR_ACTIVE_HIGH,
244 };
245
246 enum {
247 AIR_LED_MODE_DISABLE,
248 AIR_LED_MODE_USER_DEFINE,
249 };
250
251 #define AIR_PHY_LED_DUR_UNIT 1024
252 #define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64MS)
253
254 static const unsigned long en8811h_led_trig = BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
255 BIT(TRIGGER_NETDEV_LINK) |
256 BIT(TRIGGER_NETDEV_LINK_10) |
257 BIT(TRIGGER_NETDEV_LINK_100) |
258 BIT(TRIGGER_NETDEV_LINK_1000) |
259 BIT(TRIGGER_NETDEV_LINK_2500) |
260 BIT(TRIGGER_NETDEV_RX) |
261 BIT(TRIGGER_NETDEV_TX);
262
air_phy_read_page(struct phy_device * phydev)263 static int air_phy_read_page(struct phy_device *phydev)
264 {
265 return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
266 }
267
air_phy_write_page(struct phy_device * phydev,int page)268 static int air_phy_write_page(struct phy_device *phydev, int page)
269 {
270 return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
271 }
272
__air_pbus_reg_write(struct mdio_device * mdiodev,u32 pbus_reg,u32 pbus_data)273 static int __air_pbus_reg_write(struct mdio_device *mdiodev,
274 u32 pbus_reg, u32 pbus_data)
275 {
276 int ret;
277
278 ret = __mdiobus_write(mdiodev->bus, mdiodev->addr, AIR_EXT_PAGE_ACCESS,
279 upper_16_bits(pbus_reg));
280 if (ret < 0)
281 return ret;
282
283 ret = __mdiobus_write(mdiodev->bus, mdiodev->addr, AIR_PBUS_ADDR_HIGH,
284 FIELD_GET(AIR_PBUS_REG_ADDR_HIGH_MASK, pbus_reg));
285 if (ret < 0)
286 return ret;
287
288 ret = __mdiobus_write(mdiodev->bus, mdiodev->addr,
289 FIELD_GET(AIR_PBUS_REG_ADDR_LOW_MASK, pbus_reg),
290 lower_16_bits(pbus_data));
291 if (ret < 0)
292 return ret;
293
294 return __mdiobus_write(mdiodev->bus, mdiodev->addr, AIR_PBUS_DATA_HIGH,
295 upper_16_bits(pbus_data));
296 }
297
__air_buckpbus_reg_write(struct phy_device * phydev,u32 pbus_address,u32 pbus_data)298 static int __air_buckpbus_reg_write(struct phy_device *phydev,
299 u32 pbus_address, u32 pbus_data)
300 {
301 int ret;
302
303 ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
304 if (ret < 0)
305 return ret;
306
307 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
308 upper_16_bits(pbus_address));
309 if (ret < 0)
310 return ret;
311
312 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
313 lower_16_bits(pbus_address));
314 if (ret < 0)
315 return ret;
316
317 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
318 upper_16_bits(pbus_data));
319 if (ret < 0)
320 return ret;
321
322 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
323 lower_16_bits(pbus_data));
324 if (ret < 0)
325 return ret;
326
327 return 0;
328 }
329
air_buckpbus_reg_write(struct phy_device * phydev,u32 pbus_address,u32 pbus_data)330 static int air_buckpbus_reg_write(struct phy_device *phydev,
331 u32 pbus_address, u32 pbus_data)
332 {
333 int saved_page;
334 int ret = 0;
335
336 saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
337
338 if (saved_page >= 0) {
339 ret = __air_buckpbus_reg_write(phydev, pbus_address,
340 pbus_data);
341 if (ret < 0)
342 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
343 pbus_address, ret);
344 }
345
346 return phy_restore_page(phydev, saved_page, ret);
347 }
348
__air_buckpbus_reg_read(struct phy_device * phydev,u32 pbus_address,u32 * pbus_data)349 static int __air_buckpbus_reg_read(struct phy_device *phydev,
350 u32 pbus_address, u32 *pbus_data)
351 {
352 int pbus_data_low, pbus_data_high;
353 int ret;
354
355 ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
356 if (ret < 0)
357 return ret;
358
359 ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
360 upper_16_bits(pbus_address));
361 if (ret < 0)
362 return ret;
363
364 ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
365 lower_16_bits(pbus_address));
366 if (ret < 0)
367 return ret;
368
369 pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
370 if (pbus_data_high < 0)
371 return pbus_data_high;
372
373 pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
374 if (pbus_data_low < 0)
375 return pbus_data_low;
376
377 *pbus_data = pbus_data_low | (pbus_data_high << 16);
378 return 0;
379 }
380
air_buckpbus_reg_read(struct phy_device * phydev,u32 pbus_address,u32 * pbus_data)381 static int air_buckpbus_reg_read(struct phy_device *phydev,
382 u32 pbus_address, u32 *pbus_data)
383 {
384 int saved_page;
385 int ret = 0;
386
387 saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
388
389 if (saved_page >= 0) {
390 ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
391 if (ret < 0)
392 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
393 pbus_address, ret);
394 }
395
396 return phy_restore_page(phydev, saved_page, ret);
397 }
398
__air_buckpbus_reg_modify(struct phy_device * phydev,u32 pbus_address,u32 mask,u32 set)399 static int __air_buckpbus_reg_modify(struct phy_device *phydev,
400 u32 pbus_address, u32 mask, u32 set)
401 {
402 int pbus_data_low, pbus_data_high;
403 u32 pbus_data_old, pbus_data_new;
404 int ret;
405
406 ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
407 if (ret < 0)
408 return ret;
409
410 ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
411 upper_16_bits(pbus_address));
412 if (ret < 0)
413 return ret;
414
415 ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
416 lower_16_bits(pbus_address));
417 if (ret < 0)
418 return ret;
419
420 pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
421 if (pbus_data_high < 0)
422 return pbus_data_high;
423
424 pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
425 if (pbus_data_low < 0)
426 return pbus_data_low;
427
428 pbus_data_old = pbus_data_low | (pbus_data_high << 16);
429 pbus_data_new = (pbus_data_old & ~mask) | set;
430 if (pbus_data_new == pbus_data_old)
431 return 0;
432
433 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
434 upper_16_bits(pbus_address));
435 if (ret < 0)
436 return ret;
437
438 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
439 lower_16_bits(pbus_address));
440 if (ret < 0)
441 return ret;
442
443 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
444 upper_16_bits(pbus_data_new));
445 if (ret < 0)
446 return ret;
447
448 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
449 lower_16_bits(pbus_data_new));
450 if (ret < 0)
451 return ret;
452
453 return 0;
454 }
455
air_buckpbus_reg_modify(struct phy_device * phydev,u32 pbus_address,u32 mask,u32 set)456 static int air_buckpbus_reg_modify(struct phy_device *phydev,
457 u32 pbus_address, u32 mask, u32 set)
458 {
459 int saved_page;
460 int ret = 0;
461
462 saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
463
464 if (saved_page >= 0) {
465 ret = __air_buckpbus_reg_modify(phydev, pbus_address, mask,
466 set);
467 if (ret < 0)
468 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
469 pbus_address, ret);
470 }
471
472 return phy_restore_page(phydev, saved_page, ret);
473 }
474
__air_write_buf(struct phy_device * phydev,u32 address,const struct firmware * fw)475 static int __air_write_buf(struct phy_device *phydev, u32 address,
476 const struct firmware *fw)
477 {
478 unsigned int offset;
479 int ret;
480 u16 val;
481
482 ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_INCR);
483 if (ret < 0)
484 return ret;
485
486 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
487 upper_16_bits(address));
488 if (ret < 0)
489 return ret;
490
491 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
492 lower_16_bits(address));
493 if (ret < 0)
494 return ret;
495
496 for (offset = 0; offset < fw->size; offset += 4) {
497 val = get_unaligned_le16(&fw->data[offset + 2]);
498 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, val);
499 if (ret < 0)
500 return ret;
501
502 val = get_unaligned_le16(&fw->data[offset]);
503 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, val);
504 if (ret < 0)
505 return ret;
506 }
507
508 return 0;
509 }
510
air_write_buf(struct phy_device * phydev,u32 address,const struct firmware * fw)511 static int air_write_buf(struct phy_device *phydev, u32 address,
512 const struct firmware *fw)
513 {
514 int saved_page;
515 int ret = 0;
516
517 saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
518
519 if (saved_page >= 0) {
520 ret = __air_write_buf(phydev, address, fw);
521 if (ret < 0)
522 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
523 address, ret);
524 }
525
526 return phy_restore_page(phydev, saved_page, ret);
527 }
528
en8811h_wait_mcu_ready(struct phy_device * phydev)529 static int en8811h_wait_mcu_ready(struct phy_device *phydev)
530 {
531 int ret, reg_value;
532
533 ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
534 EN8811H_FW_CTRL_1_FINISH);
535 if (ret)
536 return ret;
537
538 /* Because of mdio-lock, may have to wait for multiple loads */
539 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
540 EN8811H_PHY_FW_STATUS, reg_value,
541 reg_value == EN8811H_PHY_READY,
542 20000, 7500000, true);
543 if (ret) {
544 phydev_err(phydev, "MCU not ready: 0x%x\n", reg_value);
545 return -ENODEV;
546 }
547
548 return 0;
549 }
550
an8811hb_check_crc(struct phy_device * phydev,u32 set1,u32 mon2,u32 mon3)551 static int an8811hb_check_crc(struct phy_device *phydev, u32 set1,
552 u32 mon2, u32 mon3)
553 {
554 u32 pbus_value;
555 int retry = 25;
556 int ret;
557
558 /* Configure CRC */
559 ret = air_buckpbus_reg_modify(phydev, set1,
560 AN8811HB_CRC_RD_EN,
561 AN8811HB_CRC_RD_EN);
562 if (ret < 0)
563 return ret;
564 air_buckpbus_reg_read(phydev, set1, &pbus_value);
565
566 do {
567 msleep(300);
568 air_buckpbus_reg_read(phydev, mon2, &pbus_value);
569
570 /* We do not know what errors this check is supposed
571 * catch or what to do about a failure. So print the
572 * result and continue like the vendor driver does.
573 */
574 if (pbus_value & AN8811HB_CRC_ST) {
575 air_buckpbus_reg_read(phydev, mon3, &pbus_value);
576 phydev_dbg(phydev, "CRC Check %s!\n",
577 pbus_value & AN8811HB_CRC_CHECK_PASS ?
578 "PASS" : "FAIL");
579 return air_buckpbus_reg_modify(phydev, set1,
580 AN8811HB_CRC_RD_EN, 0);
581 }
582 } while (--retry);
583
584 phydev_err(phydev, "CRC Check is not ready (%u)\n", pbus_value);
585 return -ENODEV;
586 }
587
en8811h_print_fw_version(struct phy_device * phydev)588 static void en8811h_print_fw_version(struct phy_device *phydev)
589 {
590 struct en8811h_priv *priv = phydev->priv;
591
592 air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION,
593 &priv->firmware_version);
594 phydev_info(phydev, "MD32 firmware version: %08x\n",
595 priv->firmware_version);
596 }
597
an8811hb_load_file(struct phy_device * phydev,const char * name,u32 address)598 static int an8811hb_load_file(struct phy_device *phydev, const char *name,
599 u32 address)
600 {
601 struct device *dev = &phydev->mdio.dev;
602 const struct firmware *fw;
603 int ret;
604
605 ret = request_firmware_direct(&fw, name, dev);
606 if (ret < 0)
607 return ret;
608
609 ret = air_write_buf(phydev, address, fw);
610 release_firmware(fw);
611 return ret;
612 }
613
an8811hb_mcu_assert(struct phy_device * phydev)614 static int an8811hb_mcu_assert(struct phy_device *phydev)
615 {
616 struct en8811h_priv *priv = phydev->priv;
617 int ret;
618
619 phy_lock_mdio_bus(phydev);
620
621 ret = __air_pbus_reg_write(priv->pbusdev, AN8811HB_MCU_SW_RST,
622 AN8811HB_MCU_SW_RST_HOLD);
623 if (ret < 0)
624 goto unlock;
625
626 ret = __air_pbus_reg_write(priv->pbusdev, AN8811HB_MCU_SW_START, 0);
627 if (ret < 0)
628 goto unlock;
629
630 msleep(50);
631 phydev_dbg(phydev, "MCU asserted\n");
632
633 unlock:
634 phy_unlock_mdio_bus(phydev);
635 return ret;
636 }
637
an8811hb_mcu_deassert(struct phy_device * phydev)638 static int an8811hb_mcu_deassert(struct phy_device *phydev)
639 {
640 struct en8811h_priv *priv = phydev->priv;
641 int ret;
642
643 phy_lock_mdio_bus(phydev);
644
645 ret = __air_pbus_reg_write(priv->pbusdev, AN8811HB_MCU_SW_START,
646 AN8811HB_MCU_SW_START_EN);
647 if (ret < 0)
648 goto unlock;
649
650 ret = __air_pbus_reg_write(priv->pbusdev, AN8811HB_MCU_SW_RST,
651 AN8811HB_MCU_SW_RST_RUN);
652 if (ret < 0)
653 goto unlock;
654
655 msleep(50);
656 phydev_dbg(phydev, "MCU deasserted\n");
657
658 unlock:
659 phy_unlock_mdio_bus(phydev);
660 return ret;
661 }
662
an8811hb_load_firmware(struct phy_device * phydev)663 static int an8811hb_load_firmware(struct phy_device *phydev)
664 {
665 int ret;
666
667 ret = an8811hb_mcu_assert(phydev);
668 if (ret < 0)
669 return ret;
670
671 ret = an8811hb_mcu_deassert(phydev);
672 if (ret < 0)
673 return ret;
674
675 ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
676 EN8811H_FW_CTRL_1_START);
677 if (ret < 0)
678 return ret;
679
680 ret = an8811hb_load_file(phydev, AN8811HB_MD32_DM, AIR_FW_ADDR_DM);
681 if (ret < 0)
682 return ret;
683
684 ret = an8811hb_check_crc(phydev, AN8811HB_CRC_DM_SET1,
685 AN8811HB_CRC_DM_MON2,
686 AN8811HB_CRC_DM_MON3);
687 if (ret < 0)
688 return ret;
689
690 ret = an8811hb_load_file(phydev, AN8811HB_MD32_DSP, AIR_FW_ADDR_DSP);
691 if (ret < 0)
692 return ret;
693
694 ret = an8811hb_check_crc(phydev, AN8811HB_CRC_PM_SET1,
695 AN8811HB_CRC_PM_MON2,
696 AN8811HB_CRC_PM_MON3);
697 if (ret < 0)
698 return ret;
699
700 return en8811h_wait_mcu_ready(phydev);
701 }
702
en8811h_load_firmware(struct phy_device * phydev)703 static int en8811h_load_firmware(struct phy_device *phydev)
704 {
705 struct device *dev = &phydev->mdio.dev;
706 const struct firmware *fw1, *fw2;
707 int ret;
708
709 ret = request_firmware_direct(&fw1, EN8811H_MD32_DM, dev);
710 if (ret < 0)
711 return ret;
712
713 ret = request_firmware_direct(&fw2, EN8811H_MD32_DSP, dev);
714 if (ret < 0)
715 goto en8811h_load_firmware_rel1;
716
717 ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
718 EN8811H_FW_CTRL_1_START);
719 if (ret < 0)
720 goto en8811h_load_firmware_out;
721
722 ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
723 EN8811H_FW_CTRL_2_LOADING,
724 EN8811H_FW_CTRL_2_LOADING);
725 if (ret < 0)
726 goto en8811h_load_firmware_out;
727
728 ret = air_write_buf(phydev, AIR_FW_ADDR_DM, fw1);
729 if (ret < 0)
730 goto en8811h_load_firmware_out;
731
732 ret = air_write_buf(phydev, AIR_FW_ADDR_DSP, fw2);
733 if (ret < 0)
734 goto en8811h_load_firmware_out;
735
736 ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
737 EN8811H_FW_CTRL_2_LOADING, 0);
738 if (ret < 0)
739 goto en8811h_load_firmware_out;
740
741 ret = en8811h_wait_mcu_ready(phydev);
742 if (ret < 0)
743 goto en8811h_load_firmware_out;
744
745 en8811h_print_fw_version(phydev);
746
747 en8811h_load_firmware_out:
748 release_firmware(fw2);
749
750 en8811h_load_firmware_rel1:
751 release_firmware(fw1);
752
753 if (ret < 0)
754 phydev_err(phydev, "Load firmware failed: %d\n", ret);
755
756 return ret;
757 }
758
en8811h_restart_mcu(struct phy_device * phydev)759 static int en8811h_restart_mcu(struct phy_device *phydev)
760 {
761 int ret;
762
763 if (phy_id_compare_model(phydev->phy_id, AN8811HB_PHY_ID)) {
764 ret = an8811hb_mcu_assert(phydev);
765 if (ret < 0)
766 return ret;
767
768 ret = an8811hb_mcu_deassert(phydev);
769 if (ret < 0)
770 return ret;
771 }
772
773 ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
774 EN8811H_FW_CTRL_1_START);
775 if (ret < 0)
776 return ret;
777
778 return en8811h_wait_mcu_ready(phydev);
779 }
780
air_hw_led_on_set(struct phy_device * phydev,u8 index,bool on)781 static int air_hw_led_on_set(struct phy_device *phydev, u8 index, bool on)
782 {
783 struct en8811h_priv *priv = phydev->priv;
784 bool changed;
785
786 if (index >= EN8811H_LED_COUNT)
787 return -EINVAL;
788
789 if (on)
790 changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_ON,
791 &priv->led[index].state);
792 else
793 changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_ON,
794 &priv->led[index].state);
795
796 changed |= (priv->led[index].rules != 0);
797
798 /* clear netdev trigger rules in case LED_OFF has been set */
799 if (!on)
800 priv->led[index].rules = 0;
801
802 if (changed)
803 return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
804 AIR_PHY_LED_ON(index),
805 AIR_PHY_LED_ON_MASK,
806 on ? AIR_PHY_LED_ON_FORCE_ON : 0);
807
808 return 0;
809 }
810
air_hw_led_blink_set(struct phy_device * phydev,u8 index,bool blinking)811 static int air_hw_led_blink_set(struct phy_device *phydev, u8 index,
812 bool blinking)
813 {
814 struct en8811h_priv *priv = phydev->priv;
815 bool changed;
816
817 if (index >= EN8811H_LED_COUNT)
818 return -EINVAL;
819
820 if (blinking)
821 changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
822 &priv->led[index].state);
823 else
824 changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
825 &priv->led[index].state);
826
827 changed |= (priv->led[index].rules != 0);
828
829 if (changed)
830 return phy_write_mmd(phydev, MDIO_MMD_VEND2,
831 AIR_PHY_LED_BLINK(index),
832 blinking ?
833 AIR_PHY_LED_BLINK_FORCE_BLINK : 0);
834 else
835 return 0;
836 }
837
air_led_blink_set(struct phy_device * phydev,u8 index,unsigned long * delay_on,unsigned long * delay_off)838 static int air_led_blink_set(struct phy_device *phydev, u8 index,
839 unsigned long *delay_on,
840 unsigned long *delay_off)
841 {
842 struct en8811h_priv *priv = phydev->priv;
843 bool blinking = false;
844 int err;
845
846 if (index >= EN8811H_LED_COUNT)
847 return -EINVAL;
848
849 if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
850 blinking = true;
851 *delay_on = 50;
852 *delay_off = 50;
853 }
854
855 err = air_hw_led_blink_set(phydev, index, blinking);
856 if (err)
857 return err;
858
859 /* led-blink set, so switch led-on off */
860 err = air_hw_led_on_set(phydev, index, false);
861 if (err)
862 return err;
863
864 /* hw-control is off*/
865 if (!!test_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state))
866 priv->led[index].rules = 0;
867
868 return 0;
869 }
870
air_led_brightness_set(struct phy_device * phydev,u8 index,enum led_brightness value)871 static int air_led_brightness_set(struct phy_device *phydev, u8 index,
872 enum led_brightness value)
873 {
874 struct en8811h_priv *priv = phydev->priv;
875 int err;
876
877 if (index >= EN8811H_LED_COUNT)
878 return -EINVAL;
879
880 /* led-on set, so switch led-blink off */
881 err = air_hw_led_blink_set(phydev, index, false);
882 if (err)
883 return err;
884
885 err = air_hw_led_on_set(phydev, index, (value != LED_OFF));
886 if (err)
887 return err;
888
889 /* hw-control is off */
890 if (!!test_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state))
891 priv->led[index].rules = 0;
892
893 return 0;
894 }
895
air_led_hw_control_get(struct phy_device * phydev,u8 index,unsigned long * rules)896 static int air_led_hw_control_get(struct phy_device *phydev, u8 index,
897 unsigned long *rules)
898 {
899 struct en8811h_priv *priv = phydev->priv;
900
901 if (index >= EN8811H_LED_COUNT)
902 return -EINVAL;
903
904 *rules = priv->led[index].rules;
905
906 return 0;
907 };
908
air_led_hw_control_set(struct phy_device * phydev,u8 index,unsigned long rules)909 static int air_led_hw_control_set(struct phy_device *phydev, u8 index,
910 unsigned long rules)
911 {
912 struct en8811h_priv *priv = phydev->priv;
913 u16 on = 0, blink = 0;
914 int ret;
915
916 if (index >= EN8811H_LED_COUNT)
917 return -EINVAL;
918
919 priv->led[index].rules = rules;
920
921 if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
922 on |= AIR_PHY_LED_ON_FDX;
923
924 if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
925 on |= AIR_PHY_LED_ON_LINK10;
926
927 if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
928 on |= AIR_PHY_LED_ON_LINK100;
929
930 if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
931 on |= AIR_PHY_LED_ON_LINK1000;
932
933 if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK)))
934 on |= AIR_PHY_LED_ON_LINK2500;
935
936 if (rules & BIT(TRIGGER_NETDEV_RX)) {
937 blink |= AIR_PHY_LED_BLINK_10RX |
938 AIR_PHY_LED_BLINK_100RX |
939 AIR_PHY_LED_BLINK_1000RX |
940 AIR_PHY_LED_BLINK_2500RX;
941 }
942
943 if (rules & BIT(TRIGGER_NETDEV_TX)) {
944 blink |= AIR_PHY_LED_BLINK_10TX |
945 AIR_PHY_LED_BLINK_100TX |
946 AIR_PHY_LED_BLINK_1000TX |
947 AIR_PHY_LED_BLINK_2500TX;
948 }
949
950 if (blink || on) {
951 /* switch hw-control on, so led-on and led-blink are off */
952 clear_bit(AIR_PHY_LED_STATE_FORCE_ON,
953 &priv->led[index].state);
954 clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
955 &priv->led[index].state);
956 } else {
957 priv->led[index].rules = 0;
958 }
959
960 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
961 AIR_PHY_LED_ON_MASK, on);
962
963 if (ret < 0)
964 return ret;
965
966 return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index),
967 blink);
968 };
969
air_led_init(struct phy_device * phydev,u8 index,u8 state,u8 pol)970 static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol)
971 {
972 int val = 0;
973 int err;
974
975 if (index >= EN8811H_LED_COUNT)
976 return -EINVAL;
977
978 if (state == AIR_LED_ENABLE)
979 val |= AIR_PHY_LED_ON_ENABLE;
980 else
981 val &= ~AIR_PHY_LED_ON_ENABLE;
982
983 if (pol == AIR_ACTIVE_HIGH)
984 val |= AIR_PHY_LED_ON_POLARITY;
985 else
986 val &= ~AIR_PHY_LED_ON_POLARITY;
987
988 err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
989 AIR_PHY_LED_ON_ENABLE |
990 AIR_PHY_LED_ON_POLARITY, val);
991
992 if (err < 0)
993 return err;
994
995 return 0;
996 }
997
air_leds_init(struct phy_device * phydev,int num,int dur,int mode)998 static int air_leds_init(struct phy_device *phydev, int num, int dur, int mode)
999 {
1000 struct en8811h_priv *priv = phydev->priv;
1001 int ret, i;
1002
1003 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK,
1004 dur);
1005 if (ret < 0)
1006 return ret;
1007
1008 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON,
1009 dur >> 1);
1010 if (ret < 0)
1011 return ret;
1012
1013 switch (mode) {
1014 case AIR_LED_MODE_DISABLE:
1015 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR,
1016 AIR_PHY_LED_BCR_EXT_CTRL |
1017 AIR_PHY_LED_BCR_MODE_MASK, 0);
1018 if (ret < 0)
1019 return ret;
1020 break;
1021 case AIR_LED_MODE_USER_DEFINE:
1022 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR,
1023 AIR_PHY_LED_BCR_EXT_CTRL |
1024 AIR_PHY_LED_BCR_CLK_EN,
1025 AIR_PHY_LED_BCR_EXT_CTRL |
1026 AIR_PHY_LED_BCR_CLK_EN);
1027 if (ret < 0)
1028 return ret;
1029 break;
1030 default:
1031 phydev_err(phydev, "LED mode %d is not supported\n", mode);
1032 return -EINVAL;
1033 }
1034
1035 for (i = 0; i < num; ++i) {
1036 ret = air_led_init(phydev, i, AIR_LED_ENABLE, AIR_ACTIVE_HIGH);
1037 if (ret < 0) {
1038 phydev_err(phydev, "LED%d init failed: %d\n", i, ret);
1039 return ret;
1040 }
1041 air_led_hw_control_set(phydev, i, priv->led[i].rules);
1042 }
1043
1044 return 0;
1045 }
1046
en8811h_led_hw_is_supported(struct phy_device * phydev,u8 index,unsigned long rules)1047 static int en8811h_led_hw_is_supported(struct phy_device *phydev, u8 index,
1048 unsigned long rules)
1049 {
1050 if (index >= EN8811H_LED_COUNT)
1051 return -EINVAL;
1052
1053 /* All combinations of the supported triggers are allowed */
1054 if (rules & ~en8811h_led_trig)
1055 return -EOPNOTSUPP;
1056
1057 return 0;
1058 };
1059
an8811hb_clk_recalc_rate(struct clk_hw * hw,unsigned long parent)1060 static unsigned long an8811hb_clk_recalc_rate(struct clk_hw *hw,
1061 unsigned long parent)
1062 {
1063 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
1064 struct phy_device *phydev = priv->phydev;
1065 u32 pbus_value;
1066 int ret;
1067
1068 ret = air_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value);
1069 if (ret < 0)
1070 return ret;
1071
1072 return (pbus_value & AN8811HB_HWTRAP2_CKO) ? 50000000 : 25000000;
1073 }
1074
an8811hb_clk_enable(struct clk_hw * hw)1075 static int an8811hb_clk_enable(struct clk_hw *hw)
1076 {
1077 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
1078 struct phy_device *phydev = priv->phydev;
1079
1080 return air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
1081 AN8811HB_CLK_DRV_CKO_MASK,
1082 AN8811HB_CLK_DRV_CKO_MASK);
1083 }
1084
an8811hb_clk_disable(struct clk_hw * hw)1085 static void an8811hb_clk_disable(struct clk_hw *hw)
1086 {
1087 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
1088 struct phy_device *phydev = priv->phydev;
1089
1090 air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
1091 AN8811HB_CLK_DRV_CKO_MASK, 0);
1092 }
1093
an8811hb_clk_is_enabled(struct clk_hw * hw)1094 static int an8811hb_clk_is_enabled(struct clk_hw *hw)
1095 {
1096 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
1097 struct phy_device *phydev = priv->phydev;
1098 u32 pbus_value;
1099 int ret;
1100
1101 ret = air_buckpbus_reg_read(phydev, AN8811HB_CLK_DRV, &pbus_value);
1102 if (ret < 0)
1103 return ret;
1104
1105 return (pbus_value & AN8811HB_CLK_DRV_CKO_MASK);
1106 }
1107
an8811hb_clk_save_context(struct clk_hw * hw)1108 static int an8811hb_clk_save_context(struct clk_hw *hw)
1109 {
1110 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
1111
1112 priv->cko_is_enabled = an8811hb_clk_is_enabled(hw);
1113
1114 return 0;
1115 }
1116
an8811hb_clk_restore_context(struct clk_hw * hw)1117 static void an8811hb_clk_restore_context(struct clk_hw *hw)
1118 {
1119 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
1120
1121 if (!priv->cko_is_enabled)
1122 an8811hb_clk_disable(hw);
1123 }
1124
1125 static const struct clk_ops an8811hb_clk_ops = {
1126 .recalc_rate = an8811hb_clk_recalc_rate,
1127 .enable = an8811hb_clk_enable,
1128 .disable = an8811hb_clk_disable,
1129 .is_enabled = an8811hb_clk_is_enabled,
1130 .save_context = an8811hb_clk_save_context,
1131 .restore_context = an8811hb_clk_restore_context,
1132 };
1133
an8811hb_clk_provider_setup(struct device * dev,struct clk_hw * hw)1134 static int an8811hb_clk_provider_setup(struct device *dev, struct clk_hw *hw)
1135 {
1136 struct clk_init_data init;
1137 int ret;
1138
1139 if (!IS_ENABLED(CONFIG_COMMON_CLK))
1140 return 0;
1141
1142 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-cko",
1143 fwnode_get_name(dev_fwnode(dev)));
1144 if (!init.name)
1145 return -ENOMEM;
1146
1147 init.ops = &an8811hb_clk_ops;
1148 init.flags = 0;
1149 init.num_parents = 0;
1150 hw->init = &init;
1151
1152 ret = devm_clk_hw_register(dev, hw);
1153 if (ret)
1154 return ret;
1155
1156 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
1157 }
1158
en8811h_clk_recalc_rate(struct clk_hw * hw,unsigned long parent)1159 static unsigned long en8811h_clk_recalc_rate(struct clk_hw *hw,
1160 unsigned long parent)
1161 {
1162 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
1163 struct phy_device *phydev = priv->phydev;
1164 u32 pbus_value;
1165 int ret;
1166
1167 ret = air_buckpbus_reg_read(phydev, EN8811H_HWTRAP1, &pbus_value);
1168 if (ret < 0)
1169 return ret;
1170
1171 return (pbus_value & EN8811H_HWTRAP1_CKO) ? 50000000 : 25000000;
1172 }
1173
en8811h_clk_enable(struct clk_hw * hw)1174 static int en8811h_clk_enable(struct clk_hw *hw)
1175 {
1176 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
1177 struct phy_device *phydev = priv->phydev;
1178
1179 return air_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
1180 EN8811H_CLK_CGM_CKO,
1181 EN8811H_CLK_CGM_CKO);
1182 }
1183
en8811h_clk_disable(struct clk_hw * hw)1184 static void en8811h_clk_disable(struct clk_hw *hw)
1185 {
1186 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
1187 struct phy_device *phydev = priv->phydev;
1188
1189 air_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
1190 EN8811H_CLK_CGM_CKO, 0);
1191 }
1192
en8811h_clk_is_enabled(struct clk_hw * hw)1193 static int en8811h_clk_is_enabled(struct clk_hw *hw)
1194 {
1195 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
1196 struct phy_device *phydev = priv->phydev;
1197 u32 pbus_value;
1198 int ret;
1199
1200 ret = air_buckpbus_reg_read(phydev, EN8811H_CLK_CGM, &pbus_value);
1201 if (ret < 0)
1202 return ret;
1203
1204 return (pbus_value & EN8811H_CLK_CGM_CKO);
1205 }
1206
en8811h_clk_save_context(struct clk_hw * hw)1207 static int en8811h_clk_save_context(struct clk_hw *hw)
1208 {
1209 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
1210
1211 priv->cko_is_enabled = en8811h_clk_is_enabled(hw);
1212
1213 return 0;
1214 }
1215
en8811h_clk_restore_context(struct clk_hw * hw)1216 static void en8811h_clk_restore_context(struct clk_hw *hw)
1217 {
1218 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
1219
1220 if (!priv->cko_is_enabled)
1221 en8811h_clk_disable(hw);
1222 }
1223
1224 static const struct clk_ops en8811h_clk_ops = {
1225 .recalc_rate = en8811h_clk_recalc_rate,
1226 .enable = en8811h_clk_enable,
1227 .disable = en8811h_clk_disable,
1228 .is_enabled = en8811h_clk_is_enabled,
1229 .save_context = en8811h_clk_save_context,
1230 .restore_context = en8811h_clk_restore_context,
1231 };
1232
en8811h_clk_provider_setup(struct device * dev,struct clk_hw * hw)1233 static int en8811h_clk_provider_setup(struct device *dev, struct clk_hw *hw)
1234 {
1235 struct clk_init_data init;
1236 int ret;
1237
1238 if (!IS_ENABLED(CONFIG_COMMON_CLK))
1239 return 0;
1240
1241 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-cko",
1242 fwnode_get_name(dev_fwnode(dev)));
1243 if (!init.name)
1244 return -ENOMEM;
1245
1246 init.ops = &en8811h_clk_ops;
1247 init.flags = 0;
1248 init.num_parents = 0;
1249 hw->init = &init;
1250
1251 ret = devm_clk_hw_register(dev, hw);
1252 if (ret)
1253 return ret;
1254
1255 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
1256 }
1257
en8811h_leds_setup(struct phy_device * phydev)1258 static int en8811h_leds_setup(struct phy_device *phydev)
1259 {
1260 struct en8811h_priv *priv = phydev->priv;
1261 int ret;
1262
1263 priv->led[0].rules = AIR_DEFAULT_TRIGGER_LED0;
1264 priv->led[1].rules = AIR_DEFAULT_TRIGGER_LED1;
1265 priv->led[2].rules = AIR_DEFAULT_TRIGGER_LED2;
1266
1267 ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,
1268 AIR_LED_MODE_DISABLE);
1269 if (ret < 0)
1270 phydev_err(phydev, "Failed to disable leds: %d\n", ret);
1271
1272 return ret;
1273 }
1274
an8811hb_probe(struct phy_device * phydev)1275 static int an8811hb_probe(struct phy_device *phydev)
1276 {
1277 struct mdio_device *mdiodev;
1278 struct en8811h_priv *priv;
1279 int ret;
1280
1281 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv),
1282 GFP_KERNEL);
1283 if (!priv)
1284 return -ENOMEM;
1285 phydev->priv = priv;
1286
1287 /*
1288 * The AN8811HB PHY address is restricted to 8-15 (decimal),
1289 * depending on the board hardware strapping.
1290 * This means the PBUS address is only in the range 16-21 (decimal),
1291 * so we do not need to handle the case
1292 * where the PBUS address exceeds 31 (decimal).
1293 */
1294 mdiodev = mdio_device_create(phydev->mdio.bus,
1295 phydev->mdio.addr + EN8811H_PBUS_ADDR_OFFS);
1296 if (IS_ERR(mdiodev))
1297 return PTR_ERR(mdiodev);
1298
1299 ret = mdio_device_register(mdiodev);
1300 if (ret)
1301 goto err_dev_free;
1302
1303 priv->pbusdev = mdiodev;
1304
1305 ret = an8811hb_load_firmware(phydev);
1306 if (ret < 0) {
1307 phydev_err(phydev, "Load firmware failed: %d\n", ret);
1308 goto err_dev_create;
1309 }
1310
1311 en8811h_print_fw_version(phydev);
1312
1313 /* mcu has just restarted after firmware load */
1314 priv->mcu_needs_restart = false;
1315
1316 /* MDIO_DEVS1/2 empty, so set mmds_present bits here */
1317 phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
1318
1319 ret = en8811h_leds_setup(phydev);
1320 if (ret < 0)
1321 goto err_dev_create;
1322
1323 priv->phydev = phydev;
1324 /* Co-Clock Output */
1325 ret = an8811hb_clk_provider_setup(&phydev->mdio.dev, &priv->hw);
1326 if (ret)
1327 goto err_dev_create;
1328
1329 /* Configure led gpio pins as output */
1330 ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT,
1331 AN8811HB_GPIO_OUTPUT_345,
1332 AN8811HB_GPIO_OUTPUT_345);
1333 if (ret < 0)
1334 goto err_dev_create;
1335
1336 return 0;
1337
1338 err_dev_create:
1339 mdio_device_remove(mdiodev);
1340
1341 err_dev_free:
1342 mdio_device_free(mdiodev);
1343 return ret;
1344 }
1345
en8811h_probe(struct phy_device * phydev)1346 static int en8811h_probe(struct phy_device *phydev)
1347 {
1348 struct en8811h_priv *priv;
1349 int ret;
1350
1351 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv),
1352 GFP_KERNEL);
1353 if (!priv)
1354 return -ENOMEM;
1355 phydev->priv = priv;
1356
1357 ret = en8811h_load_firmware(phydev);
1358 if (ret < 0)
1359 return ret;
1360
1361 /* mcu has just restarted after firmware load */
1362 priv->mcu_needs_restart = false;
1363
1364 /* MDIO_DEVS1/2 empty, so set mmds_present bits here */
1365 phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
1366
1367 ret = en8811h_leds_setup(phydev);
1368 if (ret < 0)
1369 return ret;
1370
1371 priv->phydev = phydev;
1372 /* Co-Clock Output */
1373 ret = en8811h_clk_provider_setup(&phydev->mdio.dev, &priv->hw);
1374 if (ret)
1375 return ret;
1376
1377 /* Configure led gpio pins as output */
1378 ret = air_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT,
1379 EN8811H_GPIO_OUTPUT_345,
1380 EN8811H_GPIO_OUTPUT_345);
1381 if (ret < 0)
1382 return ret;
1383
1384 return 0;
1385 }
1386
an8811hb_config_serdes_polarity(struct phy_device * phydev)1387 static int an8811hb_config_serdes_polarity(struct phy_device *phydev)
1388 {
1389 struct device *dev = &phydev->mdio.dev;
1390 u32 pbus_value = 0;
1391 unsigned int pol;
1392 int ret;
1393
1394 ret = phy_get_manual_rx_polarity(dev_fwnode(dev),
1395 phy_modes(phydev->interface), &pol);
1396 if (ret)
1397 return ret;
1398 if (pol == PHY_POL_NORMAL)
1399 pbus_value |= AN8811HB_RX_POLARITY_NORMAL;
1400 ret = air_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY,
1401 AN8811HB_RX_POLARITY_NORMAL,
1402 pbus_value);
1403 if (ret < 0)
1404 return ret;
1405
1406 ret = phy_get_manual_tx_polarity(dev_fwnode(dev),
1407 phy_modes(phydev->interface), &pol);
1408 if (ret)
1409 return ret;
1410 pbus_value = 0;
1411 if (pol == PHY_POL_NORMAL)
1412 pbus_value |= AN8811HB_TX_POLARITY_NORMAL;
1413 return air_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY,
1414 AN8811HB_TX_POLARITY_NORMAL,
1415 pbus_value);
1416 }
1417
en8811h_config_serdes_polarity(struct phy_device * phydev)1418 static int en8811h_config_serdes_polarity(struct phy_device *phydev)
1419 {
1420 struct device *dev = &phydev->mdio.dev;
1421 unsigned int pol, default_pol;
1422 u32 pbus_value = 0;
1423 int ret;
1424
1425 default_pol = PHY_POL_NORMAL;
1426 if (device_property_read_bool(dev, "airoha,pnswap-rx"))
1427 default_pol = PHY_POL_INVERT;
1428
1429 ret = phy_get_rx_polarity(dev_fwnode(dev), phy_modes(phydev->interface),
1430 BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT),
1431 default_pol, &pol);
1432 if (ret)
1433 return ret;
1434 if (pol == PHY_POL_INVERT)
1435 pbus_value |= EN8811H_POLARITY_RX_REVERSE;
1436
1437 default_pol = PHY_POL_NORMAL;
1438 if (device_property_read_bool(dev, "airoha,pnswap-tx"))
1439 default_pol = PHY_POL_INVERT;
1440
1441 ret = phy_get_tx_polarity(dev_fwnode(dev), phy_modes(phydev->interface),
1442 BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT),
1443 default_pol, &pol);
1444 if (ret)
1445 return ret;
1446 if (pol == PHY_POL_NORMAL)
1447 pbus_value |= EN8811H_POLARITY_TX_NORMAL;
1448
1449 return air_buckpbus_reg_modify(phydev, EN8811H_POLARITY,
1450 EN8811H_POLARITY_RX_REVERSE |
1451 EN8811H_POLARITY_TX_NORMAL, pbus_value);
1452 }
1453
an8811hb_config_init(struct phy_device * phydev)1454 static int an8811hb_config_init(struct phy_device *phydev)
1455 {
1456 struct en8811h_priv *priv = phydev->priv;
1457 int ret;
1458
1459 /* If restart happened in .probe(), no need to restart now */
1460 if (priv->mcu_needs_restart) {
1461 ret = en8811h_restart_mcu(phydev);
1462 if (ret < 0)
1463 return ret;
1464 } else {
1465 /* Next calls to .config_init() mcu needs to restart */
1466 priv->mcu_needs_restart = true;
1467 }
1468
1469 ret = an8811hb_config_serdes_polarity(phydev);
1470 if (ret < 0)
1471 return ret;
1472
1473 ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,
1474 AIR_LED_MODE_USER_DEFINE);
1475 if (ret < 0)
1476 phydev_err(phydev, "Failed to initialize leds: %d\n", ret);
1477
1478 return ret;
1479 }
1480
en8811h_config_init(struct phy_device * phydev)1481 static int en8811h_config_init(struct phy_device *phydev)
1482 {
1483 struct en8811h_priv *priv = phydev->priv;
1484 int ret;
1485
1486 /* If restart happened in .probe(), no need to restart now */
1487 if (priv->mcu_needs_restart) {
1488 ret = en8811h_restart_mcu(phydev);
1489 if (ret < 0)
1490 return ret;
1491 } else {
1492 /* Next calls to .config_init() mcu needs to restart */
1493 priv->mcu_needs_restart = true;
1494 }
1495
1496 /* Select mode 1, the only mode supported.
1497 * Configures the SerDes for 2500Base-X with rate adaptation
1498 */
1499 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_1,
1500 AIR_PHY_MCU_CMD_1_MODE1);
1501 if (ret < 0)
1502 return ret;
1503 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_2,
1504 AIR_PHY_MCU_CMD_2_MODE1);
1505 if (ret < 0)
1506 return ret;
1507 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3,
1508 AIR_PHY_MCU_CMD_3_MODE1);
1509 if (ret < 0)
1510 return ret;
1511 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4,
1512 AIR_PHY_MCU_CMD_4_MODE1);
1513 if (ret < 0)
1514 return ret;
1515
1516 ret = en8811h_config_serdes_polarity(phydev);
1517 if (ret < 0)
1518 return ret;
1519
1520 ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,
1521 AIR_LED_MODE_USER_DEFINE);
1522 if (ret < 0) {
1523 phydev_err(phydev, "Failed to initialize leds: %d\n", ret);
1524 return ret;
1525 }
1526
1527 return 0;
1528 }
1529
en8811h_get_features(struct phy_device * phydev)1530 static int en8811h_get_features(struct phy_device *phydev)
1531 {
1532 linkmode_set_bit_array(phy_basic_ports_array,
1533 ARRAY_SIZE(phy_basic_ports_array),
1534 phydev->supported);
1535
1536 return genphy_c45_pma_read_abilities(phydev);
1537 }
1538
en8811h_get_rate_matching(struct phy_device * phydev,phy_interface_t iface)1539 static int en8811h_get_rate_matching(struct phy_device *phydev,
1540 phy_interface_t iface)
1541 {
1542 return RATE_MATCH_PAUSE;
1543 }
1544
en8811h_config_aneg(struct phy_device * phydev)1545 static int en8811h_config_aneg(struct phy_device *phydev)
1546 {
1547 bool changed = false;
1548 int ret;
1549 u32 adv;
1550
1551 if (phydev->autoneg == AUTONEG_DISABLE) {
1552 phydev_warn(phydev, "Disabling autoneg is not supported\n");
1553 return -EINVAL;
1554 }
1555
1556 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
1557
1558 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
1559 MDIO_AN_10GBT_CTRL_ADV2_5G, adv);
1560 if (ret < 0)
1561 return ret;
1562 if (ret > 0)
1563 changed = true;
1564
1565 return __genphy_config_aneg(phydev, changed);
1566 }
1567
en8811h_read_status(struct phy_device * phydev)1568 static int en8811h_read_status(struct phy_device *phydev)
1569 {
1570 struct en8811h_priv *priv = phydev->priv;
1571 u32 pbus_value;
1572 int ret, val;
1573
1574 ret = genphy_update_link(phydev);
1575 if (ret)
1576 return ret;
1577
1578 phydev->master_slave_get = MASTER_SLAVE_CFG_UNSUPPORTED;
1579 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
1580 phydev->speed = SPEED_UNKNOWN;
1581 phydev->duplex = DUPLEX_UNKNOWN;
1582 phydev->pause = 0;
1583 phydev->asym_pause = 0;
1584 phydev->rate_matching = RATE_MATCH_PAUSE;
1585
1586 ret = genphy_read_master_slave(phydev);
1587 if (ret < 0)
1588 return ret;
1589
1590 ret = genphy_read_lpa(phydev);
1591 if (ret < 0)
1592 return ret;
1593
1594 if (phy_id_compare_model(phydev->phy_id, AN8811HB_PHY_ID)) {
1595 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
1596 if (val < 0)
1597 return val;
1598 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
1599 phydev->lp_advertising,
1600 val & MDIO_AN_10GBT_STAT_LP2_5G);
1601 } else {
1602 /* Get link partner 2.5GBASE-T ability from vendor register */
1603 ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA,
1604 &pbus_value);
1605 if (ret < 0)
1606 return ret;
1607 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
1608 phydev->lp_advertising,
1609 pbus_value & EN8811H_2P5G_LPA_2P5G);
1610 }
1611
1612 if (phydev->autoneg_complete)
1613 phy_resolve_aneg_pause(phydev);
1614
1615 if (!phydev->link)
1616 return 0;
1617
1618 /* Get real speed from vendor register */
1619 val = phy_read(phydev, AIR_AUX_CTRL_STATUS);
1620 if (val < 0)
1621 return val;
1622 switch (val & AIR_AUX_CTRL_STATUS_SPEED_MASK) {
1623 case AIR_AUX_CTRL_STATUS_SPEED_2500:
1624 phydev->speed = SPEED_2500;
1625 break;
1626 case AIR_AUX_CTRL_STATUS_SPEED_1000:
1627 phydev->speed = SPEED_1000;
1628 break;
1629 case AIR_AUX_CTRL_STATUS_SPEED_100:
1630 phydev->speed = SPEED_100;
1631 break;
1632 case AIR_AUX_CTRL_STATUS_SPEED_10:
1633 phydev->speed = SPEED_10;
1634 break;
1635 }
1636
1637 /* Firmware before version 24011202 has no vendor register 2P5G_LPA.
1638 * Assume link partner advertised it if connected at 2500Mbps.
1639 */
1640 if (priv->firmware_version < 0x24011202) {
1641 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
1642 phydev->lp_advertising,
1643 phydev->speed == SPEED_2500);
1644 }
1645
1646 /* Only supports full duplex */
1647 phydev->duplex = DUPLEX_FULL;
1648
1649 return 0;
1650 }
1651
en8811h_clear_intr(struct phy_device * phydev)1652 static int en8811h_clear_intr(struct phy_device *phydev)
1653 {
1654 int ret;
1655
1656 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3,
1657 AIR_PHY_MCU_CMD_3_DOCMD);
1658 if (ret < 0)
1659 return ret;
1660
1661 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4,
1662 AIR_PHY_MCU_CMD_4_INTCLR);
1663 if (ret < 0)
1664 return ret;
1665
1666 return 0;
1667 }
1668
en8811h_handle_interrupt(struct phy_device * phydev)1669 static irqreturn_t en8811h_handle_interrupt(struct phy_device *phydev)
1670 {
1671 int ret;
1672
1673 ret = en8811h_clear_intr(phydev);
1674 if (ret < 0) {
1675 phy_error(phydev);
1676 return IRQ_NONE;
1677 }
1678
1679 phy_trigger_machine(phydev);
1680
1681 return IRQ_HANDLED;
1682 }
1683
en8811h_resume(struct phy_device * phydev)1684 static int en8811h_resume(struct phy_device *phydev)
1685 {
1686 clk_restore_context();
1687
1688 return genphy_resume(phydev);
1689 }
1690
en8811h_suspend(struct phy_device * phydev)1691 static int en8811h_suspend(struct phy_device *phydev)
1692 {
1693 clk_save_context();
1694
1695 return genphy_suspend(phydev);
1696 }
1697
an8811hb_remove(struct phy_device * phydev)1698 static void an8811hb_remove(struct phy_device *phydev)
1699 {
1700 struct en8811h_priv *priv = phydev->priv;
1701
1702 if (priv->pbusdev) {
1703 mdio_device_remove(priv->pbusdev);
1704 mdio_device_free(priv->pbusdev);
1705 }
1706 }
1707
1708 static struct phy_driver en8811h_driver[] = {
1709 {
1710 PHY_ID_MATCH_MODEL(EN8811H_PHY_ID),
1711 .name = "Airoha EN8811H",
1712 .probe = en8811h_probe,
1713 .get_features = en8811h_get_features,
1714 .config_init = en8811h_config_init,
1715 .get_rate_matching = en8811h_get_rate_matching,
1716 .config_aneg = en8811h_config_aneg,
1717 .read_status = en8811h_read_status,
1718 .resume = en8811h_resume,
1719 .suspend = en8811h_suspend,
1720 .config_intr = en8811h_clear_intr,
1721 .handle_interrupt = en8811h_handle_interrupt,
1722 .led_hw_is_supported = en8811h_led_hw_is_supported,
1723 .read_page = air_phy_read_page,
1724 .write_page = air_phy_write_page,
1725 .led_blink_set = air_led_blink_set,
1726 .led_brightness_set = air_led_brightness_set,
1727 .led_hw_control_set = air_led_hw_control_set,
1728 .led_hw_control_get = air_led_hw_control_get,
1729 },
1730 {
1731 PHY_ID_MATCH_MODEL(AN8811HB_PHY_ID),
1732 .name = "Airoha AN8811HB",
1733 .probe = an8811hb_probe,
1734 .remove = an8811hb_remove,
1735 .get_features = en8811h_get_features,
1736 .config_init = an8811hb_config_init,
1737 .get_rate_matching = en8811h_get_rate_matching,
1738 .config_aneg = en8811h_config_aneg,
1739 .read_status = en8811h_read_status,
1740 .resume = en8811h_resume,
1741 .suspend = en8811h_suspend,
1742 .config_intr = en8811h_clear_intr,
1743 .handle_interrupt = en8811h_handle_interrupt,
1744 .led_hw_is_supported = en8811h_led_hw_is_supported,
1745 .read_page = air_phy_read_page,
1746 .write_page = air_phy_write_page,
1747 .led_blink_set = air_led_blink_set,
1748 .led_brightness_set = air_led_brightness_set,
1749 .led_hw_control_set = air_led_hw_control_set,
1750 .led_hw_control_get = air_led_hw_control_get,
1751 } };
1752
1753 module_phy_driver(en8811h_driver);
1754
1755 static const struct mdio_device_id __maybe_unused en8811h_tbl[] = {
1756 { PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) },
1757 { PHY_ID_MATCH_MODEL(AN8811HB_PHY_ID) },
1758 { }
1759 };
1760
1761 MODULE_DEVICE_TABLE(mdio, en8811h_tbl);
1762 MODULE_FIRMWARE(EN8811H_MD32_DM);
1763 MODULE_FIRMWARE(EN8811H_MD32_DSP);
1764 MODULE_FIRMWARE(AN8811HB_MD32_DM);
1765 MODULE_FIRMWARE(AN8811HB_MD32_DSP);
1766
1767 MODULE_DESCRIPTION("Airoha EN8811H and AN8811HB PHY drivers");
1768 MODULE_AUTHOR("Airoha");
1769 MODULE_AUTHOR("Eric Woudstra <ericwouds@gmail.com>");
1770 MODULE_LICENSE("GPL");
1771