1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * ADXL380 3-Axis Digital Accelerometer core driver
4 *
5 * Copyright 2024 Analog Devices Inc.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/module.h>
12 #include <linux/property.h>
13 #include <linux/regmap.h>
14 #include <linux/units.h>
15
16 #include <linux/unaligned.h>
17
18 #include <linux/iio/buffer.h>
19 #include <linux/iio/events.h>
20 #include <linux/iio/iio.h>
21 #include <linux/iio/kfifo_buf.h>
22 #include <linux/iio/sysfs.h>
23
24 #include <linux/regulator/consumer.h>
25
26 #include "adxl380.h"
27
28 #define ADXL380_ID_VAL 380
29 #define ADXL318_ID_VAL 380
30 #define ADXL382_ID_VAL 382
31 #define ADXL319_ID_VAL 382
32
33 #define ADXL380_DEVID_AD_REG 0x00
34 #define ADLX380_PART_ID_REG 0x02
35
36 #define ADXL380_X_DATA_H_REG 0x15
37 #define ADXL380_Y_DATA_H_REG 0x17
38 #define ADXL380_Z_DATA_H_REG 0x19
39 #define ADXL380_T_DATA_H_REG 0x1B
40
41 #define ADXL380_MISC_0_REG 0x20
42 #define ADXL380_XL382_MSK BIT(7)
43
44 #define ADXL380_MISC_1_REG 0x21
45
46 #define ADXL380_X_DSM_OFFSET_REG 0x4D
47
48 #define ADXL380_ACT_INACT_CTL_REG 0x37
49 #define ADXL380_INACT_EN_MSK BIT(2)
50 #define ADXL380_ACT_EN_MSK BIT(0)
51
52 #define ADXL380_SNSR_AXIS_EN_REG 0x38
53 #define ADXL380_ACT_INACT_AXIS_EN_MSK GENMASK(2, 0)
54
55 #define ADXL380_THRESH_ACT_H_REG 0x39
56 #define ADXL380_TIME_ACT_H_REG 0x3B
57 #define ADXL380_THRESH_INACT_H_REG 0x3E
58 #define ADXL380_TIME_INACT_H_REG 0x40
59 #define ADXL380_THRESH_MAX GENMASK(12, 0)
60 #define ADXL380_TIME_MAX GENMASK(24, 0)
61
62 #define ADXL380_FIFO_CONFIG_0_REG 0x30
63 #define ADXL380_FIFO_SAMPLES_8_MSK BIT(0)
64 #define ADXL380_FIFO_MODE_MSK GENMASK(5, 4)
65
66 #define ADXL380_FIFO_DISABLED 0
67 #define ADXL380_FIFO_NORMAL 1
68 #define ADXL380_FIFO_STREAMED 2
69 #define ADXL380_FIFO_TRIGGERED 3
70
71 #define ADXL380_FIFO_CONFIG_1_REG 0x31
72 #define ADXL380_FIFO_STATUS_0_REG 0x1E
73
74 #define ADXL380_TAP_THRESH_REG 0x43
75 #define ADXL380_TAP_DUR_REG 0x44
76 #define ADXL380_TAP_LATENT_REG 0x45
77 #define ADXL380_TAP_WINDOW_REG 0x46
78 #define ADXL380_TAP_TIME_MAX GENMASK(7, 0)
79
80 #define ADXL380_TAP_CFG_REG 0x47
81 #define ADXL380_TAP_AXIS_MSK GENMASK(1, 0)
82
83 #define ADXL380_TRIG_CFG_REG 0x49
84 #define ADXL380_TRIG_CFG_DEC_2X_MSK BIT(7)
85 #define ADXL380_TRIG_CFG_SINC_RATE_MSK BIT(6)
86
87 #define ADXL380_FILTER_REG 0x50
88 #define ADXL380_FILTER_EQ_FILT_MSK BIT(6)
89 #define ADXL380_FILTER_LPF_MODE_MSK GENMASK(5, 4)
90 #define ADXL380_FILTER_HPF_PATH_MSK BIT(3)
91 #define ADXL380_FILTER_HPF_CORNER_MSK GENMASK(2, 0)
92
93 #define ADXL380_OP_MODE_REG 0x26
94 #define ADXL380_OP_MODE_RANGE_MSK GENMASK(7, 6)
95 #define ADXL380_OP_MODE_MSK GENMASK(3, 0)
96 #define ADXL380_OP_MODE_STANDBY 0
97 #define ADXL380_OP_MODE_HEART_SOUND 1
98 #define ADXL380_OP_MODE_ULP 2
99 #define ADXL380_OP_MODE_VLP 3
100 #define ADXL380_OP_MODE_LP 4
101 #define ADXL380_OP_MODE_LP_ULP 6
102 #define ADXL380_OP_MODE_LP_VLP 7
103 #define ADXL380_OP_MODE_RBW 8
104 #define ADXL380_OP_MODE_RBW_ULP 10
105 #define ADXL380_OP_MODE_RBW_VLP 11
106 #define ADXL380_OP_MODE_HP 12
107 #define ADXL380_OP_MODE_HP_ULP 14
108 #define ADXL380_OP_MODE_HP_VLP 15
109
110 #define ADXL380_OP_MODE_4G_RANGE 0
111 #define ADXL382_OP_MODE_15G_RANGE 0
112 #define ADXL380_OP_MODE_8G_RANGE 1
113 #define ADXL382_OP_MODE_30G_RANGE 1
114 #define ADXL380_OP_MODE_16G_RANGE 2
115 #define ADXL382_OP_MODE_60G_RANGE 2
116
117 #define ADXL380_DIG_EN_REG 0x27
118 #define ADXL380_CHAN_EN_MSK(chan) BIT(4 + (chan))
119 #define ADXL380_FIFO_EN_MSK BIT(3)
120
121 #define ADXL380_INT0_MAP0_REG 0x2B
122 #define ADXL380_INT1_MAP0_REG 0x2D
123 #define ADXL380_INT_MAP0_INACT_INT0_MSK BIT(6)
124 #define ADXL380_INT_MAP0_ACT_INT0_MSK BIT(5)
125 #define ADXL380_INT_MAP0_FIFO_WM_INT0_MSK BIT(3)
126
127 #define ADXL380_INT0_MAP1_REG 0x2C
128 #define ADXL380_INT1_MAP1_REG 0x2E
129 #define ADXL380_INT_MAP1_DOUBLE_TAP_INT0_MSK BIT(1)
130 #define ADXL380_INT_MAP1_SINGLE_TAP_INT0_MSK BIT(0)
131
132 #define ADXL380_INT0_REG 0x5D
133 #define ADXL380_INT0_POL_MSK BIT(7)
134
135 #define ADXL380_RESET_REG 0x2A
136 #define ADXL380_FIFO_DATA 0x1D
137
138 #define ADXL380_DEVID_AD_VAL 0xAD
139 #define ADXL380_RESET_CODE 0x52
140
141 #define ADXL380_STATUS_0_REG 0x11
142 #define ADXL380_STATUS_0_FIFO_FULL_MSK BIT(1)
143 #define ADXL380_STATUS_0_FIFO_WM_MSK BIT(3)
144
145 #define ADXL380_STATUS_1_INACT_MSK BIT(6)
146 #define ADXL380_STATUS_1_ACT_MSK BIT(5)
147 #define ADXL380_STATUS_1_DOUBLE_TAP_MSK BIT(1)
148 #define ADXL380_STATUS_1_SINGLE_TAP_MSK BIT(0)
149
150 #define ADXL380_FIFO_SAMPLES 315UL
151
152 enum adxl380_channels {
153 ADXL380_ACCEL_X,
154 ADXL380_ACCEL_Y,
155 ADXL380_ACCEL_Z,
156 ADXL380_TEMP,
157 ADXL380_CH_NUM
158 };
159
160 enum adxl380_axis {
161 ADXL380_X_AXIS,
162 ADXL380_Y_AXIS,
163 ADXL380_Z_AXIS,
164 };
165
166 enum adxl380_activity_type {
167 ADXL380_ACTIVITY,
168 ADXL380_INACTIVITY,
169 };
170
171 enum adxl380_tap_type {
172 ADXL380_SINGLE_TAP,
173 ADXL380_DOUBLE_TAP,
174 };
175
176 enum adxl380_tap_time_type {
177 ADXL380_TAP_TIME_LATENT,
178 ADXL380_TAP_TIME_WINDOW,
179 };
180
181 static const int adxl380_range_scale_factor_tbl[] = { 1, 2, 4 };
182
183 static const unsigned int adxl380_th_reg_high_addr[2] = {
184 [ADXL380_ACTIVITY] = ADXL380_THRESH_ACT_H_REG,
185 [ADXL380_INACTIVITY] = ADXL380_THRESH_INACT_H_REG,
186 };
187
188 static const unsigned int adxl380_time_reg_high_addr[2] = {
189 [ADXL380_ACTIVITY] = ADXL380_TIME_ACT_H_REG,
190 [ADXL380_INACTIVITY] = ADXL380_TIME_INACT_H_REG,
191 };
192
193 static const unsigned int adxl380_tap_time_reg[2] = {
194 [ADXL380_TAP_TIME_LATENT] = ADXL380_TAP_LATENT_REG,
195 [ADXL380_TAP_TIME_WINDOW] = ADXL380_TAP_WINDOW_REG,
196 };
197
198 struct adxl380_state {
199 struct regmap *regmap;
200 struct device *dev;
201 const struct adxl380_chip_info *chip_info;
202 /*
203 * Synchronize access to members of driver state, and ensure atomicity
204 * of consecutive regmap operations.
205 */
206 struct mutex lock;
207 enum adxl380_axis tap_axis_en;
208 u8 range;
209 u8 odr;
210 u8 fifo_set_size;
211 u8 transf_buf[3];
212 u16 watermark;
213 u32 act_time_ms;
214 u32 act_threshold;
215 u32 inact_time_ms;
216 u32 inact_threshold;
217 u32 tap_latent_us;
218 u32 tap_window_us;
219 u32 tap_duration_us;
220 u32 tap_threshold;
221 int irq;
222 int int_map[2];
223 int lpf_tbl[4];
224 int hpf_tbl[7][2];
225
226 __be16 fifo_buf[ADXL380_FIFO_SAMPLES] __aligned(IIO_DMA_MINALIGN);
227 };
228
adxl380_readable_noinc_reg(struct device * dev,unsigned int reg)229 bool adxl380_readable_noinc_reg(struct device *dev, unsigned int reg)
230 {
231 return reg == ADXL380_FIFO_DATA;
232 }
233 EXPORT_SYMBOL_NS_GPL(adxl380_readable_noinc_reg, "IIO_ADXL380");
234
adxl380_act_inact_enabled(struct adxl380_state * st,bool * enabled)235 static int adxl380_act_inact_enabled(struct adxl380_state *st, bool *enabled)
236 {
237 unsigned int act_inact_ctl;
238 int ret;
239
240 if (!st->chip_info->has_low_power) {
241 *enabled = false;
242 return 0;
243 }
244
245 ret = regmap_read(st->regmap, ADXL380_ACT_INACT_CTL_REG, &act_inact_ctl);
246 if (ret)
247 return ret;
248
249 *enabled = FIELD_GET(ADXL380_ACT_EN_MSK, act_inact_ctl) ||
250 FIELD_GET(ADXL380_INACT_EN_MSK, act_inact_ctl);
251
252 return 0;
253 }
254
adxl380_set_measure_en(struct adxl380_state * st,bool en)255 static int adxl380_set_measure_en(struct adxl380_state *st, bool en)
256 {
257 int ret;
258 u8 op_mode = ADXL380_OP_MODE_STANDBY;
259
260 if (en) {
261 bool act_inact_enabled;
262
263 ret = adxl380_act_inact_enabled(st, &act_inact_enabled);
264 if (ret)
265 return ret;
266
267 /*
268 * Activity/Inactivity detection available only in VLP/ULP
269 * mode and for devices that support low power modes.
270 */
271 if (act_inact_enabled)
272 st->odr = ADXL380_ODR_VLP;
273
274 if (st->odr == ADXL380_ODR_VLP)
275 op_mode = ADXL380_OP_MODE_VLP;
276 else
277 op_mode = ADXL380_OP_MODE_HP;
278 }
279
280 return regmap_update_bits(st->regmap, ADXL380_OP_MODE_REG,
281 ADXL380_OP_MODE_MSK,
282 FIELD_PREP(ADXL380_OP_MODE_MSK, op_mode));
283 }
284
adxl380_scale_act_inact_thresholds(struct adxl380_state * st,u8 old_range,u8 new_range)285 static void adxl380_scale_act_inact_thresholds(struct adxl380_state *st,
286 u8 old_range,
287 u8 new_range)
288 {
289 st->act_threshold = mult_frac(st->act_threshold,
290 adxl380_range_scale_factor_tbl[old_range],
291 adxl380_range_scale_factor_tbl[new_range]);
292 st->inact_threshold = mult_frac(st->inact_threshold,
293 adxl380_range_scale_factor_tbl[old_range],
294 adxl380_range_scale_factor_tbl[new_range]);
295 }
296
adxl380_write_act_inact_threshold(struct adxl380_state * st,enum adxl380_activity_type act,unsigned int th)297 static int adxl380_write_act_inact_threshold(struct adxl380_state *st,
298 enum adxl380_activity_type act,
299 unsigned int th)
300 {
301 int ret;
302 u8 reg = adxl380_th_reg_high_addr[act];
303
304 if (th > ADXL380_THRESH_MAX)
305 return -EINVAL;
306
307 ret = regmap_write(st->regmap, reg + 1, th & GENMASK(7, 0));
308 if (ret)
309 return ret;
310
311 ret = regmap_update_bits(st->regmap, reg, GENMASK(2, 0), th >> 8);
312 if (ret)
313 return ret;
314
315 if (act == ADXL380_ACTIVITY)
316 st->act_threshold = th;
317 else
318 st->inact_threshold = th;
319
320 return 0;
321 }
322
adxl380_set_act_inact_threshold(struct iio_dev * indio_dev,enum adxl380_activity_type act,u16 th)323 static int adxl380_set_act_inact_threshold(struct iio_dev *indio_dev,
324 enum adxl380_activity_type act,
325 u16 th)
326 {
327 struct adxl380_state *st = iio_priv(indio_dev);
328 int ret;
329
330 guard(mutex)(&st->lock);
331
332 ret = adxl380_set_measure_en(st, false);
333 if (ret)
334 return ret;
335
336 ret = adxl380_write_act_inact_threshold(st, act, th);
337 if (ret)
338 return ret;
339
340 return adxl380_set_measure_en(st, true);
341 }
342
adxl380_set_tap_threshold_value(struct iio_dev * indio_dev,u8 th)343 static int adxl380_set_tap_threshold_value(struct iio_dev *indio_dev, u8 th)
344 {
345 int ret;
346 struct adxl380_state *st = iio_priv(indio_dev);
347
348 guard(mutex)(&st->lock);
349
350 ret = adxl380_set_measure_en(st, false);
351 if (ret)
352 return ret;
353
354 ret = regmap_write(st->regmap, ADXL380_TAP_THRESH_REG, th);
355 if (ret)
356 return ret;
357
358 st->tap_threshold = th;
359
360 return adxl380_set_measure_en(st, true);
361 }
362
_adxl380_write_tap_time_us(struct adxl380_state * st,enum adxl380_tap_time_type tap_time_type,u32 us)363 static int _adxl380_write_tap_time_us(struct adxl380_state *st,
364 enum adxl380_tap_time_type tap_time_type,
365 u32 us)
366 {
367 u8 reg = adxl380_tap_time_reg[tap_time_type];
368 unsigned int reg_val;
369 int ret;
370
371 /* scale factor for tap window is 1250us / LSB */
372 reg_val = DIV_ROUND_CLOSEST(us, 1250);
373 if (reg_val > ADXL380_TAP_TIME_MAX)
374 reg_val = ADXL380_TAP_TIME_MAX;
375
376 ret = regmap_write(st->regmap, reg, reg_val);
377 if (ret)
378 return ret;
379
380 if (tap_time_type == ADXL380_TAP_TIME_WINDOW)
381 st->tap_window_us = us;
382 else
383 st->tap_latent_us = us;
384
385 return 0;
386 }
387
adxl380_write_tap_time_us(struct adxl380_state * st,enum adxl380_tap_time_type tap_time_type,u32 us)388 static int adxl380_write_tap_time_us(struct adxl380_state *st,
389 enum adxl380_tap_time_type tap_time_type, u32 us)
390 {
391 int ret;
392
393 guard(mutex)(&st->lock);
394
395 ret = adxl380_set_measure_en(st, false);
396 if (ret)
397 return ret;
398
399 ret = _adxl380_write_tap_time_us(st, tap_time_type, us);
400 if (ret)
401 return ret;
402
403 return adxl380_set_measure_en(st, true);
404 }
405
adxl380_write_tap_dur_us(struct iio_dev * indio_dev,u32 us)406 static int adxl380_write_tap_dur_us(struct iio_dev *indio_dev, u32 us)
407 {
408 int ret;
409 unsigned int reg_val;
410 struct adxl380_state *st = iio_priv(indio_dev);
411
412 /* 625us per code is the scale factor of TAP_DUR register */
413 reg_val = DIV_ROUND_CLOSEST(us, 625);
414
415 ret = adxl380_set_measure_en(st, false);
416 if (ret)
417 return ret;
418
419 ret = regmap_write(st->regmap, ADXL380_TAP_DUR_REG, reg_val);
420 if (ret)
421 return ret;
422
423 return adxl380_set_measure_en(st, true);
424 }
425
adxl380_read_chn(struct adxl380_state * st,u8 addr)426 static int adxl380_read_chn(struct adxl380_state *st, u8 addr)
427 {
428 int ret;
429
430 guard(mutex)(&st->lock);
431
432 ret = regmap_bulk_read(st->regmap, addr, &st->transf_buf, 2);
433 if (ret)
434 return ret;
435
436 return get_unaligned_be16(st->transf_buf);
437 }
438
adxl380_get_odr(struct adxl380_state * st,int * odr)439 static int adxl380_get_odr(struct adxl380_state *st, int *odr)
440 {
441 *odr = st->chip_info->samp_freq_tbl[st->odr];
442
443 return 0;
444 }
445
446 static const int adxl380_lpf_div[] = {
447 1, 4, 8, 16,
448 };
449
adxl380_fill_lpf_tbl(struct adxl380_state * st)450 static int adxl380_fill_lpf_tbl(struct adxl380_state *st)
451 {
452 int ret, i;
453 int odr;
454
455 ret = adxl380_get_odr(st, &odr);
456 if (ret)
457 return ret;
458
459 for (i = 0; i < ARRAY_SIZE(st->lpf_tbl); i++)
460 st->lpf_tbl[i] = DIV_ROUND_CLOSEST(odr, adxl380_lpf_div[i]);
461
462 return 0;
463 }
464
465 static const int adxl380_hpf_mul[] = {
466 0, 247000, 62084, 15545, 3862, 954, 238,
467 };
468
adxl380_fill_hpf_tbl(struct adxl380_state * st)469 static int adxl380_fill_hpf_tbl(struct adxl380_state *st)
470 {
471 int i, ret, odr_hz;
472 u32 multiplier;
473 u64 div, rem, odr;
474
475 ret = adxl380_get_odr(st, &odr_hz);
476 if (ret)
477 return ret;
478
479 for (i = 0; i < ARRAY_SIZE(adxl380_hpf_mul); i++) {
480 odr = mul_u64_u32_shr(odr_hz, MEGA, 0);
481 multiplier = adxl380_hpf_mul[i];
482 div = div64_u64_rem(mul_u64_u32_shr(odr, multiplier, 0),
483 TERA * 100, &rem);
484
485 st->hpf_tbl[i][0] = div;
486 st->hpf_tbl[i][1] = div_u64(rem, MEGA * 100);
487 }
488
489 return 0;
490 }
491
adxl380_set_odr(struct adxl380_state * st,u8 odr)492 static int adxl380_set_odr(struct adxl380_state *st, u8 odr)
493 {
494 int ret;
495
496 guard(mutex)(&st->lock);
497
498 ret = adxl380_set_measure_en(st, false);
499 if (ret)
500 return ret;
501
502 if (odr >= ADXL380_ODR_DSM) {
503 u8 mul = odr - ADXL380_ODR_DSM;
504 u8 field;
505
506 field = FIELD_PREP(ADXL380_TRIG_CFG_DEC_2X_MSK, mul & 1);
507 ret = regmap_update_bits(st->regmap, ADXL380_TRIG_CFG_REG,
508 ADXL380_TRIG_CFG_DEC_2X_MSK, field);
509 if (ret)
510 return ret;
511
512 field = FIELD_PREP(ADXL380_TRIG_CFG_SINC_RATE_MSK, mul >> 1);
513 ret = regmap_update_bits(st->regmap, ADXL380_TRIG_CFG_REG,
514 ADXL380_TRIG_CFG_SINC_RATE_MSK, field);
515 if (ret)
516 return ret;
517 }
518
519 st->odr = odr;
520 ret = adxl380_set_measure_en(st, true);
521 if (ret)
522 return ret;
523
524 ret = adxl380_fill_lpf_tbl(st);
525 if (ret)
526 return ret;
527
528 return adxl380_fill_hpf_tbl(st);
529 }
530
adxl380_find_match_1d_tbl(const int * array,unsigned int size,int val)531 static int adxl380_find_match_1d_tbl(const int *array, unsigned int size,
532 int val)
533 {
534 int i;
535
536 for (i = 0; i < size; i++) {
537 if (val == array[i])
538 return i;
539 }
540
541 return size - 1;
542 }
543
adxl380_find_match_2d_tbl(const int (* freq_tbl)[2],int n,int val,int val2)544 static int adxl380_find_match_2d_tbl(const int (*freq_tbl)[2], int n, int val, int val2)
545 {
546 int i;
547
548 for (i = 0; i < n; i++) {
549 if (freq_tbl[i][0] == val && freq_tbl[i][1] == val2)
550 return i;
551 }
552
553 return -EINVAL;
554 }
555
adxl380_get_lpf(struct adxl380_state * st,int * lpf)556 static int adxl380_get_lpf(struct adxl380_state *st, int *lpf)
557 {
558 int ret;
559 unsigned int trig_cfg, lpf_idx;
560
561 guard(mutex)(&st->lock);
562
563 ret = regmap_read(st->regmap, ADXL380_FILTER_REG, &trig_cfg);
564 if (ret)
565 return ret;
566
567 lpf_idx = FIELD_GET(ADXL380_FILTER_LPF_MODE_MSK, trig_cfg);
568
569 *lpf = st->lpf_tbl[lpf_idx];
570
571 return 0;
572 }
573
adxl380_set_lpf(struct adxl380_state * st,u8 lpf)574 static int adxl380_set_lpf(struct adxl380_state *st, u8 lpf)
575 {
576 int ret;
577 u8 eq_bypass = 0;
578
579 guard(mutex)(&st->lock);
580
581 ret = adxl380_set_measure_en(st, false);
582 if (ret)
583 return ret;
584
585 if (lpf)
586 eq_bypass = 1;
587
588 ret = regmap_update_bits(st->regmap, ADXL380_FILTER_REG,
589 ADXL380_FILTER_EQ_FILT_MSK,
590 FIELD_PREP(ADXL380_FILTER_EQ_FILT_MSK, eq_bypass));
591 if (ret)
592 return ret;
593
594 ret = regmap_update_bits(st->regmap, ADXL380_FILTER_REG,
595 ADXL380_FILTER_LPF_MODE_MSK,
596 FIELD_PREP(ADXL380_FILTER_LPF_MODE_MSK, lpf));
597 if (ret)
598 return ret;
599
600 return adxl380_set_measure_en(st, true);
601 }
602
adxl380_get_hpf(struct adxl380_state * st,int * hpf_int,int * hpf_frac)603 static int adxl380_get_hpf(struct adxl380_state *st, int *hpf_int, int *hpf_frac)
604 {
605 int ret;
606 unsigned int trig_cfg, hpf_idx;
607
608 guard(mutex)(&st->lock);
609
610 ret = regmap_read(st->regmap, ADXL380_FILTER_REG, &trig_cfg);
611 if (ret)
612 return ret;
613
614 hpf_idx = FIELD_GET(ADXL380_FILTER_HPF_CORNER_MSK, trig_cfg);
615
616 *hpf_int = st->hpf_tbl[hpf_idx][0];
617 *hpf_frac = st->hpf_tbl[hpf_idx][1];
618
619 return 0;
620 }
621
adxl380_set_hpf(struct adxl380_state * st,u8 hpf)622 static int adxl380_set_hpf(struct adxl380_state *st, u8 hpf)
623 {
624 int ret;
625 u8 hpf_path = 0;
626
627 guard(mutex)(&st->lock);
628
629 ret = adxl380_set_measure_en(st, false);
630 if (ret)
631 return ret;
632
633 if (hpf)
634 hpf_path = 1;
635
636 ret = regmap_update_bits(st->regmap, ADXL380_FILTER_REG,
637 ADXL380_FILTER_HPF_PATH_MSK,
638 FIELD_PREP(ADXL380_FILTER_HPF_PATH_MSK, hpf_path));
639 if (ret)
640 return ret;
641
642 ret = regmap_update_bits(st->regmap, ADXL380_FILTER_REG,
643 ADXL380_FILTER_HPF_CORNER_MSK,
644 FIELD_PREP(ADXL380_FILTER_HPF_CORNER_MSK, hpf));
645 if (ret)
646 return ret;
647
648 return adxl380_set_measure_en(st, true);
649 }
650
_adxl380_set_act_inact_time_ms(struct adxl380_state * st,enum adxl380_activity_type act,u32 ms)651 static int _adxl380_set_act_inact_time_ms(struct adxl380_state *st,
652 enum adxl380_activity_type act,
653 u32 ms)
654 {
655 u8 reg = adxl380_time_reg_high_addr[act];
656 unsigned int reg_val;
657 int ret;
658
659 /* 500us per code is the scale factor of TIME_ACT / TIME_INACT registers */
660 reg_val = min(DIV_ROUND_CLOSEST(ms * 1000, 500), ADXL380_TIME_MAX);
661
662 put_unaligned_be24(reg_val, &st->transf_buf[0]);
663
664 ret = regmap_bulk_write(st->regmap, reg, st->transf_buf, sizeof(st->transf_buf));
665 if (ret)
666 return ret;
667
668 if (act == ADXL380_ACTIVITY)
669 st->act_time_ms = ms;
670 else
671 st->inact_time_ms = ms;
672
673 return 0;
674 }
675
adxl380_set_act_inact_time_ms(struct adxl380_state * st,enum adxl380_activity_type act,u32 ms)676 static int adxl380_set_act_inact_time_ms(struct adxl380_state *st,
677 enum adxl380_activity_type act,
678 u32 ms)
679 {
680 int ret;
681
682 guard(mutex)(&st->lock);
683
684 ret = adxl380_set_measure_en(st, false);
685 if (ret)
686 return ret;
687
688 ret = _adxl380_set_act_inact_time_ms(st, act, ms);
689 if (ret)
690 return ret;
691
692 return adxl380_set_measure_en(st, true);
693 }
694
adxl380_set_range(struct adxl380_state * st,u8 range)695 static int adxl380_set_range(struct adxl380_state *st, u8 range)
696 {
697 int ret;
698
699 guard(mutex)(&st->lock);
700
701 ret = adxl380_set_measure_en(st, false);
702 if (ret)
703 return ret;
704
705 ret = regmap_update_bits(st->regmap, ADXL380_OP_MODE_REG,
706 ADXL380_OP_MODE_RANGE_MSK,
707 FIELD_PREP(ADXL380_OP_MODE_RANGE_MSK, range));
708
709 if (ret)
710 return ret;
711
712 adxl380_scale_act_inact_thresholds(st, st->range, range);
713
714 /* Activity thresholds depend on range */
715 ret = adxl380_write_act_inact_threshold(st, ADXL380_ACTIVITY,
716 st->act_threshold);
717 if (ret)
718 return ret;
719
720 ret = adxl380_write_act_inact_threshold(st, ADXL380_INACTIVITY,
721 st->inact_threshold);
722 if (ret)
723 return ret;
724
725 st->range = range;
726
727 return adxl380_set_measure_en(st, true);
728 }
729
adxl380_write_act_inact_en(struct adxl380_state * st,enum adxl380_activity_type type,bool en)730 static int adxl380_write_act_inact_en(struct adxl380_state *st,
731 enum adxl380_activity_type type,
732 bool en)
733 {
734 if (type == ADXL380_ACTIVITY)
735 return regmap_update_bits(st->regmap, ADXL380_ACT_INACT_CTL_REG,
736 ADXL380_ACT_EN_MSK,
737 FIELD_PREP(ADXL380_ACT_EN_MSK, en));
738
739 return regmap_update_bits(st->regmap, ADXL380_ACT_INACT_CTL_REG,
740 ADXL380_INACT_EN_MSK,
741 FIELD_PREP(ADXL380_INACT_EN_MSK, en));
742 }
743
adxl380_read_act_inact_int(struct adxl380_state * st,enum adxl380_activity_type type,bool * en)744 static int adxl380_read_act_inact_int(struct adxl380_state *st,
745 enum adxl380_activity_type type,
746 bool *en)
747 {
748 int ret;
749 unsigned int reg_val;
750
751 guard(mutex)(&st->lock);
752
753 ret = regmap_read(st->regmap, st->int_map[0], ®_val);
754 if (ret)
755 return ret;
756
757 if (type == ADXL380_ACTIVITY)
758 *en = FIELD_GET(ADXL380_INT_MAP0_ACT_INT0_MSK, reg_val);
759 else
760 *en = FIELD_GET(ADXL380_INT_MAP0_INACT_INT0_MSK, reg_val);
761
762 return 0;
763 }
764
adxl380_write_act_inact_int(struct adxl380_state * st,enum adxl380_activity_type act,bool en)765 static int adxl380_write_act_inact_int(struct adxl380_state *st,
766 enum adxl380_activity_type act,
767 bool en)
768 {
769 if (act == ADXL380_ACTIVITY)
770 return regmap_update_bits(st->regmap, st->int_map[0],
771 ADXL380_INT_MAP0_ACT_INT0_MSK,
772 FIELD_PREP(ADXL380_INT_MAP0_ACT_INT0_MSK, en));
773
774 return regmap_update_bits(st->regmap, st->int_map[0],
775 ADXL380_INT_MAP0_INACT_INT0_MSK,
776 FIELD_PREP(ADXL380_INT_MAP0_INACT_INT0_MSK, en));
777 }
778
adxl380_act_inact_config(struct adxl380_state * st,enum adxl380_activity_type type,bool en)779 static int adxl380_act_inact_config(struct adxl380_state *st,
780 enum adxl380_activity_type type,
781 bool en)
782 {
783 int ret;
784
785 guard(mutex)(&st->lock);
786
787 ret = adxl380_set_measure_en(st, false);
788 if (ret)
789 return ret;
790
791 ret = adxl380_write_act_inact_en(st, type, en);
792 if (ret)
793 return ret;
794
795 ret = adxl380_write_act_inact_int(st, type, en);
796 if (ret)
797 return ret;
798
799 return adxl380_set_measure_en(st, true);
800 }
801
adxl380_write_tap_axis(struct adxl380_state * st,enum adxl380_axis axis)802 static int adxl380_write_tap_axis(struct adxl380_state *st,
803 enum adxl380_axis axis)
804 {
805 int ret;
806
807 ret = regmap_update_bits(st->regmap, ADXL380_TAP_CFG_REG,
808 ADXL380_TAP_AXIS_MSK,
809 FIELD_PREP(ADXL380_TAP_AXIS_MSK, axis));
810
811 if (ret)
812 return ret;
813
814 st->tap_axis_en = axis;
815
816 return 0;
817 }
818
adxl380_read_tap_int(struct adxl380_state * st,enum adxl380_tap_type type,bool * en)819 static int adxl380_read_tap_int(struct adxl380_state *st, enum adxl380_tap_type type, bool *en)
820 {
821 int ret;
822 unsigned int reg_val;
823
824 ret = regmap_read(st->regmap, st->int_map[1], ®_val);
825 if (ret)
826 return ret;
827
828 if (type == ADXL380_SINGLE_TAP)
829 *en = FIELD_GET(ADXL380_INT_MAP1_SINGLE_TAP_INT0_MSK, reg_val);
830 else
831 *en = FIELD_GET(ADXL380_INT_MAP1_DOUBLE_TAP_INT0_MSK, reg_val);
832
833 return 0;
834 }
835
adxl380_write_tap_int(struct adxl380_state * st,enum adxl380_tap_type type,bool en)836 static int adxl380_write_tap_int(struct adxl380_state *st, enum adxl380_tap_type type, bool en)
837 {
838 if (type == ADXL380_SINGLE_TAP)
839 return regmap_update_bits(st->regmap, st->int_map[1],
840 ADXL380_INT_MAP1_SINGLE_TAP_INT0_MSK,
841 FIELD_PREP(ADXL380_INT_MAP1_SINGLE_TAP_INT0_MSK, en));
842
843 return regmap_update_bits(st->regmap, st->int_map[1],
844 ADXL380_INT_MAP1_DOUBLE_TAP_INT0_MSK,
845 FIELD_PREP(ADXL380_INT_MAP1_DOUBLE_TAP_INT0_MSK, en));
846 }
847
adxl380_tap_config(struct adxl380_state * st,enum adxl380_axis axis,enum adxl380_tap_type type,bool en)848 static int adxl380_tap_config(struct adxl380_state *st,
849 enum adxl380_axis axis,
850 enum adxl380_tap_type type,
851 bool en)
852 {
853 int ret;
854
855 guard(mutex)(&st->lock);
856
857 ret = adxl380_set_measure_en(st, false);
858 if (ret)
859 return ret;
860
861 ret = adxl380_write_tap_axis(st, axis);
862 if (ret)
863 return ret;
864
865 ret = adxl380_write_tap_int(st, type, en);
866 if (ret)
867 return ret;
868
869 return adxl380_set_measure_en(st, true);
870 }
871
adxl380_set_fifo_samples(struct adxl380_state * st)872 static int adxl380_set_fifo_samples(struct adxl380_state *st)
873 {
874 int ret;
875 u16 fifo_samples = st->watermark * st->fifo_set_size;
876
877 ret = regmap_update_bits(st->regmap, ADXL380_FIFO_CONFIG_0_REG,
878 ADXL380_FIFO_SAMPLES_8_MSK,
879 FIELD_PREP(ADXL380_FIFO_SAMPLES_8_MSK,
880 (fifo_samples & BIT(8))));
881 if (ret)
882 return ret;
883
884 return regmap_write(st->regmap, ADXL380_FIFO_CONFIG_1_REG,
885 fifo_samples & 0xFF);
886 }
887
adxl380_get_status(struct adxl380_state * st,u8 * status0,u8 * status1)888 static int adxl380_get_status(struct adxl380_state *st, u8 *status0, u8 *status1)
889 {
890 int ret;
891
892 /* STATUS0, STATUS1 are adjacent regs */
893 ret = regmap_bulk_read(st->regmap, ADXL380_STATUS_0_REG,
894 &st->transf_buf, 2);
895 if (ret)
896 return ret;
897
898 *status0 = st->transf_buf[0];
899 *status1 = st->transf_buf[1];
900
901 return 0;
902 }
903
adxl380_get_fifo_entries(struct adxl380_state * st,u16 * fifo_entries)904 static int adxl380_get_fifo_entries(struct adxl380_state *st, u16 *fifo_entries)
905 {
906 int ret;
907
908 ret = regmap_bulk_read(st->regmap, ADXL380_FIFO_STATUS_0_REG,
909 &st->transf_buf, 2);
910 if (ret)
911 return ret;
912
913 *fifo_entries = st->transf_buf[0] | ((BIT(0) & st->transf_buf[1]) << 8);
914
915 return 0;
916 }
917
adxl380_push_event(struct iio_dev * indio_dev,s64 timestamp,u8 status1)918 static void adxl380_push_event(struct iio_dev *indio_dev, s64 timestamp,
919 u8 status1)
920 {
921 if (FIELD_GET(ADXL380_STATUS_1_ACT_MSK, status1))
922 iio_push_event(indio_dev,
923 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z,
924 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
925 timestamp);
926
927 if (FIELD_GET(ADXL380_STATUS_1_INACT_MSK, status1))
928 iio_push_event(indio_dev,
929 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z,
930 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
931 timestamp);
932 if (FIELD_GET(ADXL380_STATUS_1_SINGLE_TAP_MSK, status1))
933 iio_push_event(indio_dev,
934 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z,
935 IIO_EV_TYPE_GESTURE, IIO_EV_DIR_SINGLETAP),
936 timestamp);
937
938 if (FIELD_GET(ADXL380_STATUS_1_DOUBLE_TAP_MSK, status1))
939 iio_push_event(indio_dev,
940 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z,
941 IIO_EV_TYPE_GESTURE, IIO_EV_DIR_DOUBLETAP),
942 timestamp);
943 }
944
adxl380_irq_handler(int irq,void * p)945 static irqreturn_t adxl380_irq_handler(int irq, void *p)
946 {
947 struct iio_dev *indio_dev = p;
948 struct adxl380_state *st = iio_priv(indio_dev);
949 u8 status0, status1;
950 u16 fifo_entries;
951 int i;
952 int ret;
953
954 guard(mutex)(&st->lock);
955
956 ret = adxl380_get_status(st, &status0, &status1);
957 if (ret)
958 return IRQ_HANDLED;
959
960 adxl380_push_event(indio_dev, iio_get_time_ns(indio_dev), status1);
961
962 if (!FIELD_GET(ADXL380_STATUS_0_FIFO_WM_MSK, status0))
963 return IRQ_HANDLED;
964
965 ret = adxl380_get_fifo_entries(st, &fifo_entries);
966 if (ret)
967 return IRQ_HANDLED;
968
969 fifo_entries = rounddown(fifo_entries, st->fifo_set_size);
970 ret = regmap_noinc_read(st->regmap, ADXL380_FIFO_DATA, &st->fifo_buf,
971 sizeof(*st->fifo_buf) * fifo_entries);
972 if (ret)
973 return IRQ_HANDLED;
974 for (i = 0; i < fifo_entries; i += st->fifo_set_size)
975 iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);
976
977 return IRQ_HANDLED;
978 }
979
adxl380_write_calibbias_value(struct adxl380_state * st,unsigned long chan_addr,s8 calibbias)980 static int adxl380_write_calibbias_value(struct adxl380_state *st,
981 unsigned long chan_addr,
982 s8 calibbias)
983 {
984 int ret;
985
986 guard(mutex)(&st->lock);
987
988 ret = adxl380_set_measure_en(st, false);
989 if (ret)
990 return ret;
991
992 ret = regmap_write(st->regmap, ADXL380_X_DSM_OFFSET_REG + chan_addr, calibbias);
993 if (ret)
994 return ret;
995
996 return adxl380_set_measure_en(st, true);
997 }
998
adxl380_read_calibbias_value(struct adxl380_state * st,unsigned long chan_addr,int * calibbias)999 static int adxl380_read_calibbias_value(struct adxl380_state *st,
1000 unsigned long chan_addr,
1001 int *calibbias)
1002 {
1003 int ret;
1004 unsigned int reg_val;
1005
1006 guard(mutex)(&st->lock);
1007
1008 ret = regmap_read(st->regmap, ADXL380_X_DSM_OFFSET_REG + chan_addr, ®_val);
1009 if (ret)
1010 return ret;
1011
1012 *calibbias = sign_extend32(reg_val, 7);
1013
1014 return 0;
1015 }
1016
hwfifo_watermark_min_show(struct device * dev,struct device_attribute * attr,char * buf)1017 static ssize_t hwfifo_watermark_min_show(struct device *dev,
1018 struct device_attribute *attr,
1019 char *buf)
1020 {
1021 return sysfs_emit(buf, "1\n");
1022 }
1023
hwfifo_watermark_max_show(struct device * dev,struct device_attribute * attr,char * buf)1024 static ssize_t hwfifo_watermark_max_show(struct device *dev,
1025 struct device_attribute *attr,
1026 char *buf)
1027 {
1028 return sysfs_emit(buf, "%lu\n", ADXL380_FIFO_SAMPLES);
1029 }
1030
adxl380_get_fifo_watermark(struct device * dev,struct device_attribute * attr,char * buf)1031 static ssize_t adxl380_get_fifo_watermark(struct device *dev,
1032 struct device_attribute *attr,
1033 char *buf)
1034 {
1035 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1036 struct adxl380_state *st = iio_priv(indio_dev);
1037
1038 return sysfs_emit(buf, "%d\n", st->watermark);
1039 }
1040
adxl380_get_fifo_enabled(struct device * dev,struct device_attribute * attr,char * buf)1041 static ssize_t adxl380_get_fifo_enabled(struct device *dev,
1042 struct device_attribute *attr,
1043 char *buf)
1044 {
1045 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1046 struct adxl380_state *st = iio_priv(indio_dev);
1047 int ret;
1048 unsigned int reg_val;
1049
1050 ret = regmap_read(st->regmap, ADXL380_DIG_EN_REG, ®_val);
1051 if (ret)
1052 return ret;
1053
1054 return sysfs_emit(buf, "%lu\n",
1055 FIELD_GET(ADXL380_FIFO_EN_MSK, reg_val));
1056 }
1057
1058 static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0);
1059 static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0);
1060 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
1061 adxl380_get_fifo_watermark, NULL, 0);
1062 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
1063 adxl380_get_fifo_enabled, NULL, 0);
1064
1065 static const struct iio_dev_attr *adxl380_fifo_attributes[] = {
1066 &iio_dev_attr_hwfifo_watermark_min,
1067 &iio_dev_attr_hwfifo_watermark_max,
1068 &iio_dev_attr_hwfifo_watermark,
1069 &iio_dev_attr_hwfifo_enabled,
1070 NULL
1071 };
1072
adxl380_buffer_postenable(struct iio_dev * indio_dev)1073 static int adxl380_buffer_postenable(struct iio_dev *indio_dev)
1074 {
1075 struct adxl380_state *st = iio_priv(indio_dev);
1076 int i;
1077 int ret;
1078
1079 guard(mutex)(&st->lock);
1080
1081 ret = adxl380_set_measure_en(st, false);
1082 if (ret)
1083 return ret;
1084
1085 ret = regmap_update_bits(st->regmap,
1086 st->int_map[0],
1087 ADXL380_INT_MAP0_FIFO_WM_INT0_MSK,
1088 FIELD_PREP(ADXL380_INT_MAP0_FIFO_WM_INT0_MSK, 1));
1089 if (ret)
1090 return ret;
1091
1092 for_each_clear_bit(i, indio_dev->active_scan_mask, ADXL380_CH_NUM) {
1093 ret = regmap_update_bits(st->regmap, ADXL380_DIG_EN_REG,
1094 ADXL380_CHAN_EN_MSK(i),
1095 0 << (4 + i));
1096 if (ret)
1097 return ret;
1098 }
1099
1100 st->fifo_set_size = bitmap_weight(indio_dev->active_scan_mask,
1101 iio_get_masklength(indio_dev));
1102
1103 if ((st->watermark * st->fifo_set_size) > ADXL380_FIFO_SAMPLES)
1104 st->watermark = (ADXL380_FIFO_SAMPLES / st->fifo_set_size);
1105
1106 ret = adxl380_set_fifo_samples(st);
1107 if (ret)
1108 return ret;
1109
1110 ret = regmap_update_bits(st->regmap, ADXL380_DIG_EN_REG, ADXL380_FIFO_EN_MSK,
1111 FIELD_PREP(ADXL380_FIFO_EN_MSK, 1));
1112 if (ret)
1113 return ret;
1114
1115 return adxl380_set_measure_en(st, true);
1116 }
1117
adxl380_buffer_predisable(struct iio_dev * indio_dev)1118 static int adxl380_buffer_predisable(struct iio_dev *indio_dev)
1119 {
1120 struct adxl380_state *st = iio_priv(indio_dev);
1121 int ret, i;
1122
1123 guard(mutex)(&st->lock);
1124
1125 ret = adxl380_set_measure_en(st, false);
1126 if (ret)
1127 return ret;
1128
1129 ret = regmap_update_bits(st->regmap,
1130 st->int_map[0],
1131 ADXL380_INT_MAP0_FIFO_WM_INT0_MSK,
1132 FIELD_PREP(ADXL380_INT_MAP0_FIFO_WM_INT0_MSK, 0));
1133 if (ret)
1134 return ret;
1135
1136 for (i = 0; i < indio_dev->num_channels; i++) {
1137 ret = regmap_update_bits(st->regmap, ADXL380_DIG_EN_REG,
1138 ADXL380_CHAN_EN_MSK(i),
1139 1 << (4 + i));
1140 if (ret)
1141 return ret;
1142 }
1143
1144 ret = regmap_update_bits(st->regmap, ADXL380_DIG_EN_REG, ADXL380_FIFO_EN_MSK,
1145 FIELD_PREP(ADXL380_FIFO_EN_MSK, 0));
1146 if (ret)
1147 return ret;
1148
1149 return adxl380_set_measure_en(st, true);
1150 }
1151
1152 static const struct iio_buffer_setup_ops adxl380_buffer_ops = {
1153 .postenable = adxl380_buffer_postenable,
1154 .predisable = adxl380_buffer_predisable,
1155 };
1156
adxl380_samp_freq_avail(struct adxl380_state * st,const int ** vals,int * length)1157 static int adxl380_samp_freq_avail(struct adxl380_state *st, const int **vals,
1158 int *length)
1159 {
1160 bool act_inact_enabled;
1161 int ret;
1162
1163 if (!st->chip_info->has_low_power) {
1164 *vals = st->chip_info->samp_freq_tbl + ADXL380_ODR_DSM;
1165 *length = ADXL380_ODR_MAX - ADXL380_ODR_DSM;
1166 return 0;
1167 }
1168
1169 ret = adxl380_act_inact_enabled(st, &act_inact_enabled);
1170 if (ret)
1171 return 0;
1172
1173 /*
1174 * Motion detection is only functional in low-power mode, and this
1175 * affects the available sampling frequencies.
1176 */
1177 *vals = st->chip_info->samp_freq_tbl;
1178 *length = act_inact_enabled ? ADXL380_ODR_DSM : ADXL380_ODR_MAX;
1179
1180 return 0;
1181 }
1182
adxl380_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)1183 static int adxl380_read_raw(struct iio_dev *indio_dev,
1184 struct iio_chan_spec const *chan,
1185 int *val, int *val2, long info)
1186 {
1187 struct adxl380_state *st = iio_priv(indio_dev);
1188 int ret;
1189
1190 switch (info) {
1191 case IIO_CHAN_INFO_RAW:
1192 if (!iio_device_claim_direct(indio_dev))
1193 return -EBUSY;
1194
1195 ret = adxl380_read_chn(st, chan->address);
1196 iio_device_release_direct(indio_dev);
1197 if (ret < 0)
1198 return ret;
1199
1200 *val = sign_extend32(ret >> chan->scan_type.shift,
1201 chan->scan_type.realbits - 1);
1202 return IIO_VAL_INT;
1203 case IIO_CHAN_INFO_SCALE:
1204 switch (chan->type) {
1205 case IIO_ACCEL:
1206 scoped_guard(mutex, &st->lock) {
1207 *val = st->chip_info->scale_tbl[st->range][0];
1208 *val2 = st->chip_info->scale_tbl[st->range][1];
1209 }
1210 return IIO_VAL_INT_PLUS_NANO;
1211 case IIO_TEMP:
1212 /* 10.2 LSB / Degree Celsius */
1213 *val = 10000;
1214 *val2 = 102;
1215 return IIO_VAL_FRACTIONAL;
1216 default:
1217 return -EINVAL;
1218 }
1219 case IIO_CHAN_INFO_OFFSET:
1220 switch (chan->type) {
1221 case IIO_TEMP:
1222 *val = st->chip_info->temp_offset;
1223 return IIO_VAL_INT;
1224 default:
1225 return -EINVAL;
1226 }
1227 case IIO_CHAN_INFO_CALIBBIAS:
1228 switch (chan->type) {
1229 case IIO_ACCEL:
1230 ret = adxl380_read_calibbias_value(st, chan->scan_index, val);
1231 if (ret)
1232 return ret;
1233 return IIO_VAL_INT;
1234 default:
1235 return -EINVAL;
1236 }
1237 case IIO_CHAN_INFO_SAMP_FREQ:
1238 ret = adxl380_get_odr(st, val);
1239 if (ret)
1240 return ret;
1241 return IIO_VAL_INT;
1242 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
1243 ret = adxl380_get_lpf(st, val);
1244 if (ret)
1245 return ret;
1246 return IIO_VAL_INT;
1247 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
1248 ret = adxl380_get_hpf(st, val, val2);
1249 if (ret)
1250 return ret;
1251 return IIO_VAL_INT_PLUS_MICRO;
1252 }
1253
1254 return -EINVAL;
1255 }
1256
adxl380_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)1257 static int adxl380_read_avail(struct iio_dev *indio_dev,
1258 struct iio_chan_spec const *chan,
1259 const int **vals, int *type, int *length,
1260 long mask)
1261 {
1262 struct adxl380_state *st = iio_priv(indio_dev);
1263 int ret;
1264
1265 if (chan->type != IIO_ACCEL)
1266 return -EINVAL;
1267
1268 switch (mask) {
1269 case IIO_CHAN_INFO_SCALE:
1270 *vals = (const int *)st->chip_info->scale_tbl;
1271 *type = IIO_VAL_INT_PLUS_NANO;
1272 *length = ARRAY_SIZE(st->chip_info->scale_tbl) * 2;
1273 return IIO_AVAIL_LIST;
1274 case IIO_CHAN_INFO_SAMP_FREQ:
1275 ret = adxl380_samp_freq_avail(st, vals, length);
1276 if (ret)
1277 return ret;
1278
1279 *type = IIO_VAL_INT;
1280 return IIO_AVAIL_LIST;
1281 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
1282 *vals = (const int *)st->lpf_tbl;
1283 *type = IIO_VAL_INT;
1284 *length = ARRAY_SIZE(st->lpf_tbl);
1285 return IIO_AVAIL_LIST;
1286 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
1287 *vals = (const int *)st->hpf_tbl;
1288 *type = IIO_VAL_INT_PLUS_MICRO;
1289 /* Values are stored in a 2D matrix */
1290 *length = ARRAY_SIZE(st->hpf_tbl) * 2;
1291 return IIO_AVAIL_LIST;
1292 default:
1293 return -EINVAL;
1294 }
1295 }
1296
adxl380_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)1297 static int adxl380_write_raw(struct iio_dev *indio_dev,
1298 struct iio_chan_spec const *chan,
1299 int val, int val2, long info)
1300 {
1301 struct adxl380_state *st = iio_priv(indio_dev);
1302 const int *freq_vals;
1303 int odr_index, lpf_index, hpf_index, range_index, freq_count, ret;
1304
1305 switch (info) {
1306 case IIO_CHAN_INFO_SAMP_FREQ:
1307 ret = adxl380_samp_freq_avail(st, &freq_vals, &freq_count);
1308 if (ret)
1309 return ret;
1310
1311 odr_index = adxl380_find_match_1d_tbl(freq_vals, freq_count,
1312 val);
1313 return adxl380_set_odr(st, odr_index);
1314 case IIO_CHAN_INFO_CALIBBIAS:
1315 return adxl380_write_calibbias_value(st, chan->scan_index, val);
1316 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
1317 lpf_index = adxl380_find_match_1d_tbl(st->lpf_tbl,
1318 ARRAY_SIZE(st->lpf_tbl),
1319 val);
1320 return adxl380_set_lpf(st, lpf_index);
1321 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
1322 hpf_index = adxl380_find_match_2d_tbl(st->hpf_tbl,
1323 ARRAY_SIZE(st->hpf_tbl),
1324 val, val2);
1325 if (hpf_index < 0)
1326 return hpf_index;
1327 return adxl380_set_hpf(st, hpf_index);
1328 case IIO_CHAN_INFO_SCALE:
1329 range_index = adxl380_find_match_2d_tbl(st->chip_info->scale_tbl,
1330 ARRAY_SIZE(st->chip_info->scale_tbl),
1331 val, val2);
1332 if (range_index < 0)
1333 return range_index;
1334 return adxl380_set_range(st, range_index);
1335 default:
1336 return -EINVAL;
1337 }
1338 }
1339
adxl380_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long info)1340 static int adxl380_write_raw_get_fmt(struct iio_dev *indio_dev,
1341 struct iio_chan_spec const *chan,
1342 long info)
1343 {
1344 switch (info) {
1345 case IIO_CHAN_INFO_SCALE:
1346 if (chan->type != IIO_ACCEL)
1347 return -EINVAL;
1348
1349 return IIO_VAL_INT_PLUS_NANO;
1350 default:
1351 return IIO_VAL_INT_PLUS_MICRO;
1352 }
1353 }
1354
adxl380_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)1355 static int adxl380_read_event_config(struct iio_dev *indio_dev,
1356 const struct iio_chan_spec *chan,
1357 enum iio_event_type type,
1358 enum iio_event_direction dir)
1359 {
1360 struct adxl380_state *st = iio_priv(indio_dev);
1361 int ret;
1362 bool int_en;
1363 bool tap_axis_en = false;
1364
1365 switch (chan->channel2) {
1366 case IIO_MOD_X:
1367 tap_axis_en = st->tap_axis_en == ADXL380_X_AXIS;
1368 break;
1369 case IIO_MOD_Y:
1370 tap_axis_en = st->tap_axis_en == ADXL380_Y_AXIS;
1371 break;
1372 case IIO_MOD_Z:
1373 tap_axis_en = st->tap_axis_en == ADXL380_Z_AXIS;
1374 break;
1375 default:
1376 return -EINVAL;
1377 }
1378
1379 switch (dir) {
1380 case IIO_EV_DIR_RISING:
1381 ret = adxl380_read_act_inact_int(st, ADXL380_ACTIVITY, &int_en);
1382 if (ret)
1383 return ret;
1384 return int_en;
1385 case IIO_EV_DIR_FALLING:
1386 ret = adxl380_read_act_inact_int(st, ADXL380_INACTIVITY, &int_en);
1387 if (ret)
1388 return ret;
1389 return int_en;
1390 case IIO_EV_DIR_SINGLETAP:
1391 ret = adxl380_read_tap_int(st, ADXL380_SINGLE_TAP, &int_en);
1392 if (ret)
1393 return ret;
1394 return int_en && tap_axis_en;
1395 case IIO_EV_DIR_DOUBLETAP:
1396 ret = adxl380_read_tap_int(st, ADXL380_DOUBLE_TAP, &int_en);
1397 if (ret)
1398 return ret;
1399 return int_en && tap_axis_en;
1400 default:
1401 return -EINVAL;
1402 }
1403 }
1404
adxl380_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)1405 static int adxl380_write_event_config(struct iio_dev *indio_dev,
1406 const struct iio_chan_spec *chan,
1407 enum iio_event_type type,
1408 enum iio_event_direction dir,
1409 bool state)
1410 {
1411 struct adxl380_state *st = iio_priv(indio_dev);
1412 enum adxl380_axis axis;
1413
1414 switch (chan->channel2) {
1415 case IIO_MOD_X:
1416 axis = ADXL380_X_AXIS;
1417 break;
1418 case IIO_MOD_Y:
1419 axis = ADXL380_Y_AXIS;
1420 break;
1421 case IIO_MOD_Z:
1422 axis = ADXL380_Z_AXIS;
1423 break;
1424 default:
1425 return -EINVAL;
1426 }
1427
1428 switch (dir) {
1429 case IIO_EV_DIR_RISING:
1430 return adxl380_act_inact_config(st, ADXL380_ACTIVITY, state);
1431 case IIO_EV_DIR_FALLING:
1432 return adxl380_act_inact_config(st, ADXL380_INACTIVITY, state);
1433 case IIO_EV_DIR_SINGLETAP:
1434 return adxl380_tap_config(st, axis, ADXL380_SINGLE_TAP, state);
1435 case IIO_EV_DIR_DOUBLETAP:
1436 return adxl380_tap_config(st, axis, ADXL380_DOUBLE_TAP, state);
1437 default:
1438 return -EINVAL;
1439 }
1440 }
1441
adxl380_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)1442 static int adxl380_read_event_value(struct iio_dev *indio_dev,
1443 const struct iio_chan_spec *chan,
1444 enum iio_event_type type,
1445 enum iio_event_direction dir,
1446 enum iio_event_info info,
1447 int *val, int *val2)
1448 {
1449 struct adxl380_state *st = iio_priv(indio_dev);
1450
1451 guard(mutex)(&st->lock);
1452
1453 switch (type) {
1454 case IIO_EV_TYPE_THRESH:
1455 switch (info) {
1456 case IIO_EV_INFO_VALUE: {
1457 switch (dir) {
1458 case IIO_EV_DIR_RISING:
1459 *val = st->act_threshold;
1460 return IIO_VAL_INT;
1461 case IIO_EV_DIR_FALLING:
1462 *val = st->inact_threshold;
1463 return IIO_VAL_INT;
1464 default:
1465 return -EINVAL;
1466 }
1467 }
1468 case IIO_EV_INFO_PERIOD:
1469 switch (dir) {
1470 case IIO_EV_DIR_RISING:
1471 *val = st->act_time_ms;
1472 *val2 = 1000;
1473 return IIO_VAL_FRACTIONAL;
1474 case IIO_EV_DIR_FALLING:
1475 *val = st->inact_time_ms;
1476 *val2 = 1000;
1477 return IIO_VAL_FRACTIONAL;
1478 default:
1479 return -EINVAL;
1480 }
1481 default:
1482 return -EINVAL;
1483 }
1484 case IIO_EV_TYPE_GESTURE:
1485 switch (info) {
1486 case IIO_EV_INFO_VALUE:
1487 *val = st->tap_threshold;
1488 return IIO_VAL_INT;
1489 case IIO_EV_INFO_RESET_TIMEOUT:
1490 *val = st->tap_window_us;
1491 *val2 = 1000000;
1492 return IIO_VAL_FRACTIONAL;
1493 case IIO_EV_INFO_TAP2_MIN_DELAY:
1494 *val = st->tap_latent_us;
1495 *val2 = 1000000;
1496 return IIO_VAL_FRACTIONAL;
1497 default:
1498 return -EINVAL;
1499 }
1500 default:
1501 return -EINVAL;
1502 }
1503 }
1504
adxl380_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)1505 static int adxl380_write_event_value(struct iio_dev *indio_dev,
1506 const struct iio_chan_spec *chan,
1507 enum iio_event_type type, enum iio_event_direction dir,
1508 enum iio_event_info info, int val, int val2)
1509 {
1510 struct adxl380_state *st = iio_priv(indio_dev);
1511 u32 val_ms, val_us;
1512
1513 if (chan->type != IIO_ACCEL)
1514 return -EINVAL;
1515
1516 switch (type) {
1517 case IIO_EV_TYPE_THRESH:
1518 switch (info) {
1519 case IIO_EV_INFO_VALUE:
1520 switch (dir) {
1521 case IIO_EV_DIR_RISING:
1522 return adxl380_set_act_inact_threshold(indio_dev,
1523 ADXL380_ACTIVITY, val);
1524 case IIO_EV_DIR_FALLING:
1525 return adxl380_set_act_inact_threshold(indio_dev,
1526 ADXL380_INACTIVITY, val);
1527 default:
1528 return -EINVAL;
1529 }
1530 case IIO_EV_INFO_PERIOD:
1531 val_ms = val * 1000 + DIV_ROUND_UP(val2, 1000);
1532 switch (dir) {
1533 case IIO_EV_DIR_RISING:
1534 return adxl380_set_act_inact_time_ms(st,
1535 ADXL380_ACTIVITY, val_ms);
1536 case IIO_EV_DIR_FALLING:
1537 return adxl380_set_act_inact_time_ms(st,
1538 ADXL380_INACTIVITY, val_ms);
1539 default:
1540 return -EINVAL;
1541 }
1542
1543 default:
1544 return -EINVAL;
1545 }
1546 case IIO_EV_TYPE_GESTURE:
1547 switch (info) {
1548 case IIO_EV_INFO_VALUE:
1549 return adxl380_set_tap_threshold_value(indio_dev, val);
1550 case IIO_EV_INFO_RESET_TIMEOUT:
1551 val_us = val * 1000000 + val2;
1552 return adxl380_write_tap_time_us(st,
1553 ADXL380_TAP_TIME_WINDOW,
1554 val_us);
1555 case IIO_EV_INFO_TAP2_MIN_DELAY:
1556 val_us = val * 1000000 + val2;
1557 return adxl380_write_tap_time_us(st,
1558 ADXL380_TAP_TIME_LATENT,
1559 val_us);
1560 default:
1561 return -EINVAL;
1562 }
1563 default:
1564 return -EINVAL;
1565 }
1566 }
1567
in_accel_gesture_tap_maxtomin_time_show(struct device * dev,struct device_attribute * attr,char * buf)1568 static ssize_t in_accel_gesture_tap_maxtomin_time_show(struct device *dev,
1569 struct device_attribute *attr,
1570 char *buf)
1571 {
1572 int vals[2];
1573 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1574 struct adxl380_state *st = iio_priv(indio_dev);
1575
1576 guard(mutex)(&st->lock);
1577
1578 vals[0] = st->tap_duration_us;
1579 vals[1] = MICRO;
1580
1581 return iio_format_value(buf, IIO_VAL_FRACTIONAL, 2, vals);
1582 }
1583
in_accel_gesture_tap_maxtomin_time_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)1584 static ssize_t in_accel_gesture_tap_maxtomin_time_store(struct device *dev,
1585 struct device_attribute *attr,
1586 const char *buf, size_t len)
1587 {
1588 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1589 struct adxl380_state *st = iio_priv(indio_dev);
1590 int ret, val_int, val_fract_us;
1591
1592 guard(mutex)(&st->lock);
1593
1594 ret = iio_str_to_fixpoint(buf, 100000, &val_int, &val_fract_us);
1595 if (ret)
1596 return ret;
1597
1598 /* maximum value is 255 * 625 us = 0.159375 seconds */
1599 if (val_int || val_fract_us > 159375 || val_fract_us < 0)
1600 return -EINVAL;
1601
1602 ret = adxl380_write_tap_dur_us(indio_dev, val_fract_us);
1603 if (ret)
1604 return ret;
1605
1606 return len;
1607 }
1608
1609 static IIO_DEVICE_ATTR_RW(in_accel_gesture_tap_maxtomin_time, 0);
1610
1611 static struct attribute *adxl380_event_attributes[] = {
1612 &iio_dev_attr_in_accel_gesture_tap_maxtomin_time.dev_attr.attr,
1613 NULL
1614 };
1615
1616 static const struct attribute_group adxl380_event_attribute_group = {
1617 .attrs = adxl380_event_attributes,
1618 };
1619
adxl380_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)1620 static int adxl380_reg_access(struct iio_dev *indio_dev,
1621 unsigned int reg,
1622 unsigned int writeval,
1623 unsigned int *readval)
1624 {
1625 struct adxl380_state *st = iio_priv(indio_dev);
1626
1627 if (readval)
1628 return regmap_read(st->regmap, reg, readval);
1629
1630 return regmap_write(st->regmap, reg, writeval);
1631 }
1632
adxl380_set_watermark(struct iio_dev * indio_dev,unsigned int val)1633 static int adxl380_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1634 {
1635 struct adxl380_state *st = iio_priv(indio_dev);
1636
1637 st->watermark = min(val, ADXL380_FIFO_SAMPLES);
1638
1639 return 0;
1640 }
1641
1642 static const struct iio_info adxl318_info = {
1643 .read_raw = adxl380_read_raw,
1644 .read_avail = &adxl380_read_avail,
1645 .write_raw = adxl380_write_raw,
1646 .write_raw_get_fmt = adxl380_write_raw_get_fmt,
1647 .debugfs_reg_access = &adxl380_reg_access,
1648 .hwfifo_set_watermark = adxl380_set_watermark,
1649 };
1650
1651 static const struct iio_info adxl380_info = {
1652 .read_raw = adxl380_read_raw,
1653 .read_avail = &adxl380_read_avail,
1654 .write_raw = adxl380_write_raw,
1655 .write_raw_get_fmt = adxl380_write_raw_get_fmt,
1656 .read_event_config = adxl380_read_event_config,
1657 .write_event_config = adxl380_write_event_config,
1658 .read_event_value = adxl380_read_event_value,
1659 .write_event_value = adxl380_write_event_value,
1660 .event_attrs = &adxl380_event_attribute_group,
1661 .debugfs_reg_access = &adxl380_reg_access,
1662 .hwfifo_set_watermark = adxl380_set_watermark,
1663 };
1664
1665 const struct adxl380_chip_info adxl318_chip_info = {
1666 .name = "adxl318",
1667 .chip_id = ADXL318_ID_VAL,
1668 .scale_tbl = {
1669 [ADXL380_OP_MODE_4G_RANGE] = { 0, 1307226 },
1670 [ADXL380_OP_MODE_8G_RANGE] = { 0, 2615434 },
1671 [ADXL380_OP_MODE_16G_RANGE] = { 0, 5229886 },
1672 },
1673 .samp_freq_tbl = { 0, 8000, 16000, 32000 },
1674 /*
1675 * The datasheet defines an intercept of 550 LSB at 25 degC
1676 * and a sensitivity of 10.2 LSB/C.
1677 */
1678 .temp_offset = 25 * 102 / 10 - 550,
1679 .info = &adxl318_info,
1680 };
1681 EXPORT_SYMBOL_NS_GPL(adxl318_chip_info, "IIO_ADXL380");
1682
1683 const struct adxl380_chip_info adxl319_chip_info = {
1684 .name = "adxl319",
1685 .chip_id = ADXL319_ID_VAL,
1686 .scale_tbl = {
1687 [ADXL382_OP_MODE_15G_RANGE] = { 0, 4903325 },
1688 [ADXL382_OP_MODE_30G_RANGE] = { 0, 9806650 },
1689 [ADXL382_OP_MODE_60G_RANGE] = { 0, 19613300 },
1690 },
1691 .samp_freq_tbl = { 0, 16000, 32000, 64000 },
1692 /*
1693 * The datasheet defines an intercept of 550 LSB at 25 degC
1694 * and a sensitivity of 10.2 LSB/C.
1695 */
1696 .temp_offset = 25 * 102 / 10 - 550,
1697 .info = &adxl318_info,
1698 };
1699 EXPORT_SYMBOL_NS_GPL(adxl319_chip_info, "IIO_ADXL380");
1700
1701 const struct adxl380_chip_info adxl380_chip_info = {
1702 .name = "adxl380",
1703 .chip_id = ADXL380_ID_VAL,
1704 .scale_tbl = {
1705 [ADXL380_OP_MODE_4G_RANGE] = { 0, 1307226 },
1706 [ADXL380_OP_MODE_8G_RANGE] = { 0, 2615434 },
1707 [ADXL380_OP_MODE_16G_RANGE] = { 0, 5229886 },
1708 },
1709 .samp_freq_tbl = { 1000, 8000, 16000, 32000 },
1710 /*
1711 * The datasheet defines an intercept of 470 LSB at 25 degC
1712 * and a sensitivity of 10.2 LSB/C.
1713 */
1714 .temp_offset = 25 * 102 / 10 - 470,
1715 .has_low_power = true,
1716 .info = &adxl380_info,
1717
1718 };
1719 EXPORT_SYMBOL_NS_GPL(adxl380_chip_info, "IIO_ADXL380");
1720
1721 const struct adxl380_chip_info adxl382_chip_info = {
1722 .name = "adxl382",
1723 .chip_id = ADXL382_ID_VAL,
1724 .scale_tbl = {
1725 [ADXL382_OP_MODE_15G_RANGE] = { 0, 4903325 },
1726 [ADXL382_OP_MODE_30G_RANGE] = { 0, 9806650 },
1727 [ADXL382_OP_MODE_60G_RANGE] = { 0, 19613300 },
1728 },
1729 .samp_freq_tbl = { 1000, 16000, 32000, 64000 },
1730 /*
1731 * The datasheet defines an intercept of 570 LSB at 25 degC
1732 * and a sensitivity of 10.2 LSB/C.
1733 */
1734 .temp_offset = 25 * 102 / 10 - 570,
1735 .has_low_power = true,
1736 .info = &adxl380_info,
1737 };
1738 EXPORT_SYMBOL_NS_GPL(adxl382_chip_info, "IIO_ADXL380");
1739
1740 static const struct iio_event_spec adxl380_events[] = {
1741 {
1742 .type = IIO_EV_TYPE_THRESH,
1743 .dir = IIO_EV_DIR_RISING,
1744 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) |
1745 BIT(IIO_EV_INFO_VALUE) |
1746 BIT(IIO_EV_INFO_PERIOD),
1747 },
1748 {
1749 .type = IIO_EV_TYPE_THRESH,
1750 .dir = IIO_EV_DIR_FALLING,
1751 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) |
1752 BIT(IIO_EV_INFO_VALUE) |
1753 BIT(IIO_EV_INFO_PERIOD),
1754 },
1755 {
1756 .type = IIO_EV_TYPE_GESTURE,
1757 .dir = IIO_EV_DIR_SINGLETAP,
1758 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1759 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1760 BIT(IIO_EV_INFO_RESET_TIMEOUT),
1761 },
1762 {
1763 .type = IIO_EV_TYPE_GESTURE,
1764 .dir = IIO_EV_DIR_DOUBLETAP,
1765 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1766 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1767 BIT(IIO_EV_INFO_RESET_TIMEOUT) |
1768 BIT(IIO_EV_INFO_TAP2_MIN_DELAY),
1769 },
1770 };
1771
1772 #define ADXL380_ACCEL_CHANNEL(index, reg, axis) { \
1773 .type = IIO_ACCEL, \
1774 .address = reg, \
1775 .modified = 1, \
1776 .channel2 = IIO_MOD_##axis, \
1777 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1778 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1779 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1780 .info_mask_shared_by_all_available = \
1781 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1782 .info_mask_shared_by_type = \
1783 BIT(IIO_CHAN_INFO_SCALE) | \
1784 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
1785 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
1786 .info_mask_shared_by_type_available = \
1787 BIT(IIO_CHAN_INFO_SCALE) | \
1788 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
1789 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
1790 .scan_index = index, \
1791 .scan_type = { \
1792 .sign = 's', \
1793 .realbits = 16, \
1794 .storagebits = 16, \
1795 .endianness = IIO_BE, \
1796 }, \
1797 .event_spec = adxl380_events, \
1798 .num_event_specs = ARRAY_SIZE(adxl380_events) \
1799 }
1800
1801 static const struct iio_chan_spec adxl380_channels[] = {
1802 ADXL380_ACCEL_CHANNEL(0, ADXL380_X_DATA_H_REG, X),
1803 ADXL380_ACCEL_CHANNEL(1, ADXL380_Y_DATA_H_REG, Y),
1804 ADXL380_ACCEL_CHANNEL(2, ADXL380_Z_DATA_H_REG, Z),
1805 {
1806 .type = IIO_TEMP,
1807 .address = ADXL380_T_DATA_H_REG,
1808 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1809 BIT(IIO_CHAN_INFO_SCALE) |
1810 BIT(IIO_CHAN_INFO_OFFSET),
1811 .scan_index = 3,
1812 .scan_type = {
1813 .sign = 's',
1814 .realbits = 12,
1815 .storagebits = 16,
1816 .shift = 4,
1817 .endianness = IIO_BE,
1818 },
1819 },
1820 };
1821
adxl380_config_irq(struct iio_dev * indio_dev)1822 static int adxl380_config_irq(struct iio_dev *indio_dev)
1823 {
1824 struct adxl380_state *st = iio_priv(indio_dev);
1825 unsigned long irq_flag;
1826 u32 irq_type;
1827 u8 polarity;
1828 int ret;
1829
1830 st->irq = fwnode_irq_get_byname(dev_fwnode(st->dev), "INT0");
1831 if (st->irq > 0) {
1832 st->int_map[0] = ADXL380_INT0_MAP0_REG;
1833 st->int_map[1] = ADXL380_INT0_MAP1_REG;
1834 } else {
1835 st->irq = fwnode_irq_get_byname(dev_fwnode(st->dev), "INT1");
1836 if (st->irq < 0)
1837 return dev_err_probe(st->dev, st->irq,
1838 "no interrupt name specified\n");
1839 st->int_map[0] = ADXL380_INT1_MAP0_REG;
1840 st->int_map[1] = ADXL380_INT1_MAP1_REG;
1841 }
1842
1843 irq_type = irq_get_trigger_type(st->irq);
1844 if (irq_type == IRQ_TYPE_LEVEL_HIGH) {
1845 polarity = 0;
1846 irq_flag = IRQF_TRIGGER_HIGH | IRQF_ONESHOT;
1847 } else if (irq_type == IRQ_TYPE_LEVEL_LOW) {
1848 polarity = 1;
1849 irq_flag = IRQF_TRIGGER_LOW | IRQF_ONESHOT;
1850 } else {
1851 return dev_err_probe(st->dev, -EINVAL,
1852 "Invalid interrupt 0x%x. Only level interrupts supported\n",
1853 irq_type);
1854 }
1855
1856 ret = regmap_update_bits(st->regmap, ADXL380_INT0_REG,
1857 ADXL380_INT0_POL_MSK,
1858 FIELD_PREP(ADXL380_INT0_POL_MSK, polarity));
1859 if (ret)
1860 return ret;
1861
1862 return devm_request_threaded_irq(st->dev, st->irq, NULL,
1863 adxl380_irq_handler, irq_flag,
1864 indio_dev->name, indio_dev);
1865 }
1866
adxl380_setup(struct iio_dev * indio_dev)1867 static int adxl380_setup(struct iio_dev *indio_dev)
1868 {
1869 unsigned int reg_val;
1870 u16 part_id, chip_id;
1871 int ret, i;
1872 struct adxl380_state *st = iio_priv(indio_dev);
1873
1874 ret = regmap_read(st->regmap, ADXL380_DEVID_AD_REG, ®_val);
1875 if (ret)
1876 return ret;
1877
1878 if (reg_val != ADXL380_DEVID_AD_VAL)
1879 dev_warn(st->dev, "Unknown chip id %x\n", reg_val);
1880
1881 ret = regmap_bulk_read(st->regmap, ADLX380_PART_ID_REG,
1882 &st->transf_buf, 2);
1883 if (ret)
1884 return ret;
1885
1886 part_id = get_unaligned_be16(st->transf_buf);
1887 part_id >>= 4;
1888
1889 if (part_id != ADXL380_ID_VAL)
1890 dev_warn(st->dev, "Unknown part id %x\n", part_id);
1891
1892 ret = regmap_read(st->regmap, ADXL380_MISC_0_REG, ®_val);
1893 if (ret)
1894 return ret;
1895
1896 /* Bit to differentiate between ADXL380/382. */
1897 if (reg_val & ADXL380_XL382_MSK)
1898 chip_id = ADXL382_ID_VAL;
1899 else
1900 chip_id = ADXL380_ID_VAL;
1901
1902 if (chip_id != st->chip_info->chip_id)
1903 dev_warn(st->dev, "Unknown chip id %x\n", chip_id);
1904
1905 ret = regmap_write(st->regmap, ADXL380_RESET_REG, ADXL380_RESET_CODE);
1906 if (ret)
1907 return ret;
1908
1909 /*
1910 * A latency of approximately 0.5 ms is required after soft reset.
1911 * Stated in the register REG_RESET description.
1912 */
1913 fsleep(500);
1914
1915 for (i = 0; i < indio_dev->num_channels; i++) {
1916 ret = regmap_update_bits(st->regmap, ADXL380_DIG_EN_REG,
1917 ADXL380_CHAN_EN_MSK(i),
1918 1 << (4 + i));
1919 if (ret)
1920 return ret;
1921 }
1922
1923 ret = regmap_update_bits(st->regmap, ADXL380_FIFO_CONFIG_0_REG,
1924 ADXL380_FIFO_MODE_MSK,
1925 FIELD_PREP(ADXL380_FIFO_MODE_MSK, ADXL380_FIFO_STREAMED));
1926 if (ret)
1927 return ret;
1928
1929 /* Select all 3 axis for act/inact detection. */
1930 ret = regmap_update_bits(st->regmap, ADXL380_SNSR_AXIS_EN_REG,
1931 ADXL380_ACT_INACT_AXIS_EN_MSK,
1932 FIELD_PREP(ADXL380_ACT_INACT_AXIS_EN_MSK,
1933 ADXL380_ACT_INACT_AXIS_EN_MSK));
1934 if (ret)
1935 return ret;
1936
1937 ret = adxl380_config_irq(indio_dev);
1938 if (ret)
1939 return ret;
1940
1941 ret = adxl380_fill_lpf_tbl(st);
1942 if (ret)
1943 return ret;
1944
1945 ret = adxl380_fill_hpf_tbl(st);
1946 if (ret)
1947 return ret;
1948
1949 return adxl380_set_measure_en(st, true);
1950 }
1951
adxl380_probe(struct device * dev,struct regmap * regmap,const struct adxl380_chip_info * chip_info)1952 int adxl380_probe(struct device *dev, struct regmap *regmap,
1953 const struct adxl380_chip_info *chip_info)
1954 {
1955 struct iio_dev *indio_dev;
1956 struct adxl380_state *st;
1957 int ret;
1958
1959 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1960 if (!indio_dev)
1961 return -ENOMEM;
1962
1963 st = iio_priv(indio_dev);
1964
1965 st->dev = dev;
1966 st->regmap = regmap;
1967 st->chip_info = chip_info;
1968 st->odr = ADXL380_ODR_DSM;
1969
1970 mutex_init(&st->lock);
1971
1972 indio_dev->channels = adxl380_channels;
1973 indio_dev->num_channels = ARRAY_SIZE(adxl380_channels);
1974 indio_dev->name = chip_info->name;
1975 indio_dev->info = chip_info->info;
1976 indio_dev->modes = INDIO_DIRECT_MODE;
1977
1978 ret = devm_regulator_get_enable(dev, "vddio");
1979 if (ret)
1980 return dev_err_probe(st->dev, ret,
1981 "Failed to get vddio regulator\n");
1982
1983 ret = devm_regulator_get_enable(st->dev, "vsupply");
1984 if (ret)
1985 return dev_err_probe(st->dev, ret,
1986 "Failed to get vsupply regulator\n");
1987
1988 ret = adxl380_setup(indio_dev);
1989 if (ret)
1990 return ret;
1991
1992 ret = devm_iio_kfifo_buffer_setup_ext(st->dev, indio_dev,
1993 &adxl380_buffer_ops,
1994 adxl380_fifo_attributes);
1995 if (ret)
1996 return ret;
1997
1998 return devm_iio_device_register(dev, indio_dev);
1999 }
2000 EXPORT_SYMBOL_NS_GPL(adxl380_probe, "IIO_ADXL380");
2001
2002 MODULE_AUTHOR("Ramona Gradinariu <ramona.gradinariu@analog.com>");
2003 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com>");
2004 MODULE_DESCRIPTION("Analog Devices ADXL380 3-axis accelerometer driver");
2005 MODULE_LICENSE("GPL");
2006