1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * adux1020.c - Support for Analog Devices ADUX1020 photometric sensor
4 *
5 * Copyright (C) 2019 Linaro Ltd.
6 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
7 *
8 * TODO: Triggered buffer support
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/delay.h>
13 #include <linux/err.h>
14 #include <linux/i2c.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/module.h>
19 #include <linux/mutex.h>
20 #include <linux/regmap.h>
21
22 #include <linux/iio/iio.h>
23 #include <linux/iio/sysfs.h>
24 #include <linux/iio/events.h>
25
26 #define ADUX1020_REGMAP_NAME "adux1020_regmap"
27 #define ADUX1020_DRV_NAME "adux1020"
28
29 /* System registers */
30 #define ADUX1020_REG_CHIP_ID 0x08
31 #define ADUX1020_REG_SLAVE_ADDRESS 0x09
32
33 #define ADUX1020_REG_SW_RESET 0x0f
34 #define ADUX1020_REG_INT_ENABLE 0x1c
35 #define ADUX1020_REG_INT_POLARITY 0x1d
36 #define ADUX1020_REG_PROX_TH_ON1 0x2a
37 #define ADUX1020_REG_PROX_TH_OFF1 0x2b
38 #define ADUX1020_REG_PROX_TYPE 0x2f
39 #define ADUX1020_REG_TEST_MODES_3 0x32
40 #define ADUX1020_REG_FORCE_MODE 0x33
41 #define ADUX1020_REG_FREQUENCY 0x40
42 #define ADUX1020_REG_LED_CURRENT 0x41
43 #define ADUX1020_REG_OP_MODE 0x45
44 #define ADUX1020_REG_INT_MASK 0x48
45 #define ADUX1020_REG_INT_STATUS 0x49
46 #define ADUX1020_REG_DATA_BUFFER 0x60
47
48 /* Chip ID bits */
49 #define ADUX1020_CHIP_ID_MASK GENMASK(11, 0)
50 #define ADUX1020_CHIP_ID 0x03fc
51
52 #define ADUX1020_SW_RESET BIT(1)
53 #define ADUX1020_FIFO_FLUSH BIT(15)
54 #define ADUX1020_OP_MODE_MASK GENMASK(3, 0)
55 #define ADUX1020_DATA_OUT_MODE_MASK GENMASK(7, 4)
56 #define ADUX1020_DATA_OUT_PROX_I FIELD_PREP(ADUX1020_DATA_OUT_MODE_MASK, 1)
57
58 #define ADUX1020_MODE_INT_MASK GENMASK(7, 0)
59 #define ADUX1020_INT_ENABLE 0x2094
60 #define ADUX1020_INT_DISABLE 0x2090
61 #define ADUX1020_PROX_INT_ENABLE 0x00f0
62 #define ADUX1020_PROX_ON1_INT BIT(0)
63 #define ADUX1020_PROX_OFF1_INT BIT(1)
64 #define ADUX1020_FIFO_INT_ENABLE 0x7f
65 #define ADUX1020_MODE_INT_DISABLE 0xff
66 #define ADUX1020_MODE_INT_STATUS_MASK GENMASK(7, 0)
67 #define ADUX1020_FIFO_STATUS_MASK GENMASK(15, 8)
68 #define ADUX1020_INT_CLEAR 0xff
69 #define ADUX1020_PROX_TYPE BIT(15)
70
71 #define ADUX1020_INT_PROX_ON1 BIT(0)
72 #define ADUX1020_INT_PROX_OFF1 BIT(1)
73
74 #define ADUX1020_FORCE_CLOCK_ON 0x0f4f
75 #define ADUX1020_FORCE_CLOCK_RESET 0x0040
76 #define ADUX1020_ACTIVE_4_STATE 0x0008
77
78 #define ADUX1020_PROX_FREQ_MASK GENMASK(7, 4)
79 #define ADUX1020_PROX_FREQ(x) FIELD_PREP(ADUX1020_PROX_FREQ_MASK, x)
80
81 #define ADUX1020_LED_CURRENT_MASK GENMASK(3, 0)
82 #define ADUX1020_LED_PIREF_EN BIT(12)
83
84 /* Operating modes */
85 enum adux1020_op_modes {
86 ADUX1020_MODE_STANDBY,
87 ADUX1020_MODE_PROX_I,
88 ADUX1020_MODE_PROX_XY,
89 ADUX1020_MODE_GEST,
90 ADUX1020_MODE_SAMPLE,
91 ADUX1020_MODE_FORCE = 0x0e,
92 ADUX1020_MODE_IDLE = 0x0f,
93 };
94
95 struct adux1020_data {
96 struct i2c_client *client;
97 struct iio_dev *indio_dev;
98 struct mutex lock;
99 struct regmap *regmap;
100 };
101
102 struct adux1020_mode_data {
103 u8 bytes;
104 u8 buf_len;
105 u16 int_en;
106 };
107
108 static const struct adux1020_mode_data adux1020_modes[] = {
109 [ADUX1020_MODE_PROX_I] = {
110 .bytes = 2,
111 .buf_len = 1,
112 .int_en = ADUX1020_PROX_INT_ENABLE,
113 },
114 };
115
116 static const struct regmap_config adux1020_regmap_config = {
117 .name = ADUX1020_REGMAP_NAME,
118 .reg_bits = 8,
119 .val_bits = 16,
120 .max_register = 0x6F,
121 .cache_type = REGCACHE_NONE,
122 };
123
124 static const struct reg_sequence adux1020_def_conf[] = {
125 { 0x000c, 0x000f },
126 { 0x0010, 0x1010 },
127 { 0x0011, 0x004c },
128 { 0x0012, 0x5f0c },
129 { 0x0013, 0xada5 },
130 { 0x0014, 0x0080 },
131 { 0x0015, 0x0000 },
132 { 0x0016, 0x0600 },
133 { 0x0017, 0x0000 },
134 { 0x0018, 0x2693 },
135 { 0x0019, 0x0004 },
136 { 0x001a, 0x4280 },
137 { 0x001b, 0x0060 },
138 { 0x001c, 0x2094 },
139 { 0x001d, 0x0020 },
140 { 0x001e, 0x0001 },
141 { 0x001f, 0x0100 },
142 { 0x0020, 0x0320 },
143 { 0x0021, 0x0A13 },
144 { 0x0022, 0x0320 },
145 { 0x0023, 0x0113 },
146 { 0x0024, 0x0000 },
147 { 0x0025, 0x2412 },
148 { 0x0026, 0x2412 },
149 { 0x0027, 0x0022 },
150 { 0x0028, 0x0000 },
151 { 0x0029, 0x0300 },
152 { 0x002a, 0x0700 },
153 { 0x002b, 0x0600 },
154 { 0x002c, 0x6000 },
155 { 0x002d, 0x4000 },
156 { 0x002e, 0x0000 },
157 { 0x002f, 0x0000 },
158 { 0x0030, 0x0000 },
159 { 0x0031, 0x0000 },
160 { 0x0032, 0x0040 },
161 { 0x0033, 0x0008 },
162 { 0x0034, 0xE400 },
163 { 0x0038, 0x8080 },
164 { 0x0039, 0x8080 },
165 { 0x003a, 0x2000 },
166 { 0x003b, 0x1f00 },
167 { 0x003c, 0x2000 },
168 { 0x003d, 0x2000 },
169 { 0x003e, 0x0000 },
170 { 0x0040, 0x8069 },
171 { 0x0041, 0x1f2f },
172 { 0x0042, 0x4000 },
173 { 0x0043, 0x0000 },
174 { 0x0044, 0x0008 },
175 { 0x0046, 0x0000 },
176 { 0x0048, 0x00ef },
177 { 0x0049, 0x0000 },
178 { 0x0045, 0x0000 },
179 };
180
181 static const int adux1020_rates[][2] = {
182 { 0, 100000 },
183 { 0, 200000 },
184 { 0, 500000 },
185 { 1, 0 },
186 { 2, 0 },
187 { 5, 0 },
188 { 10, 0 },
189 { 20, 0 },
190 { 50, 0 },
191 { 100, 0 },
192 { 190, 0 },
193 { 450, 0 },
194 { 820, 0 },
195 { 1400, 0 },
196 };
197
198 static const int adux1020_led_currents[][2] = {
199 { 0, 25000 },
200 { 0, 40000 },
201 { 0, 55000 },
202 { 0, 70000 },
203 { 0, 85000 },
204 { 0, 100000 },
205 { 0, 115000 },
206 { 0, 130000 },
207 { 0, 145000 },
208 { 0, 160000 },
209 { 0, 175000 },
210 { 0, 190000 },
211 { 0, 205000 },
212 { 0, 220000 },
213 { 0, 235000 },
214 { 0, 250000 },
215 };
216
adux1020_flush_fifo(struct adux1020_data * data)217 static int adux1020_flush_fifo(struct adux1020_data *data)
218 {
219 int ret;
220
221 /* Force Idle mode */
222 ret = regmap_write(data->regmap, ADUX1020_REG_FORCE_MODE,
223 ADUX1020_ACTIVE_4_STATE);
224 if (ret < 0)
225 return ret;
226
227 ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
228 ADUX1020_OP_MODE_MASK, ADUX1020_MODE_FORCE);
229 if (ret < 0)
230 return ret;
231
232 ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
233 ADUX1020_OP_MODE_MASK, ADUX1020_MODE_IDLE);
234 if (ret < 0)
235 return ret;
236
237 /* Flush FIFO */
238 ret = regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
239 ADUX1020_FORCE_CLOCK_ON);
240 if (ret < 0)
241 return ret;
242
243 ret = regmap_write(data->regmap, ADUX1020_REG_INT_STATUS,
244 ADUX1020_FIFO_FLUSH);
245 if (ret < 0)
246 return ret;
247
248 return regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
249 ADUX1020_FORCE_CLOCK_RESET);
250 }
251
adux1020_read_fifo(struct adux1020_data * data,u16 * buf,u8 buf_len)252 static int adux1020_read_fifo(struct adux1020_data *data, u16 *buf, u8 buf_len)
253 {
254 unsigned int regval;
255 int i, ret;
256
257 /* Enable 32MHz clock */
258 ret = regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
259 ADUX1020_FORCE_CLOCK_ON);
260 if (ret < 0)
261 return ret;
262
263 for (i = 0; i < buf_len; i++) {
264 ret = regmap_read(data->regmap, ADUX1020_REG_DATA_BUFFER,
265 ®val);
266 if (ret < 0)
267 return ret;
268
269 buf[i] = regval;
270 }
271
272 /* Set 32MHz clock to be controlled by internal state machine */
273 return regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
274 ADUX1020_FORCE_CLOCK_RESET);
275 }
276
adux1020_set_mode(struct adux1020_data * data,enum adux1020_op_modes mode)277 static int adux1020_set_mode(struct adux1020_data *data,
278 enum adux1020_op_modes mode)
279 {
280 int ret;
281
282 /* Switch to standby mode before changing the mode */
283 ret = regmap_write(data->regmap, ADUX1020_REG_OP_MODE,
284 ADUX1020_MODE_STANDBY);
285 if (ret < 0)
286 return ret;
287
288 /* Set data out and switch to the desired mode */
289 switch (mode) {
290 case ADUX1020_MODE_PROX_I:
291 ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
292 ADUX1020_DATA_OUT_MODE_MASK,
293 ADUX1020_DATA_OUT_PROX_I);
294 if (ret < 0)
295 return ret;
296
297 ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
298 ADUX1020_OP_MODE_MASK,
299 ADUX1020_MODE_PROX_I);
300 if (ret < 0)
301 return ret;
302 break;
303 default:
304 return -EINVAL;
305 }
306
307 return 0;
308 }
309
adux1020_measure(struct adux1020_data * data,enum adux1020_op_modes mode,u16 * val)310 static int adux1020_measure(struct adux1020_data *data,
311 enum adux1020_op_modes mode,
312 u16 *val)
313 {
314 unsigned int status;
315 int ret, tries = 50;
316
317 /* Disable INT pin as polling is going to be used */
318 ret = regmap_write(data->regmap, ADUX1020_REG_INT_ENABLE,
319 ADUX1020_INT_DISABLE);
320 if (ret < 0)
321 return ret;
322
323 /* Enable mode interrupt */
324 ret = regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
325 ADUX1020_MODE_INT_MASK,
326 adux1020_modes[mode].int_en);
327 if (ret < 0)
328 return ret;
329
330 while (tries--) {
331 ret = regmap_read(data->regmap, ADUX1020_REG_INT_STATUS,
332 &status);
333 if (ret < 0)
334 return ret;
335
336 status &= ADUX1020_FIFO_STATUS_MASK;
337 if (status >= adux1020_modes[mode].bytes)
338 break;
339 msleep(20);
340 }
341
342 if (tries < 0)
343 return -EIO;
344
345 ret = adux1020_read_fifo(data, val, adux1020_modes[mode].buf_len);
346 if (ret < 0)
347 return ret;
348
349 /* Clear mode interrupt */
350 ret = regmap_write(data->regmap, ADUX1020_REG_INT_STATUS,
351 (~adux1020_modes[mode].int_en));
352 if (ret < 0)
353 return ret;
354
355 /* Disable mode interrupts */
356 return regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
357 ADUX1020_MODE_INT_MASK,
358 ADUX1020_MODE_INT_DISABLE);
359 }
360
adux1020_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)361 static int adux1020_read_raw(struct iio_dev *indio_dev,
362 struct iio_chan_spec const *chan,
363 int *val, int *val2, long mask)
364 {
365 struct adux1020_data *data = iio_priv(indio_dev);
366 u16 buf[3];
367 int ret = -EINVAL;
368 unsigned int regval;
369
370 mutex_lock(&data->lock);
371
372 switch (mask) {
373 case IIO_CHAN_INFO_RAW:
374 switch (chan->type) {
375 case IIO_PROXIMITY:
376 ret = adux1020_set_mode(data, ADUX1020_MODE_PROX_I);
377 if (ret < 0)
378 goto fail;
379
380 ret = adux1020_measure(data, ADUX1020_MODE_PROX_I, buf);
381 if (ret < 0)
382 goto fail;
383
384 *val = buf[0];
385 ret = IIO_VAL_INT;
386 break;
387 default:
388 break;
389 }
390 break;
391 case IIO_CHAN_INFO_PROCESSED:
392 switch (chan->type) {
393 case IIO_CURRENT:
394 ret = regmap_read(data->regmap,
395 ADUX1020_REG_LED_CURRENT, ®val);
396 if (ret < 0)
397 goto fail;
398
399 regval = regval & ADUX1020_LED_CURRENT_MASK;
400
401 *val = adux1020_led_currents[regval][0];
402 *val2 = adux1020_led_currents[regval][1];
403
404 ret = IIO_VAL_INT_PLUS_MICRO;
405 break;
406 default:
407 break;
408 }
409 break;
410 case IIO_CHAN_INFO_SAMP_FREQ:
411 switch (chan->type) {
412 case IIO_PROXIMITY:
413 ret = regmap_read(data->regmap, ADUX1020_REG_FREQUENCY,
414 ®val);
415 if (ret < 0)
416 goto fail;
417
418 regval = FIELD_GET(ADUX1020_PROX_FREQ_MASK, regval);
419
420 *val = adux1020_rates[regval][0];
421 *val2 = adux1020_rates[regval][1];
422
423 ret = IIO_VAL_INT_PLUS_MICRO;
424 break;
425 default:
426 break;
427 }
428 break;
429 default:
430 break;
431 }
432
433 fail:
434 mutex_unlock(&data->lock);
435
436 return ret;
437 };
438
adux1020_find_index(const int array[][2],int count,int val,int val2)439 static inline int adux1020_find_index(const int array[][2], int count, int val,
440 int val2)
441 {
442 int i;
443
444 for (i = 0; i < count; i++)
445 if (val == array[i][0] && val2 == array[i][1])
446 return i;
447
448 return -EINVAL;
449 }
450
adux1020_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)451 static int adux1020_write_raw(struct iio_dev *indio_dev,
452 struct iio_chan_spec const *chan,
453 int val, int val2, long mask)
454 {
455 struct adux1020_data *data = iio_priv(indio_dev);
456 int i, ret = -EINVAL;
457
458 mutex_lock(&data->lock);
459
460 switch (mask) {
461 case IIO_CHAN_INFO_SAMP_FREQ:
462 if (chan->type == IIO_PROXIMITY) {
463 i = adux1020_find_index(adux1020_rates,
464 ARRAY_SIZE(adux1020_rates),
465 val, val2);
466 if (i < 0) {
467 ret = i;
468 goto fail;
469 }
470
471 ret = regmap_update_bits(data->regmap,
472 ADUX1020_REG_FREQUENCY,
473 ADUX1020_PROX_FREQ_MASK,
474 ADUX1020_PROX_FREQ(i));
475 }
476 break;
477 case IIO_CHAN_INFO_PROCESSED:
478 if (chan->type == IIO_CURRENT) {
479 i = adux1020_find_index(adux1020_led_currents,
480 ARRAY_SIZE(adux1020_led_currents),
481 val, val2);
482 if (i < 0) {
483 ret = i;
484 goto fail;
485 }
486
487 ret = regmap_update_bits(data->regmap,
488 ADUX1020_REG_LED_CURRENT,
489 ADUX1020_LED_CURRENT_MASK, i);
490 }
491 break;
492 default:
493 break;
494 }
495
496 fail:
497 mutex_unlock(&data->lock);
498
499 return ret;
500 }
501
adux1020_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)502 static int adux1020_write_event_config(struct iio_dev *indio_dev,
503 const struct iio_chan_spec *chan,
504 enum iio_event_type type,
505 enum iio_event_direction dir, int state)
506 {
507 struct adux1020_data *data = iio_priv(indio_dev);
508 int ret, mask;
509
510 mutex_lock(&data->lock);
511
512 ret = regmap_write(data->regmap, ADUX1020_REG_INT_ENABLE,
513 ADUX1020_INT_ENABLE);
514 if (ret < 0)
515 goto fail;
516
517 ret = regmap_write(data->regmap, ADUX1020_REG_INT_POLARITY, 0);
518 if (ret < 0)
519 goto fail;
520
521 switch (chan->type) {
522 case IIO_PROXIMITY:
523 if (dir == IIO_EV_DIR_RISING)
524 mask = ADUX1020_PROX_ON1_INT;
525 else
526 mask = ADUX1020_PROX_OFF1_INT;
527
528 if (state)
529 state = 0;
530 else
531 state = mask;
532
533 ret = regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
534 mask, state);
535 if (ret < 0)
536 goto fail;
537
538 /*
539 * Trigger proximity interrupt when the intensity is above
540 * or below threshold
541 */
542 ret = regmap_set_bits(data->regmap, ADUX1020_REG_PROX_TYPE,
543 ADUX1020_PROX_TYPE);
544 if (ret < 0)
545 goto fail;
546
547 /* Set proximity mode */
548 ret = adux1020_set_mode(data, ADUX1020_MODE_PROX_I);
549 break;
550 default:
551 ret = -EINVAL;
552 break;
553 }
554
555 fail:
556 mutex_unlock(&data->lock);
557
558 return ret;
559 }
560
adux1020_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)561 static int adux1020_read_event_config(struct iio_dev *indio_dev,
562 const struct iio_chan_spec *chan,
563 enum iio_event_type type,
564 enum iio_event_direction dir)
565 {
566 struct adux1020_data *data = iio_priv(indio_dev);
567 int ret, mask;
568 unsigned int regval;
569
570 switch (chan->type) {
571 case IIO_PROXIMITY:
572 if (dir == IIO_EV_DIR_RISING)
573 mask = ADUX1020_PROX_ON1_INT;
574 else
575 mask = ADUX1020_PROX_OFF1_INT;
576 break;
577 default:
578 return -EINVAL;
579 }
580
581 ret = regmap_read(data->regmap, ADUX1020_REG_INT_MASK, ®val);
582 if (ret < 0)
583 return ret;
584
585 return !(regval & mask);
586 }
587
adux1020_read_thresh(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)588 static int adux1020_read_thresh(struct iio_dev *indio_dev,
589 const struct iio_chan_spec *chan,
590 enum iio_event_type type,
591 enum iio_event_direction dir,
592 enum iio_event_info info, int *val, int *val2)
593 {
594 struct adux1020_data *data = iio_priv(indio_dev);
595 u8 reg;
596 int ret;
597 unsigned int regval;
598
599 switch (chan->type) {
600 case IIO_PROXIMITY:
601 if (dir == IIO_EV_DIR_RISING)
602 reg = ADUX1020_REG_PROX_TH_ON1;
603 else
604 reg = ADUX1020_REG_PROX_TH_OFF1;
605 break;
606 default:
607 return -EINVAL;
608 }
609
610 ret = regmap_read(data->regmap, reg, ®val);
611 if (ret < 0)
612 return ret;
613
614 *val = regval;
615
616 return IIO_VAL_INT;
617 }
618
adux1020_write_thresh(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)619 static int adux1020_write_thresh(struct iio_dev *indio_dev,
620 const struct iio_chan_spec *chan,
621 enum iio_event_type type,
622 enum iio_event_direction dir,
623 enum iio_event_info info, int val, int val2)
624 {
625 struct adux1020_data *data = iio_priv(indio_dev);
626 u8 reg;
627
628 switch (chan->type) {
629 case IIO_PROXIMITY:
630 if (dir == IIO_EV_DIR_RISING)
631 reg = ADUX1020_REG_PROX_TH_ON1;
632 else
633 reg = ADUX1020_REG_PROX_TH_OFF1;
634 break;
635 default:
636 return -EINVAL;
637 }
638
639 /* Full scale threshold value is 0-65535 */
640 if (val < 0 || val > 65535)
641 return -EINVAL;
642
643 return regmap_write(data->regmap, reg, val);
644 }
645
646 static const struct iio_event_spec adux1020_proximity_event[] = {
647 {
648 .type = IIO_EV_TYPE_THRESH,
649 .dir = IIO_EV_DIR_RISING,
650 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
651 BIT(IIO_EV_INFO_ENABLE),
652 },
653 {
654 .type = IIO_EV_TYPE_THRESH,
655 .dir = IIO_EV_DIR_FALLING,
656 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
657 BIT(IIO_EV_INFO_ENABLE),
658 },
659 };
660
661 static const struct iio_chan_spec adux1020_channels[] = {
662 {
663 .type = IIO_PROXIMITY,
664 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
665 BIT(IIO_CHAN_INFO_SAMP_FREQ),
666 .event_spec = adux1020_proximity_event,
667 .num_event_specs = ARRAY_SIZE(adux1020_proximity_event),
668 },
669 {
670 .type = IIO_CURRENT,
671 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
672 .extend_name = "led",
673 .output = 1,
674 },
675 };
676
677 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
678 "0.1 0.2 0.5 1 2 5 10 20 50 100 190 450 820 1400");
679
680 static struct attribute *adux1020_attributes[] = {
681 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
682 NULL
683 };
684
685 static const struct attribute_group adux1020_attribute_group = {
686 .attrs = adux1020_attributes,
687 };
688
689 static const struct iio_info adux1020_info = {
690 .attrs = &adux1020_attribute_group,
691 .read_raw = adux1020_read_raw,
692 .write_raw = adux1020_write_raw,
693 .read_event_config = adux1020_read_event_config,
694 .write_event_config = adux1020_write_event_config,
695 .read_event_value = adux1020_read_thresh,
696 .write_event_value = adux1020_write_thresh,
697 };
698
adux1020_interrupt_handler(int irq,void * private)699 static irqreturn_t adux1020_interrupt_handler(int irq, void *private)
700 {
701 struct iio_dev *indio_dev = private;
702 struct adux1020_data *data = iio_priv(indio_dev);
703 int ret, status;
704
705 ret = regmap_read(data->regmap, ADUX1020_REG_INT_STATUS, &status);
706 if (ret < 0)
707 return IRQ_HANDLED;
708
709 status &= ADUX1020_MODE_INT_STATUS_MASK;
710
711 if (status & ADUX1020_INT_PROX_ON1) {
712 iio_push_event(indio_dev,
713 IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
714 IIO_EV_TYPE_THRESH,
715 IIO_EV_DIR_RISING),
716 iio_get_time_ns(indio_dev));
717 }
718
719 if (status & ADUX1020_INT_PROX_OFF1) {
720 iio_push_event(indio_dev,
721 IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
722 IIO_EV_TYPE_THRESH,
723 IIO_EV_DIR_FALLING),
724 iio_get_time_ns(indio_dev));
725 }
726
727 regmap_update_bits(data->regmap, ADUX1020_REG_INT_STATUS,
728 ADUX1020_MODE_INT_MASK, ADUX1020_INT_CLEAR);
729
730 return IRQ_HANDLED;
731 }
732
adux1020_chip_init(struct adux1020_data * data)733 static int adux1020_chip_init(struct adux1020_data *data)
734 {
735 struct i2c_client *client = data->client;
736 int ret;
737 unsigned int val;
738
739 ret = regmap_read(data->regmap, ADUX1020_REG_CHIP_ID, &val);
740 if (ret < 0)
741 return ret;
742
743 if ((val & ADUX1020_CHIP_ID_MASK) != ADUX1020_CHIP_ID) {
744 dev_err(&client->dev, "invalid chip id 0x%04x\n", val);
745 return -ENODEV;
746 }
747
748 dev_dbg(&client->dev, "Detected ADUX1020 with chip id: 0x%04x\n", val);
749
750 ret = regmap_set_bits(data->regmap, ADUX1020_REG_SW_RESET,
751 ADUX1020_SW_RESET);
752 if (ret < 0)
753 return ret;
754
755 /* Load default configuration */
756 ret = regmap_multi_reg_write(data->regmap, adux1020_def_conf,
757 ARRAY_SIZE(adux1020_def_conf));
758 if (ret < 0)
759 return ret;
760
761 ret = adux1020_flush_fifo(data);
762 if (ret < 0)
763 return ret;
764
765 /* Use LED_IREF for proximity mode */
766 ret = regmap_clear_bits(data->regmap, ADUX1020_REG_LED_CURRENT,
767 ADUX1020_LED_PIREF_EN);
768 if (ret < 0)
769 return ret;
770
771 /* Mask all interrupts */
772 return regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
773 ADUX1020_MODE_INT_MASK, ADUX1020_MODE_INT_DISABLE);
774 }
775
adux1020_probe(struct i2c_client * client)776 static int adux1020_probe(struct i2c_client *client)
777 {
778 struct adux1020_data *data;
779 struct iio_dev *indio_dev;
780 int ret;
781
782 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
783 if (!indio_dev)
784 return -ENOMEM;
785
786 indio_dev->info = &adux1020_info;
787 indio_dev->name = ADUX1020_DRV_NAME;
788 indio_dev->channels = adux1020_channels;
789 indio_dev->num_channels = ARRAY_SIZE(adux1020_channels);
790 indio_dev->modes = INDIO_DIRECT_MODE;
791
792 data = iio_priv(indio_dev);
793
794 data->regmap = devm_regmap_init_i2c(client, &adux1020_regmap_config);
795 if (IS_ERR(data->regmap)) {
796 dev_err(&client->dev, "regmap initialization failed.\n");
797 return PTR_ERR(data->regmap);
798 }
799
800 data->client = client;
801 data->indio_dev = indio_dev;
802 mutex_init(&data->lock);
803
804 ret = adux1020_chip_init(data);
805 if (ret)
806 return ret;
807
808 if (client->irq) {
809 ret = devm_request_threaded_irq(&client->dev, client->irq,
810 NULL, adux1020_interrupt_handler,
811 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
812 ADUX1020_DRV_NAME, indio_dev);
813 if (ret) {
814 dev_err(&client->dev, "irq request error %d\n", -ret);
815 return ret;
816 }
817 }
818
819 return devm_iio_device_register(&client->dev, indio_dev);
820 }
821
822 static const struct i2c_device_id adux1020_id[] = {
823 { "adux1020" },
824 {}
825 };
826 MODULE_DEVICE_TABLE(i2c, adux1020_id);
827
828 static const struct of_device_id adux1020_of_match[] = {
829 { .compatible = "adi,adux1020" },
830 { }
831 };
832 MODULE_DEVICE_TABLE(of, adux1020_of_match);
833
834 static struct i2c_driver adux1020_driver = {
835 .driver = {
836 .name = ADUX1020_DRV_NAME,
837 .of_match_table = adux1020_of_match,
838 },
839 .probe = adux1020_probe,
840 .id_table = adux1020_id,
841 };
842 module_i2c_driver(adux1020_driver);
843
844 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
845 MODULE_DESCRIPTION("ADUX1020 photometric sensor");
846 MODULE_LICENSE("GPL");
847