1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cs_dsp.c -- Cirrus Logic DSP firmware support 4 * 5 * Based on sound/soc/codecs/wm_adsp.c 6 * 7 * Copyright 2012 Wolfson Microelectronics plc 8 * Copyright (C) 2015-2021 Cirrus Logic, Inc. and 9 * Cirrus Logic International Semiconductor Ltd. 10 */ 11 12 #include <kunit/visibility.h> 13 #include <linux/cleanup.h> 14 #include <linux/ctype.h> 15 #include <linux/debugfs.h> 16 #include <linux/delay.h> 17 #include <linux/math.h> 18 #include <linux/minmax.h> 19 #include <linux/module.h> 20 #include <linux/moduleparam.h> 21 #include <linux/seq_file.h> 22 #include <linux/slab.h> 23 #include <linux/vmalloc.h> 24 25 #include <linux/firmware/cirrus/cs_dsp.h> 26 #include <linux/firmware/cirrus/wmfw.h> 27 28 #include "cs_dsp.h" 29 30 /* 31 * When the KUnit test is running the error-case tests will cause a lot 32 * of messages. Rate-limit to prevent overflowing the kernel log buffer 33 * during KUnit test runs. 34 */ 35 #if IS_ENABLED(CONFIG_FW_CS_DSP_KUNIT_TEST) 36 bool cs_dsp_suppress_err_messages; 37 EXPORT_SYMBOL_IF_KUNIT(cs_dsp_suppress_err_messages); 38 39 bool cs_dsp_suppress_warn_messages; 40 EXPORT_SYMBOL_IF_KUNIT(cs_dsp_suppress_warn_messages); 41 42 bool cs_dsp_suppress_info_messages; 43 EXPORT_SYMBOL_IF_KUNIT(cs_dsp_suppress_info_messages); 44 45 #define cs_dsp_err(_dsp, fmt, ...) \ 46 do { \ 47 if (!cs_dsp_suppress_err_messages) \ 48 dev_err_ratelimited(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__); \ 49 } while (false) 50 #define cs_dsp_warn(_dsp, fmt, ...) \ 51 do { \ 52 if (!cs_dsp_suppress_warn_messages) \ 53 dev_warn_ratelimited(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__); \ 54 } while (false) 55 #define cs_dsp_info(_dsp, fmt, ...) \ 56 do { \ 57 if (!cs_dsp_suppress_info_messages) \ 58 dev_info_ratelimited(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__); \ 59 } while (false) 60 #define cs_dsp_dbg(_dsp, fmt, ...) \ 61 dev_dbg_ratelimited(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) 62 #else 63 #define cs_dsp_err(_dsp, fmt, ...) \ 64 dev_err(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) 65 #define cs_dsp_warn(_dsp, fmt, ...) \ 66 dev_warn(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) 67 #define cs_dsp_info(_dsp, fmt, ...) \ 68 dev_info(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) 69 #define cs_dsp_dbg(_dsp, fmt, ...) \ 70 dev_dbg(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) 71 #endif 72 73 #define ADSP1_CONTROL_1 0x00 74 #define ADSP1_CONTROL_2 0x02 75 #define ADSP1_CONTROL_3 0x03 76 #define ADSP1_CONTROL_4 0x04 77 #define ADSP1_CONTROL_5 0x06 78 #define ADSP1_CONTROL_6 0x07 79 #define ADSP1_CONTROL_7 0x08 80 #define ADSP1_CONTROL_8 0x09 81 #define ADSP1_CONTROL_9 0x0A 82 #define ADSP1_CONTROL_10 0x0B 83 #define ADSP1_CONTROL_11 0x0C 84 #define ADSP1_CONTROL_12 0x0D 85 #define ADSP1_CONTROL_13 0x0F 86 #define ADSP1_CONTROL_14 0x10 87 #define ADSP1_CONTROL_15 0x11 88 #define ADSP1_CONTROL_16 0x12 89 #define ADSP1_CONTROL_17 0x13 90 #define ADSP1_CONTROL_18 0x14 91 #define ADSP1_CONTROL_19 0x16 92 #define ADSP1_CONTROL_20 0x17 93 #define ADSP1_CONTROL_21 0x18 94 #define ADSP1_CONTROL_22 0x1A 95 #define ADSP1_CONTROL_23 0x1B 96 #define ADSP1_CONTROL_24 0x1C 97 #define ADSP1_CONTROL_25 0x1E 98 #define ADSP1_CONTROL_26 0x20 99 #define ADSP1_CONTROL_27 0x21 100 #define ADSP1_CONTROL_28 0x22 101 #define ADSP1_CONTROL_29 0x23 102 #define ADSP1_CONTROL_30 0x24 103 #define ADSP1_CONTROL_31 0x26 104 105 /* 106 * ADSP1 Control 19 107 */ 108 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ 109 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ 110 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ 111 112 /* 113 * ADSP1 Control 30 114 */ 115 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */ 116 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */ 117 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */ 118 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */ 119 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ 120 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ 121 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ 122 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ 123 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ 124 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ 125 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ 126 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ 127 #define ADSP1_START 0x0001 /* DSP1_START */ 128 #define ADSP1_START_MASK 0x0001 /* DSP1_START */ 129 #define ADSP1_START_SHIFT 0 /* DSP1_START */ 130 #define ADSP1_START_WIDTH 1 /* DSP1_START */ 131 132 /* 133 * ADSP1 Control 31 134 */ 135 #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */ 136 #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */ 137 #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ 138 139 #define ADSP2_CONTROL 0x0 140 #define ADSP2_CLOCKING 0x1 141 #define ADSP2V2_CLOCKING 0x2 142 #define ADSP2_STATUS1 0x4 143 #define ADSP2_WDMA_CONFIG_1 0x30 144 #define ADSP2_WDMA_CONFIG_2 0x31 145 #define ADSP2V2_WDMA_CONFIG_2 0x32 146 #define ADSP2_RDMA_CONFIG_1 0x34 147 148 #define ADSP2_SCRATCH0 0x40 149 #define ADSP2_SCRATCH1 0x41 150 #define ADSP2_SCRATCH2 0x42 151 #define ADSP2_SCRATCH3 0x43 152 153 #define ADSP2V2_SCRATCH0_1 0x40 154 #define ADSP2V2_SCRATCH2_3 0x42 155 156 /* 157 * ADSP2 Control 158 */ 159 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */ 160 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */ 161 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */ 162 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */ 163 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ 164 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ 165 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ 166 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ 167 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ 168 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ 169 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ 170 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ 171 #define ADSP2_START 0x0001 /* DSP1_START */ 172 #define ADSP2_START_MASK 0x0001 /* DSP1_START */ 173 #define ADSP2_START_SHIFT 0 /* DSP1_START */ 174 #define ADSP2_START_WIDTH 1 /* DSP1_START */ 175 176 /* 177 * ADSP2 clocking 178 */ 179 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */ 180 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */ 181 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ 182 183 /* 184 * ADSP2V2 clocking 185 */ 186 #define ADSP2V2_CLK_SEL_MASK 0x70000 /* CLK_SEL_ENA */ 187 #define ADSP2V2_CLK_SEL_SHIFT 16 /* CLK_SEL_ENA */ 188 #define ADSP2V2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ 189 190 #define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */ 191 #define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */ 192 #define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */ 193 194 /* 195 * ADSP2 Status 1 196 */ 197 #define ADSP2_RAM_RDY 0x0001 198 #define ADSP2_RAM_RDY_MASK 0x0001 199 #define ADSP2_RAM_RDY_SHIFT 0 200 #define ADSP2_RAM_RDY_WIDTH 1 201 202 /* 203 * ADSP2 Lock support 204 */ 205 #define ADSP2_LOCK_CODE_0 0x5555 206 #define ADSP2_LOCK_CODE_1 0xAAAA 207 208 #define ADSP2_WATCHDOG 0x0A 209 #define ADSP2_BUS_ERR_ADDR 0x52 210 #define ADSP2_REGION_LOCK_STATUS 0x64 211 #define ADSP2_LOCK_REGION_1_LOCK_REGION_0 0x66 212 #define ADSP2_LOCK_REGION_3_LOCK_REGION_2 0x68 213 #define ADSP2_LOCK_REGION_5_LOCK_REGION_4 0x6A 214 #define ADSP2_LOCK_REGION_7_LOCK_REGION_6 0x6C 215 #define ADSP2_LOCK_REGION_9_LOCK_REGION_8 0x6E 216 #define ADSP2_LOCK_REGION_CTRL 0x7A 217 #define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x7C 218 219 #define ADSP2_REGION_LOCK_ERR_MASK 0x8000 220 #define ADSP2_ADDR_ERR_MASK 0x4000 221 #define ADSP2_WDT_TIMEOUT_STS_MASK 0x2000 222 #define ADSP2_CTRL_ERR_PAUSE_ENA 0x0002 223 #define ADSP2_CTRL_ERR_EINT 0x0001 224 225 #define ADSP2_BUS_ERR_ADDR_MASK 0x00FFFFFF 226 #define ADSP2_XMEM_ERR_ADDR_MASK 0x0000FFFF 227 #define ADSP2_PMEM_ERR_ADDR_MASK 0x7FFF0000 228 #define ADSP2_PMEM_ERR_ADDR_SHIFT 16 229 #define ADSP2_WDT_ENA_MASK 0xFFFFFFFD 230 231 #define ADSP2_LOCK_REGION_SHIFT 16 232 233 /* 234 * Event control messages 235 */ 236 #define CS_DSP_FW_EVENT_SHUTDOWN 0x000001 237 238 /* 239 * HALO system info 240 */ 241 #define HALO_AHBM_WINDOW_DEBUG_0 0x02040 242 #define HALO_AHBM_WINDOW_DEBUG_1 0x02044 243 244 /* 245 * HALO core 246 */ 247 #define HALO_SCRATCH1 0x005c0 248 #define HALO_SCRATCH2 0x005c8 249 #define HALO_SCRATCH3 0x005d0 250 #define HALO_SCRATCH4 0x005d8 251 #define HALO_CCM_CORE_CONTROL 0x41000 252 #define HALO_CORE_SOFT_RESET 0x00010 253 #define HALO_WDT_CONTROL 0x47000 254 255 /* 256 * HALO MPU banks 257 */ 258 #define HALO_MPU_XMEM_ACCESS_0 0x43000 259 #define HALO_MPU_YMEM_ACCESS_0 0x43004 260 #define HALO_MPU_WINDOW_ACCESS_0 0x43008 261 #define HALO_MPU_XREG_ACCESS_0 0x4300C 262 #define HALO_MPU_YREG_ACCESS_0 0x43014 263 #define HALO_MPU_XMEM_ACCESS_1 0x43018 264 #define HALO_MPU_YMEM_ACCESS_1 0x4301C 265 #define HALO_MPU_WINDOW_ACCESS_1 0x43020 266 #define HALO_MPU_XREG_ACCESS_1 0x43024 267 #define HALO_MPU_YREG_ACCESS_1 0x4302C 268 #define HALO_MPU_XMEM_ACCESS_2 0x43030 269 #define HALO_MPU_YMEM_ACCESS_2 0x43034 270 #define HALO_MPU_WINDOW_ACCESS_2 0x43038 271 #define HALO_MPU_XREG_ACCESS_2 0x4303C 272 #define HALO_MPU_YREG_ACCESS_2 0x43044 273 #define HALO_MPU_XMEM_ACCESS_3 0x43048 274 #define HALO_MPU_YMEM_ACCESS_3 0x4304C 275 #define HALO_MPU_WINDOW_ACCESS_3 0x43050 276 #define HALO_MPU_XREG_ACCESS_3 0x43054 277 #define HALO_MPU_YREG_ACCESS_3 0x4305C 278 #define HALO_MPU_XM_VIO_ADDR 0x43100 279 #define HALO_MPU_XM_VIO_STATUS 0x43104 280 #define HALO_MPU_YM_VIO_ADDR 0x43108 281 #define HALO_MPU_YM_VIO_STATUS 0x4310C 282 #define HALO_MPU_PM_VIO_ADDR 0x43110 283 #define HALO_MPU_PM_VIO_STATUS 0x43114 284 #define HALO_MPU_LOCK_CONFIG 0x43140 285 286 /* 287 * HALO_AHBM_WINDOW_DEBUG_1 288 */ 289 #define HALO_AHBM_CORE_ERR_ADDR_MASK 0x0fffff00 290 #define HALO_AHBM_CORE_ERR_ADDR_SHIFT 8 291 #define HALO_AHBM_FLAGS_ERR_MASK 0x000000ff 292 293 /* 294 * HALO_CCM_CORE_CONTROL 295 */ 296 #define HALO_CORE_RESET 0x00000200 297 #define HALO_CORE_EN 0x00000001 298 299 /* 300 * HALO_CORE_SOFT_RESET 301 */ 302 #define HALO_CORE_SOFT_RESET_MASK 0x00000001 303 304 /* 305 * HALO_WDT_CONTROL 306 */ 307 #define HALO_WDT_EN_MASK 0x00000001 308 309 /* 310 * HALO_MPU_?M_VIO_STATUS 311 */ 312 #define HALO_MPU_VIO_STS_MASK 0x007e0000 313 #define HALO_MPU_VIO_STS_SHIFT 17 314 #define HALO_MPU_VIO_ERR_WR_MASK 0x00008000 315 #define HALO_MPU_VIO_ERR_SRC_MASK 0x00007fff 316 #define HALO_MPU_VIO_ERR_SRC_SHIFT 0 317 318 /* 319 * Write Sequence 320 */ 321 #define WSEQ_OP_MAX_WORDS 3 322 #define WSEQ_END_OF_SCRIPT 0xFFFFFF 323 324 struct cs_dsp_ops { 325 bool (*validate_version)(struct cs_dsp *dsp, unsigned int version); 326 unsigned int (*parse_sizes)(struct cs_dsp *dsp, 327 const char * const file, 328 unsigned int pos, 329 const struct firmware *firmware); 330 int (*setup_algs)(struct cs_dsp *dsp); 331 unsigned int (*region_to_reg)(struct cs_dsp_region const *mem, 332 unsigned int offset); 333 334 void (*show_fw_status)(struct cs_dsp *dsp); 335 void (*stop_watchdog)(struct cs_dsp *dsp); 336 337 int (*enable_memory)(struct cs_dsp *dsp); 338 void (*disable_memory)(struct cs_dsp *dsp); 339 int (*lock_memory)(struct cs_dsp *dsp, unsigned int lock_regions); 340 341 int (*enable_core)(struct cs_dsp *dsp); 342 void (*disable_core)(struct cs_dsp *dsp); 343 344 int (*start_core)(struct cs_dsp *dsp); 345 void (*stop_core)(struct cs_dsp *dsp); 346 }; 347 348 static const struct cs_dsp_ops cs_dsp_adsp1_ops; 349 static const struct cs_dsp_ops cs_dsp_adsp2_ops[]; 350 static const struct cs_dsp_ops cs_dsp_halo_ops; 351 static const struct cs_dsp_ops cs_dsp_halo_ao_ops; 352 353 struct cs_dsp_alg_region_list_item { 354 struct list_head list; 355 struct cs_dsp_alg_region alg_region; 356 }; 357 358 /** 359 * cs_dsp_mem_region_name() - Return a name string for a memory type 360 * @type: the memory type to match 361 * 362 * Return: A const string identifying the memory region. 363 */ 364 const char *cs_dsp_mem_region_name(unsigned int type) 365 { 366 switch (type) { 367 case WMFW_ADSP1_PM: 368 return "PM"; 369 case WMFW_HALO_PM_PACKED: 370 return "PM_PACKED"; 371 case WMFW_ADSP1_DM: 372 return "DM"; 373 case WMFW_ADSP2_XM: 374 return "XM"; 375 case WMFW_HALO_XM_PACKED: 376 return "XM_PACKED"; 377 case WMFW_ADSP2_YM: 378 return "YM"; 379 case WMFW_HALO_YM_PACKED: 380 return "YM_PACKED"; 381 case WMFW_ADSP1_ZM: 382 return "ZM"; 383 default: 384 return NULL; 385 } 386 } 387 EXPORT_SYMBOL_NS_GPL(cs_dsp_mem_region_name, "FW_CS_DSP"); 388 389 #ifdef CONFIG_DEBUG_FS 390 static void cs_dsp_debugfs_save_wmfwname(struct cs_dsp *dsp, const char *s) 391 { 392 kfree(dsp->wmfw_file_name); 393 dsp->wmfw_file_name = kstrdup(s, GFP_KERNEL); 394 } 395 396 static void cs_dsp_debugfs_save_binname(struct cs_dsp *dsp, const char *s) 397 { 398 kfree(dsp->bin_file_name); 399 dsp->bin_file_name = kstrdup(s, GFP_KERNEL); 400 } 401 402 static void cs_dsp_debugfs_clear(struct cs_dsp *dsp) 403 { 404 kfree(dsp->wmfw_file_name); 405 kfree(dsp->bin_file_name); 406 dsp->wmfw_file_name = NULL; 407 dsp->bin_file_name = NULL; 408 } 409 410 static ssize_t cs_dsp_debugfs_string_read(struct cs_dsp *dsp, 411 char __user *user_buf, 412 size_t count, loff_t *ppos, 413 const char **pstr) 414 { 415 const char *str; 416 ssize_t ret = 0; 417 418 scoped_guard(mutex, &dsp->pwr_lock) { 419 if (*pstr) { 420 str = kasprintf(GFP_KERNEL, "%s\n", *pstr); 421 if (str) { 422 ret = simple_read_from_buffer(user_buf, count, 423 ppos, str, strlen(str)); 424 kfree(str); 425 } else { 426 ret = -ENOMEM; 427 } 428 } 429 } 430 431 return ret; 432 } 433 434 static ssize_t cs_dsp_debugfs_wmfw_read(struct file *file, 435 char __user *user_buf, 436 size_t count, loff_t *ppos) 437 { 438 struct cs_dsp *dsp = file->private_data; 439 440 return cs_dsp_debugfs_string_read(dsp, user_buf, count, ppos, 441 &dsp->wmfw_file_name); 442 } 443 444 static ssize_t cs_dsp_debugfs_bin_read(struct file *file, 445 char __user *user_buf, 446 size_t count, loff_t *ppos) 447 { 448 struct cs_dsp *dsp = file->private_data; 449 450 return cs_dsp_debugfs_string_read(dsp, user_buf, count, ppos, 451 &dsp->bin_file_name); 452 } 453 454 static const struct { 455 const char *name; 456 const struct file_operations fops; 457 } cs_dsp_debugfs_fops[] = { 458 { 459 .name = "wmfw_file_name", 460 .fops = { 461 .open = simple_open, 462 .read = cs_dsp_debugfs_wmfw_read, 463 }, 464 }, 465 { 466 .name = "bin_file_name", 467 .fops = { 468 .open = simple_open, 469 .read = cs_dsp_debugfs_bin_read, 470 }, 471 }, 472 }; 473 474 static int cs_dsp_coeff_base_reg(struct cs_dsp_coeff_ctl *ctl, unsigned int *reg, 475 unsigned int off); 476 477 static int cs_dsp_debugfs_read_controls_show(struct seq_file *s, void *ignored) 478 { 479 struct cs_dsp *dsp = s->private; 480 struct cs_dsp_coeff_ctl *ctl; 481 unsigned int reg; 482 483 guard(mutex)(&dsp->pwr_lock); 484 485 list_for_each_entry(ctl, &dsp->ctl_list, list) { 486 cs_dsp_coeff_base_reg(ctl, ®, 0); 487 seq_printf(s, "%22.*s: %#8x %s:%08x %#8x %s %#8x %#4x %c%c%c%c %s %s\n", 488 ctl->subname_len, ctl->subname, ctl->len, 489 cs_dsp_mem_region_name(ctl->alg_region.type), 490 ctl->offset, reg, ctl->fw_name, ctl->alg_region.alg, ctl->type, 491 ctl->flags & WMFW_CTL_FLAG_VOLATILE ? 'V' : '-', 492 ctl->flags & WMFW_CTL_FLAG_SYS ? 'S' : '-', 493 ctl->flags & WMFW_CTL_FLAG_READABLE ? 'R' : '-', 494 ctl->flags & WMFW_CTL_FLAG_WRITEABLE ? 'W' : '-', 495 ctl->enabled ? "enabled" : "disabled", 496 ctl->set ? "dirty" : "clean"); 497 } 498 499 return 0; 500 } 501 DEFINE_SHOW_ATTRIBUTE(cs_dsp_debugfs_read_controls); 502 503 /** 504 * cs_dsp_init_debugfs() - Create and populate DSP representation in debugfs 505 * @dsp: pointer to DSP structure 506 * @debugfs_root: pointer to debugfs directory in which to create this DSP 507 * representation 508 */ 509 void cs_dsp_init_debugfs(struct cs_dsp *dsp, struct dentry *debugfs_root) 510 { 511 struct dentry *root = NULL; 512 int i; 513 514 root = debugfs_create_dir(dsp->name, debugfs_root); 515 516 debugfs_create_bool("booted", 0444, root, &dsp->booted); 517 debugfs_create_bool("running", 0444, root, &dsp->running); 518 debugfs_create_x32("fw_id", 0444, root, &dsp->fw_id); 519 debugfs_create_x32("fw_version", 0444, root, &dsp->fw_id_version); 520 521 for (i = 0; i < ARRAY_SIZE(cs_dsp_debugfs_fops); ++i) 522 debugfs_create_file(cs_dsp_debugfs_fops[i].name, 0444, root, 523 dsp, &cs_dsp_debugfs_fops[i].fops); 524 525 debugfs_create_file("controls", 0444, root, dsp, 526 &cs_dsp_debugfs_read_controls_fops); 527 528 dsp->debugfs_root = root; 529 } 530 EXPORT_SYMBOL_NS_GPL(cs_dsp_init_debugfs, "FW_CS_DSP"); 531 532 /** 533 * cs_dsp_cleanup_debugfs() - Removes DSP representation from debugfs 534 * @dsp: pointer to DSP structure 535 */ 536 void cs_dsp_cleanup_debugfs(struct cs_dsp *dsp) 537 { 538 cs_dsp_debugfs_clear(dsp); 539 debugfs_remove_recursive(dsp->debugfs_root); 540 dsp->debugfs_root = ERR_PTR(-ENODEV); 541 } 542 EXPORT_SYMBOL_NS_GPL(cs_dsp_cleanup_debugfs, "FW_CS_DSP"); 543 #else 544 void cs_dsp_init_debugfs(struct cs_dsp *dsp, struct dentry *debugfs_root) 545 { 546 } 547 EXPORT_SYMBOL_NS_GPL(cs_dsp_init_debugfs, "FW_CS_DSP"); 548 549 void cs_dsp_cleanup_debugfs(struct cs_dsp *dsp) 550 { 551 } 552 EXPORT_SYMBOL_NS_GPL(cs_dsp_cleanup_debugfs, "FW_CS_DSP"); 553 554 static inline void cs_dsp_debugfs_save_wmfwname(struct cs_dsp *dsp, 555 const char *s) 556 { 557 } 558 559 static inline void cs_dsp_debugfs_save_binname(struct cs_dsp *dsp, 560 const char *s) 561 { 562 } 563 564 static inline void cs_dsp_debugfs_clear(struct cs_dsp *dsp) 565 { 566 } 567 #endif 568 569 static const struct cs_dsp_region *cs_dsp_find_region(struct cs_dsp *dsp, 570 int type) 571 { 572 int i; 573 574 for (i = 0; i < dsp->num_mems; i++) 575 if (dsp->mem[i].type == type) 576 return &dsp->mem[i]; 577 578 return NULL; 579 } 580 581 static unsigned int cs_dsp_region_to_reg(struct cs_dsp_region const *mem, 582 unsigned int offset) 583 { 584 switch (mem->type) { 585 case WMFW_ADSP1_PM: 586 return mem->base + (offset * 3); 587 case WMFW_ADSP1_DM: 588 case WMFW_ADSP2_XM: 589 case WMFW_ADSP2_YM: 590 case WMFW_ADSP1_ZM: 591 return mem->base + (offset * 2); 592 default: 593 WARN(1, "Unknown memory region type"); 594 return offset; 595 } 596 } 597 598 static unsigned int cs_dsp_halo_region_to_reg(struct cs_dsp_region const *mem, 599 unsigned int offset) 600 { 601 switch (mem->type) { 602 case WMFW_ADSP2_XM: 603 case WMFW_ADSP2_YM: 604 return mem->base + (offset * 4); 605 case WMFW_HALO_XM_PACKED: 606 case WMFW_HALO_YM_PACKED: 607 return (mem->base + (offset * 3)) & ~0x3; 608 case WMFW_HALO_PM_PACKED: 609 return mem->base + (offset * 5); 610 default: 611 WARN(1, "Unknown memory region type"); 612 return offset; 613 } 614 } 615 616 static void cs_dsp_read_fw_status(struct cs_dsp *dsp, 617 int noffs, unsigned int *offs) 618 { 619 unsigned int i; 620 int ret; 621 622 for (i = 0; i < noffs; ++i) { 623 ret = regmap_read(dsp->regmap, dsp->base + offs[i], &offs[i]); 624 if (ret) { 625 cs_dsp_err(dsp, "Failed to read SCRATCH%u: %d\n", i, ret); 626 return; 627 } 628 } 629 } 630 631 static void cs_dsp_adsp2_show_fw_status(struct cs_dsp *dsp) 632 { 633 unsigned int offs[] = { 634 ADSP2_SCRATCH0, ADSP2_SCRATCH1, ADSP2_SCRATCH2, ADSP2_SCRATCH3, 635 }; 636 637 cs_dsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); 638 639 cs_dsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", 640 offs[0], offs[1], offs[2], offs[3]); 641 } 642 643 static void cs_dsp_adsp2v2_show_fw_status(struct cs_dsp *dsp) 644 { 645 unsigned int offs[] = { ADSP2V2_SCRATCH0_1, ADSP2V2_SCRATCH2_3 }; 646 647 cs_dsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); 648 649 cs_dsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", 650 offs[0] & 0xFFFF, offs[0] >> 16, 651 offs[1] & 0xFFFF, offs[1] >> 16); 652 } 653 654 static void cs_dsp_halo_show_fw_status(struct cs_dsp *dsp) 655 { 656 unsigned int offs[] = { 657 HALO_SCRATCH1, HALO_SCRATCH2, HALO_SCRATCH3, HALO_SCRATCH4, 658 }; 659 660 cs_dsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); 661 662 cs_dsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", 663 offs[0], offs[1], offs[2], offs[3]); 664 } 665 666 static int cs_dsp_coeff_base_reg(struct cs_dsp_coeff_ctl *ctl, unsigned int *reg, 667 unsigned int off) 668 { 669 const struct cs_dsp_alg_region *alg_region = &ctl->alg_region; 670 struct cs_dsp *dsp = ctl->dsp; 671 const struct cs_dsp_region *mem; 672 673 mem = cs_dsp_find_region(dsp, alg_region->type); 674 if (!mem) { 675 cs_dsp_err(dsp, "No base for region %x\n", 676 alg_region->type); 677 return -EINVAL; 678 } 679 680 *reg = dsp->ops->region_to_reg(mem, ctl->alg_region.base + ctl->offset + off); 681 682 return 0; 683 } 684 685 /** 686 * cs_dsp_coeff_write_acked_control() - Sends event_id to the acked control 687 * @ctl: pointer to acked coefficient control 688 * @event_id: the value to write to the given acked control 689 * 690 * Once the value has been written to the control the function shall block 691 * until the running firmware acknowledges the write or timeout is exceeded. 692 * 693 * Must be called with pwr_lock held. 694 * 695 * Return: Zero for success, a negative number on error. 696 */ 697 int cs_dsp_coeff_write_acked_control(struct cs_dsp_coeff_ctl *ctl, unsigned int event_id) 698 { 699 struct cs_dsp *dsp = ctl->dsp; 700 __be32 val = cpu_to_be32(event_id); 701 unsigned int reg; 702 int i, ret; 703 704 lockdep_assert_held(&dsp->pwr_lock); 705 706 if (!dsp->running) 707 return -EPERM; 708 709 ret = cs_dsp_coeff_base_reg(ctl, ®, 0); 710 if (ret) 711 return ret; 712 713 cs_dsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n", 714 event_id, ctl->alg_region.alg, 715 cs_dsp_mem_region_name(ctl->alg_region.type), ctl->offset); 716 717 ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val)); 718 if (ret) { 719 cs_dsp_err(dsp, "Failed to write %x: %d\n", reg, ret); 720 return ret; 721 } 722 723 /* 724 * Poll for ack, we initially poll at ~1ms intervals for firmwares 725 * that respond quickly, then go to ~10ms polls. A firmware is unlikely 726 * to ack instantly so we do the first 1ms delay before reading the 727 * control to avoid a pointless bus transaction 728 */ 729 for (i = 0; i < CS_DSP_ACKED_CTL_TIMEOUT_MS;) { 730 switch (i) { 731 case 0 ... CS_DSP_ACKED_CTL_N_QUICKPOLLS - 1: 732 usleep_range(1000, 2000); 733 i++; 734 break; 735 default: 736 usleep_range(10000, 20000); 737 i += 10; 738 break; 739 } 740 741 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); 742 if (ret) { 743 cs_dsp_err(dsp, "Failed to read %x: %d\n", reg, ret); 744 return ret; 745 } 746 747 if (val == 0) { 748 cs_dsp_dbg(dsp, "Acked control ACKED at poll %u\n", i); 749 return 0; 750 } 751 } 752 753 cs_dsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n", 754 reg, ctl->alg_region.alg, 755 cs_dsp_mem_region_name(ctl->alg_region.type), 756 ctl->offset); 757 758 return -ETIMEDOUT; 759 } 760 EXPORT_SYMBOL_NS_GPL(cs_dsp_coeff_write_acked_control, "FW_CS_DSP"); 761 762 static int cs_dsp_coeff_write_ctrl_raw(struct cs_dsp_coeff_ctl *ctl, 763 unsigned int off, const void *buf, size_t len) 764 { 765 struct cs_dsp *dsp = ctl->dsp; 766 void *scratch; 767 int ret; 768 unsigned int reg; 769 770 ret = cs_dsp_coeff_base_reg(ctl, ®, off); 771 if (ret) 772 return ret; 773 774 scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA); 775 if (!scratch) 776 return -ENOMEM; 777 778 ret = regmap_raw_write(dsp->regmap, reg, scratch, 779 len); 780 if (ret) { 781 cs_dsp_err(dsp, "Failed to write %zu bytes to %x: %d\n", 782 len, reg, ret); 783 kfree(scratch); 784 return ret; 785 } 786 cs_dsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg); 787 788 kfree(scratch); 789 790 return 0; 791 } 792 793 /** 794 * cs_dsp_coeff_write_ctrl() - Writes the given buffer to the given coefficient control 795 * @ctl: pointer to coefficient control 796 * @off: word offset at which data should be written 797 * @buf: the buffer to write to the given control 798 * @len: the length of the buffer in bytes 799 * 800 * Must be called with pwr_lock held. 801 * 802 * Return: < 0 on error, 1 when the control value changed and 0 when it has not. 803 */ 804 int cs_dsp_coeff_write_ctrl(struct cs_dsp_coeff_ctl *ctl, 805 unsigned int off, const void *buf, size_t len) 806 { 807 int ret = 0; 808 809 if (!ctl) 810 return -ENOENT; 811 812 lockdep_assert_held(&ctl->dsp->pwr_lock); 813 814 if (ctl->flags && !(ctl->flags & WMFW_CTL_FLAG_WRITEABLE)) 815 return -EPERM; 816 817 if (len + off * sizeof(u32) > ctl->len) 818 return -EINVAL; 819 820 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) { 821 ret = -EPERM; 822 } else if (buf != ctl->cache) { 823 if (memcmp(ctl->cache + off * sizeof(u32), buf, len)) 824 memcpy(ctl->cache + off * sizeof(u32), buf, len); 825 else 826 return 0; 827 } 828 829 ctl->set = 1; 830 if (ctl->enabled && ctl->dsp->running) 831 ret = cs_dsp_coeff_write_ctrl_raw(ctl, off, buf, len); 832 833 if (ret < 0) 834 return ret; 835 836 return 1; 837 } 838 EXPORT_SYMBOL_NS_GPL(cs_dsp_coeff_write_ctrl, "FW_CS_DSP"); 839 840 /** 841 * cs_dsp_coeff_lock_and_write_ctrl() - Writes the given buffer to the given coefficient control 842 * @ctl: pointer to coefficient control 843 * @off: word offset at which data should be written 844 * @buf: the buffer to write to the given control 845 * @len: the length of the buffer in bytes 846 * 847 * Same as cs_dsp_coeff_write_ctrl() but takes pwr_lock. 848 * 849 * Return: A negative number on error, 1 when the control value changed and 0 when it has not. 850 */ 851 int cs_dsp_coeff_lock_and_write_ctrl(struct cs_dsp_coeff_ctl *ctl, 852 unsigned int off, const void *buf, size_t len) 853 { 854 struct cs_dsp *dsp = ctl->dsp; 855 int ret; 856 857 lockdep_assert_not_held(&dsp->pwr_lock); 858 859 mutex_lock(&dsp->pwr_lock); 860 ret = cs_dsp_coeff_write_ctrl(ctl, off, buf, len); 861 mutex_unlock(&dsp->pwr_lock); 862 863 return ret; 864 } 865 EXPORT_SYMBOL_GPL(cs_dsp_coeff_lock_and_write_ctrl); 866 867 static int cs_dsp_coeff_read_ctrl_raw(struct cs_dsp_coeff_ctl *ctl, 868 unsigned int off, void *buf, size_t len) 869 { 870 struct cs_dsp *dsp = ctl->dsp; 871 void *scratch; 872 int ret; 873 unsigned int reg; 874 875 ret = cs_dsp_coeff_base_reg(ctl, ®, off); 876 if (ret) 877 return ret; 878 879 scratch = kmalloc(len, GFP_KERNEL | GFP_DMA); 880 if (!scratch) 881 return -ENOMEM; 882 883 ret = regmap_raw_read(dsp->regmap, reg, scratch, len); 884 if (ret) { 885 cs_dsp_err(dsp, "Failed to read %zu bytes from %x: %d\n", 886 len, reg, ret); 887 kfree(scratch); 888 return ret; 889 } 890 cs_dsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg); 891 892 memcpy(buf, scratch, len); 893 kfree(scratch); 894 895 return 0; 896 } 897 898 /** 899 * cs_dsp_coeff_read_ctrl() - Reads the given coefficient control into the given buffer 900 * @ctl: pointer to coefficient control 901 * @off: word offset at which data should be read 902 * @buf: the buffer to store to the given control 903 * @len: the length of the buffer in bytes 904 * 905 * Must be called with pwr_lock held. 906 * 907 * Return: Zero for success, a negative number on error. 908 */ 909 int cs_dsp_coeff_read_ctrl(struct cs_dsp_coeff_ctl *ctl, 910 unsigned int off, void *buf, size_t len) 911 { 912 int ret = 0; 913 914 if (!ctl) 915 return -ENOENT; 916 917 lockdep_assert_held(&ctl->dsp->pwr_lock); 918 919 if (len + off * sizeof(u32) > ctl->len) 920 return -EINVAL; 921 922 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) { 923 if (ctl->enabled && ctl->dsp->running) 924 return cs_dsp_coeff_read_ctrl_raw(ctl, off, buf, len); 925 else 926 return -EPERM; 927 } else { 928 if (!ctl->flags && ctl->enabled && ctl->dsp->running) 929 ret = cs_dsp_coeff_read_ctrl_raw(ctl, 0, ctl->cache, ctl->len); 930 931 if (buf != ctl->cache) 932 memcpy(buf, ctl->cache + off * sizeof(u32), len); 933 } 934 935 return ret; 936 } 937 EXPORT_SYMBOL_NS_GPL(cs_dsp_coeff_read_ctrl, "FW_CS_DSP"); 938 939 /** 940 * cs_dsp_coeff_lock_and_read_ctrl() - Reads the given coefficient control into the given buffer 941 * @ctl: pointer to coefficient control 942 * @off: word offset at which data should be read 943 * @buf: the buffer to store to the given control 944 * @len: the length of the buffer in bytes 945 * 946 * Same as cs_dsp_coeff_read_ctrl() but takes pwr_lock. 947 * 948 * Return: Zero for success, a negative number on error. 949 */ 950 int cs_dsp_coeff_lock_and_read_ctrl(struct cs_dsp_coeff_ctl *ctl, 951 unsigned int off, void *buf, size_t len) 952 { 953 struct cs_dsp *dsp = ctl->dsp; 954 int ret; 955 956 lockdep_assert_not_held(&dsp->pwr_lock); 957 958 mutex_lock(&dsp->pwr_lock); 959 ret = cs_dsp_coeff_read_ctrl(ctl, off, buf, len); 960 mutex_unlock(&dsp->pwr_lock); 961 962 return ret; 963 } 964 EXPORT_SYMBOL_GPL(cs_dsp_coeff_lock_and_read_ctrl); 965 966 static int cs_dsp_coeff_init_control_caches(struct cs_dsp *dsp) 967 { 968 struct cs_dsp_coeff_ctl *ctl; 969 int ret; 970 971 list_for_each_entry(ctl, &dsp->ctl_list, list) { 972 if (!ctl->enabled || ctl->set) 973 continue; 974 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) 975 continue; 976 977 /* 978 * For readable controls populate the cache from the DSP memory. 979 * For non-readable controls the cache was zero-filled when 980 * created so we don't need to do anything. 981 */ 982 if (!ctl->flags || (ctl->flags & WMFW_CTL_FLAG_READABLE)) { 983 ret = cs_dsp_coeff_read_ctrl_raw(ctl, 0, ctl->cache, ctl->len); 984 if (ret < 0) 985 return ret; 986 } 987 } 988 989 return 0; 990 } 991 992 static int cs_dsp_coeff_sync_controls(struct cs_dsp *dsp) 993 { 994 struct cs_dsp_coeff_ctl *ctl; 995 int ret; 996 997 list_for_each_entry(ctl, &dsp->ctl_list, list) { 998 if (!ctl->enabled) 999 continue; 1000 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) { 1001 ret = cs_dsp_coeff_write_ctrl_raw(ctl, 0, ctl->cache, 1002 ctl->len); 1003 if (ret < 0) 1004 return ret; 1005 } 1006 } 1007 1008 return 0; 1009 } 1010 1011 static void cs_dsp_signal_event_controls(struct cs_dsp *dsp, 1012 unsigned int event) 1013 { 1014 struct cs_dsp_coeff_ctl *ctl; 1015 int ret; 1016 1017 list_for_each_entry(ctl, &dsp->ctl_list, list) { 1018 if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT) 1019 continue; 1020 1021 if (!ctl->enabled) 1022 continue; 1023 1024 ret = cs_dsp_coeff_write_acked_control(ctl, event); 1025 if (ret) 1026 cs_dsp_warn(dsp, 1027 "Failed to send 0x%x event to alg 0x%x (%d)\n", 1028 event, ctl->alg_region.alg, ret); 1029 } 1030 } 1031 1032 static void cs_dsp_free_ctl_blk(struct cs_dsp_coeff_ctl *ctl) 1033 { 1034 kvfree(ctl->cache); 1035 kfree(ctl->subname); 1036 kfree(ctl); 1037 } 1038 1039 static int cs_dsp_create_control(struct cs_dsp *dsp, 1040 const struct cs_dsp_alg_region *alg_region, 1041 unsigned int offset, unsigned int len, 1042 const char *subname, unsigned int subname_len, 1043 unsigned int flags, unsigned int type) 1044 { 1045 struct cs_dsp_coeff_ctl *ctl; 1046 int ret; 1047 1048 list_for_each_entry(ctl, &dsp->ctl_list, list) { 1049 if (ctl->fw_name == dsp->fw_name && 1050 ctl->alg_region.alg == alg_region->alg && 1051 ctl->alg_region.type == alg_region->type) { 1052 if ((!subname && !ctl->subname) || 1053 (subname && (ctl->subname_len == subname_len) && 1054 !strncmp(ctl->subname, subname, ctl->subname_len))) { 1055 if (!ctl->enabled) 1056 ctl->enabled = 1; 1057 return 0; 1058 } 1059 } 1060 } 1061 1062 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL); 1063 if (!ctl) 1064 return -ENOMEM; 1065 1066 ctl->fw_name = dsp->fw_name; 1067 ctl->alg_region = *alg_region; 1068 if (subname && dsp->wmfw_ver >= 2) { 1069 ctl->subname_len = subname_len; 1070 ctl->subname = kasprintf(GFP_KERNEL, "%.*s", subname_len, subname); 1071 if (!ctl->subname) { 1072 ret = -ENOMEM; 1073 goto err_ctl; 1074 } 1075 } 1076 ctl->enabled = 1; 1077 ctl->set = 0; 1078 ctl->dsp = dsp; 1079 1080 ctl->flags = flags; 1081 ctl->type = type; 1082 ctl->offset = offset; 1083 ctl->len = len; 1084 ctl->cache = kvzalloc(ctl->len, GFP_KERNEL); 1085 if (!ctl->cache) { 1086 ret = -ENOMEM; 1087 goto err_ctl_subname; 1088 } 1089 1090 list_add(&ctl->list, &dsp->ctl_list); 1091 1092 if (dsp->client_ops->control_add) { 1093 ret = dsp->client_ops->control_add(ctl); 1094 if (ret) 1095 goto err_list_del; 1096 } 1097 1098 return 0; 1099 1100 err_list_del: 1101 list_del(&ctl->list); 1102 kvfree(ctl->cache); 1103 err_ctl_subname: 1104 kfree(ctl->subname); 1105 err_ctl: 1106 kfree(ctl); 1107 1108 return ret; 1109 } 1110 1111 struct cs_dsp_coeff_parsed_alg { 1112 int id; 1113 const u8 *name; 1114 int name_len; 1115 int ncoeff; 1116 }; 1117 1118 struct cs_dsp_coeff_parsed_coeff { 1119 int offset; 1120 int mem_type; 1121 const u8 *name; 1122 int name_len; 1123 unsigned int ctl_type; 1124 int flags; 1125 int len; 1126 }; 1127 1128 static int cs_dsp_coeff_parse_string(int bytes, const u8 **pos, unsigned int avail, 1129 const u8 **str) 1130 { 1131 int length, total_field_len; 1132 1133 /* String fields are at least one __le32 */ 1134 if (sizeof(__le32) > avail) { 1135 *pos = NULL; 1136 return 0; 1137 } 1138 1139 switch (bytes) { 1140 case 1: 1141 length = **pos; 1142 break; 1143 case 2: 1144 length = le16_to_cpu(*((__le16 *)*pos)); 1145 break; 1146 default: 1147 return 0; 1148 } 1149 1150 total_field_len = ((length + bytes) + 3) & ~0x03; 1151 if ((unsigned int)total_field_len > avail) { 1152 *pos = NULL; 1153 return 0; 1154 } 1155 1156 if (str) 1157 *str = *pos + bytes; 1158 1159 *pos += total_field_len; 1160 1161 return length; 1162 } 1163 1164 static int cs_dsp_coeff_parse_int(int bytes, const u8 **pos) 1165 { 1166 int val = 0; 1167 1168 switch (bytes) { 1169 case 2: 1170 val = le16_to_cpu(*((__le16 *)*pos)); 1171 break; 1172 case 4: 1173 val = le32_to_cpu(*((__le32 *)*pos)); 1174 break; 1175 default: 1176 break; 1177 } 1178 1179 *pos += bytes; 1180 1181 return val; 1182 } 1183 1184 static int cs_dsp_coeff_parse_alg(struct cs_dsp *dsp, 1185 const struct wmfw_region *region, 1186 struct cs_dsp_coeff_parsed_alg *blk) 1187 { 1188 const struct wmfw_adsp_alg_data *raw; 1189 unsigned int data_len = le32_to_cpu(region->len); 1190 unsigned int pos; 1191 const u8 *tmp; 1192 1193 raw = (const struct wmfw_adsp_alg_data *)region->data; 1194 1195 switch (dsp->wmfw_ver) { 1196 case 0: 1197 case 1: 1198 if (sizeof(*raw) > data_len) 1199 return -EOVERFLOW; 1200 1201 blk->id = le32_to_cpu(raw->id); 1202 blk->name = raw->name; 1203 blk->name_len = strnlen(raw->name, ARRAY_SIZE(raw->name)); 1204 blk->ncoeff = le32_to_cpu(raw->ncoeff); 1205 1206 pos = sizeof(*raw); 1207 break; 1208 default: 1209 if (sizeof(raw->id) > data_len) 1210 return -EOVERFLOW; 1211 1212 tmp = region->data; 1213 blk->id = cs_dsp_coeff_parse_int(sizeof(raw->id), &tmp); 1214 pos = tmp - region->data; 1215 1216 tmp = ®ion->data[pos]; 1217 blk->name_len = cs_dsp_coeff_parse_string(sizeof(u8), &tmp, data_len - pos, 1218 &blk->name); 1219 if (!tmp) 1220 return -EOVERFLOW; 1221 1222 pos = tmp - region->data; 1223 cs_dsp_coeff_parse_string(sizeof(u16), &tmp, data_len - pos, NULL); 1224 if (!tmp) 1225 return -EOVERFLOW; 1226 1227 pos = tmp - region->data; 1228 if (sizeof(raw->ncoeff) > (data_len - pos)) 1229 return -EOVERFLOW; 1230 1231 blk->ncoeff = cs_dsp_coeff_parse_int(sizeof(raw->ncoeff), &tmp); 1232 pos += sizeof(raw->ncoeff); 1233 break; 1234 } 1235 1236 if ((int)blk->ncoeff < 0) 1237 return -EOVERFLOW; 1238 1239 cs_dsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id); 1240 cs_dsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name); 1241 cs_dsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff); 1242 1243 return pos; 1244 } 1245 1246 static int cs_dsp_coeff_parse_coeff(struct cs_dsp *dsp, 1247 const struct wmfw_region *region, 1248 unsigned int pos, 1249 struct cs_dsp_coeff_parsed_coeff *blk) 1250 { 1251 const struct wmfw_adsp_coeff_data *raw; 1252 unsigned int data_len = le32_to_cpu(region->len); 1253 unsigned int blk_len, blk_end_pos; 1254 const u8 *tmp; 1255 1256 raw = (const struct wmfw_adsp_coeff_data *)®ion->data[pos]; 1257 if (sizeof(raw->hdr) > (data_len - pos)) 1258 return -EOVERFLOW; 1259 1260 blk_len = le32_to_cpu(raw->hdr.size); 1261 if (blk_len > S32_MAX) 1262 return -EOVERFLOW; 1263 1264 if (blk_len > (data_len - pos - sizeof(raw->hdr))) 1265 return -EOVERFLOW; 1266 1267 blk_end_pos = pos + sizeof(raw->hdr) + blk_len; 1268 1269 blk->offset = le16_to_cpu(raw->hdr.offset); 1270 blk->mem_type = le16_to_cpu(raw->hdr.type); 1271 1272 switch (dsp->wmfw_ver) { 1273 case 0: 1274 case 1: 1275 if (sizeof(*raw) > (data_len - pos)) 1276 return -EOVERFLOW; 1277 1278 blk->name = raw->name; 1279 blk->name_len = strnlen(raw->name, ARRAY_SIZE(raw->name)); 1280 blk->ctl_type = le16_to_cpu(raw->ctl_type); 1281 blk->flags = le16_to_cpu(raw->flags); 1282 blk->len = le32_to_cpu(raw->len); 1283 break; 1284 default: 1285 pos += sizeof(raw->hdr); 1286 tmp = ®ion->data[pos]; 1287 blk->name_len = cs_dsp_coeff_parse_string(sizeof(u8), &tmp, data_len - pos, 1288 &blk->name); 1289 if (!tmp) 1290 return -EOVERFLOW; 1291 1292 pos = tmp - region->data; 1293 cs_dsp_coeff_parse_string(sizeof(u8), &tmp, data_len - pos, NULL); 1294 if (!tmp) 1295 return -EOVERFLOW; 1296 1297 pos = tmp - region->data; 1298 cs_dsp_coeff_parse_string(sizeof(u16), &tmp, data_len - pos, NULL); 1299 if (!tmp) 1300 return -EOVERFLOW; 1301 1302 pos = tmp - region->data; 1303 if (sizeof(raw->ctl_type) + sizeof(raw->flags) + sizeof(raw->len) > 1304 (data_len - pos)) 1305 return -EOVERFLOW; 1306 1307 blk->ctl_type = cs_dsp_coeff_parse_int(sizeof(raw->ctl_type), &tmp); 1308 pos += sizeof(raw->ctl_type); 1309 blk->flags = cs_dsp_coeff_parse_int(sizeof(raw->flags), &tmp); 1310 pos += sizeof(raw->flags); 1311 blk->len = cs_dsp_coeff_parse_int(sizeof(raw->len), &tmp); 1312 break; 1313 } 1314 1315 cs_dsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type); 1316 cs_dsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset); 1317 cs_dsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name); 1318 cs_dsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags); 1319 cs_dsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type); 1320 cs_dsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len); 1321 1322 return blk_end_pos; 1323 } 1324 1325 static int cs_dsp_check_coeff_flags(struct cs_dsp *dsp, 1326 const struct cs_dsp_coeff_parsed_coeff *coeff_blk, 1327 unsigned int f_required, 1328 unsigned int f_illegal) 1329 { 1330 if ((coeff_blk->flags & f_illegal) || 1331 ((coeff_blk->flags & f_required) != f_required)) { 1332 cs_dsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n", 1333 coeff_blk->flags, coeff_blk->ctl_type); 1334 return -EINVAL; 1335 } 1336 1337 return 0; 1338 } 1339 1340 static int cs_dsp_parse_coeff(struct cs_dsp *dsp, 1341 const struct wmfw_region *region) 1342 { 1343 struct cs_dsp_alg_region alg_region = {}; 1344 struct cs_dsp_coeff_parsed_alg alg_blk; 1345 struct cs_dsp_coeff_parsed_coeff coeff_blk; 1346 int i, pos, ret; 1347 1348 pos = cs_dsp_coeff_parse_alg(dsp, region, &alg_blk); 1349 if (pos < 0) 1350 return pos; 1351 1352 for (i = 0; i < alg_blk.ncoeff; i++) { 1353 pos = cs_dsp_coeff_parse_coeff(dsp, region, pos, &coeff_blk); 1354 if (pos < 0) 1355 return pos; 1356 1357 switch (coeff_blk.ctl_type) { 1358 case WMFW_CTL_TYPE_BYTES: 1359 break; 1360 case WMFW_CTL_TYPE_ACKED: 1361 if (coeff_blk.flags & WMFW_CTL_FLAG_SYS) 1362 continue; /* ignore */ 1363 1364 ret = cs_dsp_check_coeff_flags(dsp, &coeff_blk, 1365 WMFW_CTL_FLAG_VOLATILE | 1366 WMFW_CTL_FLAG_WRITEABLE | 1367 WMFW_CTL_FLAG_READABLE, 1368 0); 1369 if (ret) 1370 return -EINVAL; 1371 break; 1372 case WMFW_CTL_TYPE_HOSTEVENT: 1373 case WMFW_CTL_TYPE_FWEVENT: 1374 ret = cs_dsp_check_coeff_flags(dsp, &coeff_blk, 1375 WMFW_CTL_FLAG_SYS | 1376 WMFW_CTL_FLAG_VOLATILE | 1377 WMFW_CTL_FLAG_WRITEABLE | 1378 WMFW_CTL_FLAG_READABLE, 1379 0); 1380 if (ret) 1381 return -EINVAL; 1382 break; 1383 case WMFW_CTL_TYPE_HOST_BUFFER: 1384 ret = cs_dsp_check_coeff_flags(dsp, &coeff_blk, 1385 WMFW_CTL_FLAG_SYS | 1386 WMFW_CTL_FLAG_VOLATILE | 1387 WMFW_CTL_FLAG_READABLE, 1388 0); 1389 if (ret) 1390 return -EINVAL; 1391 break; 1392 default: 1393 cs_dsp_err(dsp, "Unknown control type: %d\n", 1394 coeff_blk.ctl_type); 1395 return -EINVAL; 1396 } 1397 1398 alg_region.type = coeff_blk.mem_type; 1399 alg_region.alg = alg_blk.id; 1400 1401 ret = cs_dsp_create_control(dsp, &alg_region, 1402 coeff_blk.offset, 1403 coeff_blk.len, 1404 coeff_blk.name, 1405 coeff_blk.name_len, 1406 coeff_blk.flags, 1407 coeff_blk.ctl_type); 1408 if (ret < 0) 1409 cs_dsp_err(dsp, "Failed to create control: %.*s, %d\n", 1410 coeff_blk.name_len, coeff_blk.name, ret); 1411 } 1412 1413 return 0; 1414 } 1415 1416 static unsigned int cs_dsp_adsp1_parse_sizes(struct cs_dsp *dsp, 1417 const char * const file, 1418 unsigned int pos, 1419 const struct firmware *firmware) 1420 { 1421 const struct wmfw_adsp1_sizes *adsp1_sizes; 1422 1423 adsp1_sizes = (void *)&firmware->data[pos]; 1424 if (sizeof(*adsp1_sizes) > firmware->size - pos) { 1425 cs_dsp_err(dsp, "%s: file truncated\n", file); 1426 return 0; 1427 } 1428 1429 cs_dsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n", file, 1430 le32_to_cpu(adsp1_sizes->dm), le32_to_cpu(adsp1_sizes->pm), 1431 le32_to_cpu(adsp1_sizes->zm)); 1432 1433 return pos + sizeof(*adsp1_sizes); 1434 } 1435 1436 static unsigned int cs_dsp_adsp2_parse_sizes(struct cs_dsp *dsp, 1437 const char * const file, 1438 unsigned int pos, 1439 const struct firmware *firmware) 1440 { 1441 const struct wmfw_adsp2_sizes *adsp2_sizes; 1442 1443 adsp2_sizes = (void *)&firmware->data[pos]; 1444 if (sizeof(*adsp2_sizes) > firmware->size - pos) { 1445 cs_dsp_err(dsp, "%s: file truncated\n", file); 1446 return 0; 1447 } 1448 1449 cs_dsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n", file, 1450 le32_to_cpu(adsp2_sizes->xm), le32_to_cpu(adsp2_sizes->ym), 1451 le32_to_cpu(adsp2_sizes->pm), le32_to_cpu(adsp2_sizes->zm)); 1452 1453 return pos + sizeof(*adsp2_sizes); 1454 } 1455 1456 static bool cs_dsp_validate_version(struct cs_dsp *dsp, unsigned int version) 1457 { 1458 switch (version) { 1459 case 0: 1460 cs_dsp_warn(dsp, "Deprecated file format %d\n", version); 1461 return true; 1462 case 1: 1463 case 2: 1464 return true; 1465 default: 1466 return false; 1467 } 1468 } 1469 1470 static bool cs_dsp_halo_validate_version(struct cs_dsp *dsp, unsigned int version) 1471 { 1472 switch (version) { 1473 case 3: 1474 return true; 1475 default: 1476 return false; 1477 } 1478 } 1479 1480 static int cs_dsp_load(struct cs_dsp *dsp, const struct firmware *firmware, 1481 const char *file) 1482 { 1483 LIST_HEAD(buf_list); 1484 struct regmap *regmap = dsp->regmap; 1485 unsigned int pos = 0; 1486 const struct wmfw_header *header; 1487 const struct wmfw_footer *footer; 1488 const struct wmfw_region *region; 1489 const struct cs_dsp_region *mem; 1490 const char *region_name; 1491 u8 *buf = NULL; 1492 size_t buf_len = 0; 1493 size_t region_len; 1494 unsigned int reg; 1495 int regions = 0; 1496 int ret, offset, type; 1497 1498 if (!firmware) 1499 return 0; 1500 1501 ret = -EINVAL; 1502 1503 if (sizeof(*header) >= firmware->size) { 1504 ret = -EOVERFLOW; 1505 goto out_fw; 1506 } 1507 1508 header = (void *)&firmware->data[0]; 1509 1510 if (memcmp(&header->magic[0], "WMFW", 4) != 0) { 1511 cs_dsp_err(dsp, "%s: invalid magic\n", file); 1512 goto out_fw; 1513 } 1514 1515 if (!dsp->ops->validate_version(dsp, header->ver)) { 1516 cs_dsp_err(dsp, "%s: unknown file format %d\n", 1517 file, header->ver); 1518 goto out_fw; 1519 } 1520 1521 dsp->wmfw_ver = header->ver; 1522 1523 if (header->core != dsp->type) { 1524 cs_dsp_err(dsp, "%s: invalid core %d != %d\n", 1525 file, header->core, dsp->type); 1526 goto out_fw; 1527 } 1528 1529 pos = sizeof(*header); 1530 pos = dsp->ops->parse_sizes(dsp, file, pos, firmware); 1531 if ((pos == 0) || (sizeof(*footer) > firmware->size - pos)) { 1532 ret = -EOVERFLOW; 1533 goto out_fw; 1534 } 1535 1536 footer = (void *)&firmware->data[pos]; 1537 pos += sizeof(*footer); 1538 1539 if (le32_to_cpu(header->len) != pos) { 1540 ret = -EOVERFLOW; 1541 goto out_fw; 1542 } 1543 1544 cs_dsp_info(dsp, "%s: format %d timestamp %#llx\n", file, header->ver, 1545 le64_to_cpu(footer->timestamp)); 1546 1547 while (pos < firmware->size) { 1548 /* Is there enough data for a complete block header? */ 1549 if (sizeof(*region) > firmware->size - pos) { 1550 ret = -EOVERFLOW; 1551 goto out_fw; 1552 } 1553 1554 region = (void *)&(firmware->data[pos]); 1555 1556 if (le32_to_cpu(region->len) > firmware->size - pos - sizeof(*region)) { 1557 ret = -EOVERFLOW; 1558 goto out_fw; 1559 } 1560 1561 region_name = "Unknown"; 1562 reg = 0; 1563 offset = le32_to_cpu(region->offset) & 0xffffff; 1564 type = be32_to_cpu(region->type) & 0xff; 1565 1566 switch (type) { 1567 case WMFW_INFO_TEXT: 1568 case WMFW_NAME_TEXT: 1569 region_name = "Info/Name"; 1570 cs_dsp_info(dsp, "%s: %.*s\n", file, 1571 min(le32_to_cpu(region->len), 100), region->data); 1572 break; 1573 case WMFW_ALGORITHM_DATA: 1574 region_name = "Algorithm"; 1575 ret = cs_dsp_parse_coeff(dsp, region); 1576 if (ret != 0) 1577 goto out_fw; 1578 break; 1579 case WMFW_ABSOLUTE: 1580 region_name = "Absolute"; 1581 reg = offset; 1582 break; 1583 case WMFW_ADSP1_PM: 1584 case WMFW_ADSP1_DM: 1585 case WMFW_ADSP2_XM: 1586 case WMFW_ADSP2_YM: 1587 case WMFW_ADSP1_ZM: 1588 case WMFW_HALO_PM_PACKED: 1589 case WMFW_HALO_XM_PACKED: 1590 case WMFW_HALO_YM_PACKED: 1591 mem = cs_dsp_find_region(dsp, type); 1592 if (!mem) { 1593 cs_dsp_err(dsp, "No region of type: %x\n", type); 1594 ret = -EINVAL; 1595 goto out_fw; 1596 } 1597 1598 region_name = cs_dsp_mem_region_name(type); 1599 reg = dsp->ops->region_to_reg(mem, offset); 1600 break; 1601 default: 1602 cs_dsp_warn(dsp, 1603 "%s.%d: Unknown region type %x at %d(%x)\n", 1604 file, regions, type, pos, pos); 1605 break; 1606 } 1607 1608 cs_dsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file, 1609 regions, le32_to_cpu(region->len), offset, 1610 region_name); 1611 1612 if (reg) { 1613 region_len = le32_to_cpu(region->len); 1614 if (region_len > buf_len) { 1615 buf_len = round_up(region_len, PAGE_SIZE); 1616 kfree(buf); 1617 buf = kmalloc(buf_len, GFP_KERNEL | GFP_DMA); 1618 if (!buf) { 1619 ret = -ENOMEM; 1620 goto out_fw; 1621 } 1622 } 1623 1624 memcpy(buf, region->data, region_len); 1625 ret = regmap_raw_write(regmap, reg, buf, region_len); 1626 if (ret != 0) { 1627 cs_dsp_err(dsp, 1628 "%s.%d: Failed to write %zu bytes at %d in %s: %d\n", 1629 file, regions, region_len, offset, region_name, ret); 1630 goto out_fw; 1631 } 1632 } 1633 1634 pos += le32_to_cpu(region->len) + sizeof(*region); 1635 regions++; 1636 } 1637 1638 if (pos > firmware->size) 1639 cs_dsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", 1640 file, regions, pos - firmware->size); 1641 1642 cs_dsp_debugfs_save_wmfwname(dsp, file); 1643 1644 ret = 0; 1645 out_fw: 1646 kfree(buf); 1647 1648 if (ret == -EOVERFLOW) 1649 cs_dsp_err(dsp, "%s: file content overflows file data\n", file); 1650 1651 return ret; 1652 } 1653 1654 /** 1655 * cs_dsp_get_ctl() - Finds a matching coefficient control 1656 * @dsp: pointer to DSP structure 1657 * @name: pointer to string to match with a control's subname 1658 * @type: the algorithm type to match 1659 * @alg: the algorithm id to match 1660 * 1661 * Find cs_dsp_coeff_ctl with input name as its subname 1662 * 1663 * Return: pointer to the control on success, NULL if not found 1664 */ 1665 struct cs_dsp_coeff_ctl *cs_dsp_get_ctl(struct cs_dsp *dsp, const char *name, int type, 1666 unsigned int alg) 1667 { 1668 struct cs_dsp_coeff_ctl *pos, *rslt = NULL; 1669 1670 lockdep_assert_held(&dsp->pwr_lock); 1671 1672 list_for_each_entry(pos, &dsp->ctl_list, list) { 1673 if (!pos->subname) 1674 continue; 1675 if (strncmp(pos->subname, name, pos->subname_len) == 0 && 1676 pos->fw_name == dsp->fw_name && 1677 pos->alg_region.alg == alg && 1678 pos->alg_region.type == type) { 1679 rslt = pos; 1680 break; 1681 } 1682 } 1683 1684 return rslt; 1685 } 1686 EXPORT_SYMBOL_NS_GPL(cs_dsp_get_ctl, "FW_CS_DSP"); 1687 1688 static void cs_dsp_ctl_fixup_base(struct cs_dsp *dsp, 1689 const struct cs_dsp_alg_region *alg_region) 1690 { 1691 struct cs_dsp_coeff_ctl *ctl; 1692 1693 list_for_each_entry(ctl, &dsp->ctl_list, list) { 1694 if (ctl->fw_name == dsp->fw_name && 1695 alg_region->alg == ctl->alg_region.alg && 1696 alg_region->type == ctl->alg_region.type) { 1697 ctl->alg_region.base = alg_region->base; 1698 } 1699 } 1700 } 1701 1702 static void *cs_dsp_read_algs(struct cs_dsp *dsp, size_t n_algs, 1703 const struct cs_dsp_region *mem, 1704 unsigned int pos, unsigned int len) 1705 { 1706 void *alg; 1707 unsigned int reg; 1708 int ret; 1709 __be32 val; 1710 1711 if (n_algs == 0) { 1712 cs_dsp_err(dsp, "No algorithms\n"); 1713 return ERR_PTR(-EINVAL); 1714 } 1715 1716 if (n_algs > 1024) { 1717 cs_dsp_err(dsp, "Algorithm count %zx excessive\n", n_algs); 1718 return ERR_PTR(-EINVAL); 1719 } 1720 1721 /* Read the terminator first to validate the length */ 1722 reg = dsp->ops->region_to_reg(mem, pos + len); 1723 1724 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); 1725 if (ret != 0) { 1726 cs_dsp_err(dsp, "Failed to read algorithm list end: %d\n", 1727 ret); 1728 return ERR_PTR(ret); 1729 } 1730 1731 if (be32_to_cpu(val) != 0xbedead) 1732 cs_dsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n", 1733 reg, be32_to_cpu(val)); 1734 1735 /* Convert length from DSP words to bytes */ 1736 len *= sizeof(u32); 1737 1738 alg = kzalloc(len, GFP_KERNEL | GFP_DMA); 1739 if (!alg) 1740 return ERR_PTR(-ENOMEM); 1741 1742 reg = dsp->ops->region_to_reg(mem, pos); 1743 1744 ret = regmap_raw_read(dsp->regmap, reg, alg, len); 1745 if (ret != 0) { 1746 cs_dsp_err(dsp, "Failed to read algorithm list: %d\n", ret); 1747 kfree(alg); 1748 return ERR_PTR(ret); 1749 } 1750 1751 return alg; 1752 } 1753 1754 /** 1755 * cs_dsp_find_alg_region() - Finds a matching algorithm region 1756 * @dsp: pointer to DSP structure 1757 * @type: the algorithm type to match 1758 * @id: the algorithm id to match 1759 * 1760 * Return: Pointer to matching algorithm region, or NULL if not found. 1761 */ 1762 struct cs_dsp_alg_region *cs_dsp_find_alg_region(struct cs_dsp *dsp, 1763 int type, unsigned int id) 1764 { 1765 struct cs_dsp_alg_region_list_item *item; 1766 1767 lockdep_assert_held(&dsp->pwr_lock); 1768 1769 list_for_each_entry(item, &dsp->alg_regions, list) { 1770 if (id == item->alg_region.alg && type == item->alg_region.type) 1771 return &item->alg_region; 1772 } 1773 1774 return NULL; 1775 } 1776 EXPORT_SYMBOL_NS_GPL(cs_dsp_find_alg_region, "FW_CS_DSP"); 1777 1778 static struct cs_dsp_alg_region *cs_dsp_create_region(struct cs_dsp *dsp, 1779 int type, __be32 id, 1780 __be32 ver, __be32 base) 1781 { 1782 struct cs_dsp_alg_region_list_item *item; 1783 1784 item = kzalloc(sizeof(*item), GFP_KERNEL); 1785 if (!item) 1786 return ERR_PTR(-ENOMEM); 1787 1788 item->alg_region.type = type; 1789 item->alg_region.alg = be32_to_cpu(id); 1790 item->alg_region.ver = be32_to_cpu(ver); 1791 item->alg_region.base = be32_to_cpu(base); 1792 1793 list_add_tail(&item->list, &dsp->alg_regions); 1794 1795 if (dsp->wmfw_ver > 0) 1796 cs_dsp_ctl_fixup_base(dsp, &item->alg_region); 1797 1798 return &item->alg_region; 1799 } 1800 1801 static void cs_dsp_free_alg_regions(struct cs_dsp *dsp) 1802 { 1803 struct cs_dsp_alg_region_list_item *item; 1804 1805 while (!list_empty(&dsp->alg_regions)) { 1806 item = list_first_entry(&dsp->alg_regions, 1807 struct cs_dsp_alg_region_list_item, 1808 list); 1809 list_del(&item->list); 1810 kfree(item); 1811 } 1812 } 1813 1814 static void cs_dsp_parse_wmfw_id_header(struct cs_dsp *dsp, 1815 struct wmfw_id_hdr *fw, int nalgs) 1816 { 1817 dsp->fw_id = be32_to_cpu(fw->id); 1818 dsp->fw_id_version = be32_to_cpu(fw->ver); 1819 1820 cs_dsp_info(dsp, "Firmware: %x v%d.%d.%d, %d algorithms\n", 1821 dsp->fw_id, (dsp->fw_id_version & 0xff0000) >> 16, 1822 (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff, 1823 nalgs); 1824 } 1825 1826 static void cs_dsp_parse_wmfw_v3_id_header(struct cs_dsp *dsp, 1827 struct wmfw_v3_id_hdr *fw, int nalgs) 1828 { 1829 dsp->fw_id = be32_to_cpu(fw->id); 1830 dsp->fw_id_version = be32_to_cpu(fw->ver); 1831 dsp->fw_vendor_id = be32_to_cpu(fw->vendor_id); 1832 1833 cs_dsp_info(dsp, "Firmware: %x vendor: 0x%x v%d.%d.%d, %d algorithms\n", 1834 dsp->fw_id, dsp->fw_vendor_id, 1835 (dsp->fw_id_version & 0xff0000) >> 16, 1836 (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff, 1837 nalgs); 1838 } 1839 1840 static int cs_dsp_create_regions(struct cs_dsp *dsp, __be32 id, __be32 ver, 1841 int nregions, const int *type, __be32 *base) 1842 { 1843 struct cs_dsp_alg_region *alg_region; 1844 int i; 1845 1846 for (i = 0; i < nregions; i++) { 1847 alg_region = cs_dsp_create_region(dsp, type[i], id, ver, base[i]); 1848 if (IS_ERR(alg_region)) 1849 return PTR_ERR(alg_region); 1850 } 1851 1852 return 0; 1853 } 1854 1855 static int cs_dsp_adsp1_setup_algs(struct cs_dsp *dsp) 1856 { 1857 struct wmfw_adsp1_id_hdr adsp1_id; 1858 struct wmfw_adsp1_alg_hdr *adsp1_alg; 1859 struct cs_dsp_alg_region *alg_region; 1860 const struct cs_dsp_region *mem; 1861 unsigned int pos, len; 1862 size_t n_algs; 1863 int i, ret; 1864 1865 mem = cs_dsp_find_region(dsp, WMFW_ADSP1_DM); 1866 if (WARN_ON(!mem)) 1867 return -EINVAL; 1868 1869 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id, 1870 sizeof(adsp1_id)); 1871 if (ret != 0) { 1872 cs_dsp_err(dsp, "Failed to read algorithm info: %d\n", 1873 ret); 1874 return ret; 1875 } 1876 1877 n_algs = be32_to_cpu(adsp1_id.n_algs); 1878 1879 cs_dsp_parse_wmfw_id_header(dsp, &adsp1_id.fw, n_algs); 1880 1881 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_ZM, 1882 adsp1_id.fw.id, adsp1_id.fw.ver, 1883 adsp1_id.zm); 1884 if (IS_ERR(alg_region)) 1885 return PTR_ERR(alg_region); 1886 1887 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_DM, 1888 adsp1_id.fw.id, adsp1_id.fw.ver, 1889 adsp1_id.dm); 1890 if (IS_ERR(alg_region)) 1891 return PTR_ERR(alg_region); 1892 1893 /* Calculate offset and length in DSP words */ 1894 pos = sizeof(adsp1_id) / sizeof(u32); 1895 len = (sizeof(*adsp1_alg) * n_algs) / sizeof(u32); 1896 1897 adsp1_alg = cs_dsp_read_algs(dsp, n_algs, mem, pos, len); 1898 if (IS_ERR(adsp1_alg)) 1899 return PTR_ERR(adsp1_alg); 1900 1901 for (i = 0; i < n_algs; i++) { 1902 cs_dsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n", 1903 i, be32_to_cpu(adsp1_alg[i].alg.id), 1904 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16, 1905 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8, 1906 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff, 1907 be32_to_cpu(adsp1_alg[i].dm), 1908 be32_to_cpu(adsp1_alg[i].zm)); 1909 1910 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_DM, 1911 adsp1_alg[i].alg.id, 1912 adsp1_alg[i].alg.ver, 1913 adsp1_alg[i].dm); 1914 if (IS_ERR(alg_region)) { 1915 ret = PTR_ERR(alg_region); 1916 goto out; 1917 } 1918 if (dsp->wmfw_ver == 0) { 1919 if (i + 1 < n_algs) { 1920 len = be32_to_cpu(adsp1_alg[i + 1].dm); 1921 len -= be32_to_cpu(adsp1_alg[i].dm); 1922 len *= 4; 1923 cs_dsp_create_control(dsp, alg_region, 0, 1924 len, NULL, 0, 0, 1925 WMFW_CTL_TYPE_BYTES); 1926 } else { 1927 cs_dsp_warn(dsp, "Missing length info for region DM with ID %x\n", 1928 be32_to_cpu(adsp1_alg[i].alg.id)); 1929 } 1930 } 1931 1932 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_ZM, 1933 adsp1_alg[i].alg.id, 1934 adsp1_alg[i].alg.ver, 1935 adsp1_alg[i].zm); 1936 if (IS_ERR(alg_region)) { 1937 ret = PTR_ERR(alg_region); 1938 goto out; 1939 } 1940 if (dsp->wmfw_ver == 0) { 1941 if (i + 1 < n_algs) { 1942 len = be32_to_cpu(adsp1_alg[i + 1].zm); 1943 len -= be32_to_cpu(adsp1_alg[i].zm); 1944 len *= 4; 1945 cs_dsp_create_control(dsp, alg_region, 0, 1946 len, NULL, 0, 0, 1947 WMFW_CTL_TYPE_BYTES); 1948 } else { 1949 cs_dsp_warn(dsp, "Missing length info for region ZM with ID %x\n", 1950 be32_to_cpu(adsp1_alg[i].alg.id)); 1951 } 1952 } 1953 } 1954 1955 out: 1956 kfree(adsp1_alg); 1957 return ret; 1958 } 1959 1960 static int cs_dsp_adsp2_setup_algs(struct cs_dsp *dsp) 1961 { 1962 struct wmfw_adsp2_id_hdr adsp2_id; 1963 struct wmfw_adsp2_alg_hdr *adsp2_alg; 1964 struct cs_dsp_alg_region *alg_region; 1965 const struct cs_dsp_region *mem; 1966 unsigned int pos, len; 1967 size_t n_algs; 1968 int i, ret; 1969 1970 mem = cs_dsp_find_region(dsp, WMFW_ADSP2_XM); 1971 if (WARN_ON(!mem)) 1972 return -EINVAL; 1973 1974 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id, 1975 sizeof(adsp2_id)); 1976 if (ret != 0) { 1977 cs_dsp_err(dsp, "Failed to read algorithm info: %d\n", 1978 ret); 1979 return ret; 1980 } 1981 1982 n_algs = be32_to_cpu(adsp2_id.n_algs); 1983 1984 cs_dsp_parse_wmfw_id_header(dsp, &adsp2_id.fw, n_algs); 1985 1986 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_XM, 1987 adsp2_id.fw.id, adsp2_id.fw.ver, 1988 adsp2_id.xm); 1989 if (IS_ERR(alg_region)) 1990 return PTR_ERR(alg_region); 1991 1992 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_YM, 1993 adsp2_id.fw.id, adsp2_id.fw.ver, 1994 adsp2_id.ym); 1995 if (IS_ERR(alg_region)) 1996 return PTR_ERR(alg_region); 1997 1998 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_ZM, 1999 adsp2_id.fw.id, adsp2_id.fw.ver, 2000 adsp2_id.zm); 2001 if (IS_ERR(alg_region)) 2002 return PTR_ERR(alg_region); 2003 2004 /* Calculate offset and length in DSP words */ 2005 pos = sizeof(adsp2_id) / sizeof(u32); 2006 len = (sizeof(*adsp2_alg) * n_algs) / sizeof(u32); 2007 2008 adsp2_alg = cs_dsp_read_algs(dsp, n_algs, mem, pos, len); 2009 if (IS_ERR(adsp2_alg)) 2010 return PTR_ERR(adsp2_alg); 2011 2012 for (i = 0; i < n_algs; i++) { 2013 cs_dsp_dbg(dsp, 2014 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n", 2015 i, be32_to_cpu(adsp2_alg[i].alg.id), 2016 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16, 2017 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8, 2018 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff, 2019 be32_to_cpu(adsp2_alg[i].xm), 2020 be32_to_cpu(adsp2_alg[i].ym), 2021 be32_to_cpu(adsp2_alg[i].zm)); 2022 2023 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_XM, 2024 adsp2_alg[i].alg.id, 2025 adsp2_alg[i].alg.ver, 2026 adsp2_alg[i].xm); 2027 if (IS_ERR(alg_region)) { 2028 ret = PTR_ERR(alg_region); 2029 goto out; 2030 } 2031 if (dsp->wmfw_ver == 0) { 2032 if (i + 1 < n_algs) { 2033 len = be32_to_cpu(adsp2_alg[i + 1].xm); 2034 len -= be32_to_cpu(adsp2_alg[i].xm); 2035 len *= 4; 2036 cs_dsp_create_control(dsp, alg_region, 0, 2037 len, NULL, 0, 0, 2038 WMFW_CTL_TYPE_BYTES); 2039 } else { 2040 cs_dsp_warn(dsp, "Missing length info for region XM with ID %x\n", 2041 be32_to_cpu(adsp2_alg[i].alg.id)); 2042 } 2043 } 2044 2045 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_YM, 2046 adsp2_alg[i].alg.id, 2047 adsp2_alg[i].alg.ver, 2048 adsp2_alg[i].ym); 2049 if (IS_ERR(alg_region)) { 2050 ret = PTR_ERR(alg_region); 2051 goto out; 2052 } 2053 if (dsp->wmfw_ver == 0) { 2054 if (i + 1 < n_algs) { 2055 len = be32_to_cpu(adsp2_alg[i + 1].ym); 2056 len -= be32_to_cpu(adsp2_alg[i].ym); 2057 len *= 4; 2058 cs_dsp_create_control(dsp, alg_region, 0, 2059 len, NULL, 0, 0, 2060 WMFW_CTL_TYPE_BYTES); 2061 } else { 2062 cs_dsp_warn(dsp, "Missing length info for region YM with ID %x\n", 2063 be32_to_cpu(adsp2_alg[i].alg.id)); 2064 } 2065 } 2066 2067 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_ZM, 2068 adsp2_alg[i].alg.id, 2069 adsp2_alg[i].alg.ver, 2070 adsp2_alg[i].zm); 2071 if (IS_ERR(alg_region)) { 2072 ret = PTR_ERR(alg_region); 2073 goto out; 2074 } 2075 if (dsp->wmfw_ver == 0) { 2076 if (i + 1 < n_algs) { 2077 len = be32_to_cpu(adsp2_alg[i + 1].zm); 2078 len -= be32_to_cpu(adsp2_alg[i].zm); 2079 len *= 4; 2080 cs_dsp_create_control(dsp, alg_region, 0, 2081 len, NULL, 0, 0, 2082 WMFW_CTL_TYPE_BYTES); 2083 } else { 2084 cs_dsp_warn(dsp, "Missing length info for region ZM with ID %x\n", 2085 be32_to_cpu(adsp2_alg[i].alg.id)); 2086 } 2087 } 2088 } 2089 2090 out: 2091 kfree(adsp2_alg); 2092 return ret; 2093 } 2094 2095 static int cs_dsp_halo_create_regions(struct cs_dsp *dsp, __be32 id, __be32 ver, 2096 __be32 xm_base, __be32 ym_base) 2097 { 2098 static const int types[] = { 2099 WMFW_ADSP2_XM, WMFW_HALO_XM_PACKED, 2100 WMFW_ADSP2_YM, WMFW_HALO_YM_PACKED 2101 }; 2102 __be32 bases[] = { xm_base, xm_base, ym_base, ym_base }; 2103 2104 return cs_dsp_create_regions(dsp, id, ver, ARRAY_SIZE(types), types, bases); 2105 } 2106 2107 static int cs_dsp_halo_setup_algs(struct cs_dsp *dsp) 2108 { 2109 struct wmfw_halo_id_hdr halo_id; 2110 struct wmfw_halo_alg_hdr *halo_alg; 2111 const struct cs_dsp_region *mem; 2112 unsigned int pos, len; 2113 size_t n_algs; 2114 int i, ret; 2115 2116 mem = cs_dsp_find_region(dsp, WMFW_ADSP2_XM); 2117 if (WARN_ON(!mem)) 2118 return -EINVAL; 2119 2120 ret = regmap_raw_read(dsp->regmap, mem->base, &halo_id, 2121 sizeof(halo_id)); 2122 if (ret != 0) { 2123 cs_dsp_err(dsp, "Failed to read algorithm info: %d\n", 2124 ret); 2125 return ret; 2126 } 2127 2128 n_algs = be32_to_cpu(halo_id.n_algs); 2129 2130 cs_dsp_parse_wmfw_v3_id_header(dsp, &halo_id.fw, n_algs); 2131 2132 ret = cs_dsp_halo_create_regions(dsp, halo_id.fw.id, halo_id.fw.ver, 2133 halo_id.xm_base, halo_id.ym_base); 2134 if (ret) 2135 return ret; 2136 2137 /* Calculate offset and length in DSP words */ 2138 pos = sizeof(halo_id) / sizeof(u32); 2139 len = (sizeof(*halo_alg) * n_algs) / sizeof(u32); 2140 2141 halo_alg = cs_dsp_read_algs(dsp, n_algs, mem, pos, len); 2142 if (IS_ERR(halo_alg)) 2143 return PTR_ERR(halo_alg); 2144 2145 for (i = 0; i < n_algs; i++) { 2146 cs_dsp_dbg(dsp, 2147 "%d: ID %x v%d.%d.%d XM@%x YM@%x\n", 2148 i, be32_to_cpu(halo_alg[i].alg.id), 2149 (be32_to_cpu(halo_alg[i].alg.ver) & 0xff0000) >> 16, 2150 (be32_to_cpu(halo_alg[i].alg.ver) & 0xff00) >> 8, 2151 be32_to_cpu(halo_alg[i].alg.ver) & 0xff, 2152 be32_to_cpu(halo_alg[i].xm_base), 2153 be32_to_cpu(halo_alg[i].ym_base)); 2154 2155 ret = cs_dsp_halo_create_regions(dsp, halo_alg[i].alg.id, 2156 halo_alg[i].alg.ver, 2157 halo_alg[i].xm_base, 2158 halo_alg[i].ym_base); 2159 if (ret) 2160 goto out; 2161 } 2162 2163 out: 2164 kfree(halo_alg); 2165 return ret; 2166 } 2167 2168 static int cs_dsp_load_coeff(struct cs_dsp *dsp, const struct firmware *firmware, 2169 const char *file) 2170 { 2171 LIST_HEAD(buf_list); 2172 struct regmap *regmap = dsp->regmap; 2173 struct wmfw_coeff_hdr *hdr; 2174 struct wmfw_coeff_item *blk; 2175 const struct cs_dsp_region *mem; 2176 struct cs_dsp_alg_region *alg_region; 2177 const char *region_name; 2178 int ret, pos, blocks, type, version; 2179 unsigned int offset, reg; 2180 u8 *buf = NULL; 2181 size_t buf_len = 0; 2182 size_t region_len; 2183 2184 if (!firmware) 2185 return 0; 2186 2187 ret = -EINVAL; 2188 2189 if (sizeof(*hdr) >= firmware->size) { 2190 cs_dsp_err(dsp, "%s: coefficient file too short, %zu bytes\n", 2191 file, firmware->size); 2192 goto out_fw; 2193 } 2194 2195 hdr = (void *)&firmware->data[0]; 2196 if (memcmp(hdr->magic, "WMDR", 4) != 0) { 2197 cs_dsp_err(dsp, "%s: invalid coefficient magic\n", file); 2198 goto out_fw; 2199 } 2200 2201 switch (be32_to_cpu(hdr->rev) & 0xff) { 2202 case 1: 2203 case 2: 2204 case 3: 2205 break; 2206 default: 2207 cs_dsp_err(dsp, "%s: Unsupported coefficient file format %d\n", 2208 file, be32_to_cpu(hdr->rev) & 0xff); 2209 ret = -EINVAL; 2210 goto out_fw; 2211 } 2212 2213 cs_dsp_info(dsp, "%s (v%d): v%d.%d.%d\n", file, 2214 be32_to_cpu(hdr->rev) & 0xff, 2215 (le32_to_cpu(hdr->ver) >> 16) & 0xff, 2216 (le32_to_cpu(hdr->ver) >> 8) & 0xff, 2217 le32_to_cpu(hdr->ver) & 0xff); 2218 2219 pos = le32_to_cpu(hdr->len); 2220 2221 blocks = 0; 2222 while (pos < firmware->size) { 2223 /* Is there enough data for a complete block header? */ 2224 if (sizeof(*blk) > firmware->size - pos) { 2225 ret = -EOVERFLOW; 2226 goto out_fw; 2227 } 2228 2229 blk = (void *)(&firmware->data[pos]); 2230 2231 if (le32_to_cpu(blk->len) > firmware->size - pos - sizeof(*blk)) { 2232 ret = -EOVERFLOW; 2233 goto out_fw; 2234 } 2235 2236 type = le16_to_cpu(blk->type); 2237 offset = le16_to_cpu(blk->offset); 2238 version = le32_to_cpu(blk->ver) >> 8; 2239 2240 cs_dsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n", 2241 file, blocks, le32_to_cpu(blk->id), 2242 (le32_to_cpu(blk->ver) >> 16) & 0xff, 2243 (le32_to_cpu(blk->ver) >> 8) & 0xff, 2244 le32_to_cpu(blk->ver) & 0xff); 2245 cs_dsp_dbg(dsp, "%s.%d: %d bytes off:%#x off32:%#x in %#x\n", 2246 file, blocks, le32_to_cpu(blk->len), offset, 2247 le32_to_cpu(blk->offset32), type); 2248 2249 reg = 0; 2250 region_name = "Unknown"; 2251 switch (type) { 2252 case (WMFW_NAME_TEXT << 8): 2253 cs_dsp_info(dsp, "%s: %.*s\n", dsp->fw_name, 2254 min(le32_to_cpu(blk->len), 100), blk->data); 2255 break; 2256 case (WMFW_INFO_TEXT << 8): 2257 case (WMFW_METADATA << 8): 2258 break; 2259 case (WMFW_ABSOLUTE << 8): 2260 /* 2261 * Old files may use this for global 2262 * coefficients. 2263 */ 2264 if (le32_to_cpu(blk->id) == dsp->fw_id && 2265 offset == 0) { 2266 region_name = "global coefficients"; 2267 mem = cs_dsp_find_region(dsp, type); 2268 if (!mem) { 2269 cs_dsp_err(dsp, "No ZM\n"); 2270 break; 2271 } 2272 reg = dsp->ops->region_to_reg(mem, 0); 2273 2274 } else { 2275 region_name = "register"; 2276 reg = offset; 2277 } 2278 break; 2279 2280 case WMFW_ADSP2_XM_LONG: 2281 case WMFW_ADSP2_YM_LONG: 2282 case WMFW_HALO_XM_PACKED_LONG: 2283 case WMFW_HALO_YM_PACKED_LONG: 2284 offset = le32_to_cpu(blk->offset32); 2285 type &= 0xff; /* strip extended block type flags */ 2286 fallthrough; 2287 case WMFW_ADSP1_DM: 2288 case WMFW_ADSP1_ZM: 2289 case WMFW_ADSP2_XM: 2290 case WMFW_ADSP2_YM: 2291 case WMFW_HALO_XM_PACKED: 2292 case WMFW_HALO_YM_PACKED: 2293 case WMFW_HALO_PM_PACKED: 2294 cs_dsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n", 2295 file, blocks, le32_to_cpu(blk->len), 2296 type, le32_to_cpu(blk->id)); 2297 2298 region_name = cs_dsp_mem_region_name(type); 2299 mem = cs_dsp_find_region(dsp, type); 2300 if (!mem) { 2301 cs_dsp_err(dsp, "No base for region %x\n", type); 2302 break; 2303 } 2304 2305 alg_region = cs_dsp_find_alg_region(dsp, type, 2306 le32_to_cpu(blk->id)); 2307 if (alg_region) { 2308 if (version != alg_region->ver) 2309 cs_dsp_warn(dsp, 2310 "Algorithm coefficient version %d.%d.%d but expected %d.%d.%d\n", 2311 (version >> 16) & 0xFF, 2312 (version >> 8) & 0xFF, 2313 version & 0xFF, 2314 (alg_region->ver >> 16) & 0xFF, 2315 (alg_region->ver >> 8) & 0xFF, 2316 alg_region->ver & 0xFF); 2317 2318 reg = alg_region->base; 2319 reg = dsp->ops->region_to_reg(mem, reg); 2320 reg += offset; 2321 } else { 2322 cs_dsp_err(dsp, "No %s for algorithm %x\n", 2323 region_name, le32_to_cpu(blk->id)); 2324 } 2325 break; 2326 2327 default: 2328 cs_dsp_err(dsp, "%s.%d: Unknown region type %x at %d\n", 2329 file, blocks, type, pos); 2330 break; 2331 } 2332 2333 if (reg) { 2334 region_len = le32_to_cpu(blk->len); 2335 if (region_len > buf_len) { 2336 buf_len = round_up(region_len, PAGE_SIZE); 2337 kfree(buf); 2338 buf = kmalloc(buf_len, GFP_KERNEL | GFP_DMA); 2339 if (!buf) { 2340 ret = -ENOMEM; 2341 goto out_fw; 2342 } 2343 } 2344 2345 memcpy(buf, blk->data, region_len); 2346 2347 cs_dsp_dbg(dsp, "%s.%d: Writing %zu bytes at %x\n", 2348 file, blocks, region_len, reg); 2349 ret = regmap_raw_write(regmap, reg, buf, region_len); 2350 if (ret != 0) { 2351 cs_dsp_err(dsp, 2352 "%s.%d: Failed to write to %x in %s: %d\n", 2353 file, blocks, reg, region_name, ret); 2354 } 2355 } 2356 2357 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03; 2358 blocks++; 2359 } 2360 2361 if (pos > firmware->size) 2362 cs_dsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", 2363 file, blocks, pos - firmware->size); 2364 2365 cs_dsp_debugfs_save_binname(dsp, file); 2366 2367 ret = 0; 2368 out_fw: 2369 kfree(buf); 2370 2371 if (ret == -EOVERFLOW) 2372 cs_dsp_err(dsp, "%s: file content overflows file data\n", file); 2373 2374 return ret; 2375 } 2376 2377 static int cs_dsp_create_name(struct cs_dsp *dsp) 2378 { 2379 if (!dsp->name) { 2380 dsp->name = devm_kasprintf(dsp->dev, GFP_KERNEL, "DSP%d", 2381 dsp->num); 2382 if (!dsp->name) 2383 return -ENOMEM; 2384 } 2385 2386 return 0; 2387 } 2388 2389 static const struct cs_dsp_client_ops cs_dsp_default_client_ops = { 2390 }; 2391 2392 static int cs_dsp_common_init(struct cs_dsp *dsp) 2393 { 2394 int ret; 2395 2396 ret = cs_dsp_create_name(dsp); 2397 if (ret) 2398 return ret; 2399 2400 INIT_LIST_HEAD(&dsp->alg_regions); 2401 INIT_LIST_HEAD(&dsp->ctl_list); 2402 2403 mutex_init(&dsp->pwr_lock); 2404 2405 if (!dsp->client_ops) 2406 dsp->client_ops = &cs_dsp_default_client_ops; 2407 2408 #ifdef CONFIG_DEBUG_FS 2409 /* Ensure this is invalid if client never provides a debugfs root */ 2410 dsp->debugfs_root = ERR_PTR(-ENODEV); 2411 #endif 2412 2413 return 0; 2414 } 2415 2416 /** 2417 * cs_dsp_adsp1_init() - Initialise a cs_dsp structure representing a ADSP1 device 2418 * @dsp: pointer to DSP structure 2419 * 2420 * Return: Zero for success, a negative number on error. 2421 */ 2422 int cs_dsp_adsp1_init(struct cs_dsp *dsp) 2423 { 2424 dsp->ops = &cs_dsp_adsp1_ops; 2425 2426 return cs_dsp_common_init(dsp); 2427 } 2428 EXPORT_SYMBOL_NS_GPL(cs_dsp_adsp1_init, "FW_CS_DSP"); 2429 2430 /** 2431 * cs_dsp_adsp1_power_up() - Load and start the named firmware 2432 * @dsp: pointer to DSP structure 2433 * @wmfw_firmware: the firmware to be sent 2434 * @wmfw_filename: file name of firmware to be sent 2435 * @coeff_firmware: the coefficient data to be sent 2436 * @coeff_filename: file name of coefficient to data be sent 2437 * @fw_name: the user-friendly firmware name 2438 * 2439 * Return: Zero for success, a negative number on error. 2440 */ 2441 int cs_dsp_adsp1_power_up(struct cs_dsp *dsp, 2442 const struct firmware *wmfw_firmware, const char *wmfw_filename, 2443 const struct firmware *coeff_firmware, const char *coeff_filename, 2444 const char *fw_name) 2445 { 2446 unsigned int val; 2447 int ret; 2448 2449 mutex_lock(&dsp->pwr_lock); 2450 2451 dsp->fw_name = fw_name; 2452 2453 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, 2454 ADSP1_SYS_ENA, ADSP1_SYS_ENA); 2455 2456 /* 2457 * For simplicity set the DSP clock rate to be the 2458 * SYSCLK rate rather than making it configurable. 2459 */ 2460 if (dsp->sysclk_reg) { 2461 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val); 2462 if (ret != 0) { 2463 cs_dsp_err(dsp, "Failed to read SYSCLK state: %d\n", ret); 2464 goto err_mutex; 2465 } 2466 2467 val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift; 2468 2469 ret = regmap_update_bits(dsp->regmap, 2470 dsp->base + ADSP1_CONTROL_31, 2471 ADSP1_CLK_SEL_MASK, val); 2472 if (ret != 0) { 2473 cs_dsp_err(dsp, "Failed to set clock rate: %d\n", ret); 2474 goto err_mutex; 2475 } 2476 } 2477 2478 ret = cs_dsp_load(dsp, wmfw_firmware, wmfw_filename); 2479 if (ret != 0) 2480 goto err_ena; 2481 2482 ret = cs_dsp_adsp1_setup_algs(dsp); 2483 if (ret != 0) 2484 goto err_ena; 2485 2486 ret = cs_dsp_load_coeff(dsp, coeff_firmware, coeff_filename); 2487 if (ret != 0) 2488 goto err_ena; 2489 2490 /* Initialize caches for enabled and unset controls */ 2491 ret = cs_dsp_coeff_init_control_caches(dsp); 2492 if (ret != 0) 2493 goto err_ena; 2494 2495 /* Sync set controls */ 2496 ret = cs_dsp_coeff_sync_controls(dsp); 2497 if (ret != 0) 2498 goto err_ena; 2499 2500 dsp->booted = true; 2501 2502 /* Start the core running */ 2503 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, 2504 ADSP1_CORE_ENA | ADSP1_START, 2505 ADSP1_CORE_ENA | ADSP1_START); 2506 2507 dsp->running = true; 2508 2509 mutex_unlock(&dsp->pwr_lock); 2510 2511 return 0; 2512 2513 err_ena: 2514 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, 2515 ADSP1_SYS_ENA, 0); 2516 err_mutex: 2517 mutex_unlock(&dsp->pwr_lock); 2518 return ret; 2519 } 2520 EXPORT_SYMBOL_NS_GPL(cs_dsp_adsp1_power_up, "FW_CS_DSP"); 2521 2522 /** 2523 * cs_dsp_adsp1_power_down() - Halts the DSP 2524 * @dsp: pointer to DSP structure 2525 */ 2526 void cs_dsp_adsp1_power_down(struct cs_dsp *dsp) 2527 { 2528 struct cs_dsp_coeff_ctl *ctl; 2529 2530 mutex_lock(&dsp->pwr_lock); 2531 2532 dsp->running = false; 2533 dsp->booted = false; 2534 2535 /* Halt the core */ 2536 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, 2537 ADSP1_CORE_ENA | ADSP1_START, 0); 2538 2539 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19, 2540 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0); 2541 2542 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, 2543 ADSP1_SYS_ENA, 0); 2544 2545 list_for_each_entry(ctl, &dsp->ctl_list, list) 2546 ctl->enabled = 0; 2547 2548 cs_dsp_free_alg_regions(dsp); 2549 2550 mutex_unlock(&dsp->pwr_lock); 2551 } 2552 EXPORT_SYMBOL_NS_GPL(cs_dsp_adsp1_power_down, "FW_CS_DSP"); 2553 2554 static int cs_dsp_adsp2v2_enable_core(struct cs_dsp *dsp) 2555 { 2556 unsigned int val; 2557 int ret, count; 2558 2559 /* Wait for the RAM to start, should be near instantaneous */ 2560 for (count = 0; count < 10; ++count) { 2561 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val); 2562 if (ret != 0) 2563 return ret; 2564 2565 if (val & ADSP2_RAM_RDY) 2566 break; 2567 2568 usleep_range(250, 500); 2569 } 2570 2571 if (!(val & ADSP2_RAM_RDY)) { 2572 cs_dsp_err(dsp, "Failed to start DSP RAM\n"); 2573 return -EBUSY; 2574 } 2575 2576 cs_dsp_dbg(dsp, "RAM ready after %d polls\n", count); 2577 2578 return 0; 2579 } 2580 2581 static int cs_dsp_adsp2_enable_core(struct cs_dsp *dsp) 2582 { 2583 int ret; 2584 2585 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, 2586 ADSP2_SYS_ENA, ADSP2_SYS_ENA); 2587 if (ret != 0) 2588 return ret; 2589 2590 return cs_dsp_adsp2v2_enable_core(dsp); 2591 } 2592 2593 static int cs_dsp_adsp2_lock(struct cs_dsp *dsp, unsigned int lock_regions) 2594 { 2595 struct regmap *regmap = dsp->regmap; 2596 unsigned int code0, code1, lock_reg; 2597 2598 if (!(lock_regions & CS_ADSP2_REGION_ALL)) 2599 return 0; 2600 2601 lock_regions &= CS_ADSP2_REGION_ALL; 2602 lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0; 2603 2604 while (lock_regions) { 2605 code0 = code1 = 0; 2606 if (lock_regions & BIT(0)) { 2607 code0 = ADSP2_LOCK_CODE_0; 2608 code1 = ADSP2_LOCK_CODE_1; 2609 } 2610 if (lock_regions & BIT(1)) { 2611 code0 |= ADSP2_LOCK_CODE_0 << ADSP2_LOCK_REGION_SHIFT; 2612 code1 |= ADSP2_LOCK_CODE_1 << ADSP2_LOCK_REGION_SHIFT; 2613 } 2614 regmap_write(regmap, lock_reg, code0); 2615 regmap_write(regmap, lock_reg, code1); 2616 lock_regions >>= 2; 2617 lock_reg += 2; 2618 } 2619 2620 return 0; 2621 } 2622 2623 static int cs_dsp_adsp2_enable_memory(struct cs_dsp *dsp) 2624 { 2625 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, 2626 ADSP2_MEM_ENA, ADSP2_MEM_ENA); 2627 } 2628 2629 static void cs_dsp_adsp2_disable_memory(struct cs_dsp *dsp) 2630 { 2631 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, 2632 ADSP2_MEM_ENA, 0); 2633 } 2634 2635 static void cs_dsp_adsp2_disable_core(struct cs_dsp *dsp) 2636 { 2637 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); 2638 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); 2639 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0); 2640 2641 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, 2642 ADSP2_SYS_ENA, 0); 2643 } 2644 2645 static void cs_dsp_adsp2v2_disable_core(struct cs_dsp *dsp) 2646 { 2647 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); 2648 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); 2649 regmap_write(dsp->regmap, dsp->base + ADSP2V2_WDMA_CONFIG_2, 0); 2650 } 2651 2652 static int cs_dsp_halo_configure_mpu(struct cs_dsp *dsp, unsigned int lock_regions) 2653 { 2654 struct reg_sequence config[] = { 2655 { dsp->base + HALO_MPU_LOCK_CONFIG, 0x5555 }, 2656 { dsp->base + HALO_MPU_LOCK_CONFIG, 0xAAAA }, 2657 { dsp->base + HALO_MPU_XMEM_ACCESS_0, 0xFFFFFFFF }, 2658 { dsp->base + HALO_MPU_YMEM_ACCESS_0, 0xFFFFFFFF }, 2659 { dsp->base + HALO_MPU_WINDOW_ACCESS_0, lock_regions }, 2660 { dsp->base + HALO_MPU_XREG_ACCESS_0, lock_regions }, 2661 { dsp->base + HALO_MPU_YREG_ACCESS_0, lock_regions }, 2662 { dsp->base + HALO_MPU_XMEM_ACCESS_1, 0xFFFFFFFF }, 2663 { dsp->base + HALO_MPU_YMEM_ACCESS_1, 0xFFFFFFFF }, 2664 { dsp->base + HALO_MPU_WINDOW_ACCESS_1, lock_regions }, 2665 { dsp->base + HALO_MPU_XREG_ACCESS_1, lock_regions }, 2666 { dsp->base + HALO_MPU_YREG_ACCESS_1, lock_regions }, 2667 { dsp->base + HALO_MPU_XMEM_ACCESS_2, 0xFFFFFFFF }, 2668 { dsp->base + HALO_MPU_YMEM_ACCESS_2, 0xFFFFFFFF }, 2669 { dsp->base + HALO_MPU_WINDOW_ACCESS_2, lock_regions }, 2670 { dsp->base + HALO_MPU_XREG_ACCESS_2, lock_regions }, 2671 { dsp->base + HALO_MPU_YREG_ACCESS_2, lock_regions }, 2672 { dsp->base + HALO_MPU_XMEM_ACCESS_3, 0xFFFFFFFF }, 2673 { dsp->base + HALO_MPU_YMEM_ACCESS_3, 0xFFFFFFFF }, 2674 { dsp->base + HALO_MPU_WINDOW_ACCESS_3, lock_regions }, 2675 { dsp->base + HALO_MPU_XREG_ACCESS_3, lock_regions }, 2676 { dsp->base + HALO_MPU_YREG_ACCESS_3, lock_regions }, 2677 { dsp->base + HALO_MPU_LOCK_CONFIG, 0 }, 2678 }; 2679 2680 return regmap_multi_reg_write(dsp->regmap, config, ARRAY_SIZE(config)); 2681 } 2682 2683 /** 2684 * cs_dsp_set_dspclk() - Applies the given frequency to the given cs_dsp 2685 * @dsp: pointer to DSP structure 2686 * @freq: clock rate to set 2687 * 2688 * This is only for use on ADSP2 cores. 2689 * 2690 * Return: Zero for success, a negative number on error. 2691 */ 2692 int cs_dsp_set_dspclk(struct cs_dsp *dsp, unsigned int freq) 2693 { 2694 int ret; 2695 2696 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CLOCKING, 2697 ADSP2_CLK_SEL_MASK, 2698 freq << ADSP2_CLK_SEL_SHIFT); 2699 if (ret) 2700 cs_dsp_err(dsp, "Failed to set clock rate: %d\n", ret); 2701 2702 return ret; 2703 } 2704 EXPORT_SYMBOL_NS_GPL(cs_dsp_set_dspclk, "FW_CS_DSP"); 2705 2706 static void cs_dsp_stop_watchdog(struct cs_dsp *dsp) 2707 { 2708 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG, 2709 ADSP2_WDT_ENA_MASK, 0); 2710 } 2711 2712 static void cs_dsp_halo_stop_watchdog(struct cs_dsp *dsp) 2713 { 2714 regmap_update_bits(dsp->regmap, dsp->base + HALO_WDT_CONTROL, 2715 HALO_WDT_EN_MASK, 0); 2716 } 2717 2718 /** 2719 * cs_dsp_power_up() - Downloads firmware to the DSP 2720 * @dsp: pointer to DSP structure 2721 * @wmfw_firmware: the firmware to be sent 2722 * @wmfw_filename: file name of firmware to be sent 2723 * @coeff_firmware: the coefficient data to be sent 2724 * @coeff_filename: file name of coefficient to data be sent 2725 * @fw_name: the user-friendly firmware name 2726 * 2727 * This function is used on ADSP2 and Halo DSP cores, it powers-up the DSP core 2728 * and downloads the firmware but does not start the firmware running. The 2729 * cs_dsp booted flag will be set once completed and if the core has a low-power 2730 * memory retention mode it will be put into this state after the firmware is 2731 * downloaded. 2732 * 2733 * Return: Zero for success, a negative number on error. 2734 */ 2735 int cs_dsp_power_up(struct cs_dsp *dsp, 2736 const struct firmware *wmfw_firmware, const char *wmfw_filename, 2737 const struct firmware *coeff_firmware, const char *coeff_filename, 2738 const char *fw_name) 2739 { 2740 int ret; 2741 2742 mutex_lock(&dsp->pwr_lock); 2743 2744 dsp->fw_name = fw_name; 2745 2746 if (dsp->ops->enable_memory) { 2747 ret = dsp->ops->enable_memory(dsp); 2748 if (ret != 0) 2749 goto err_mutex; 2750 } 2751 2752 if (dsp->ops->enable_core) { 2753 ret = dsp->ops->enable_core(dsp); 2754 if (ret != 0) 2755 goto err_mem; 2756 } 2757 2758 ret = cs_dsp_load(dsp, wmfw_firmware, wmfw_filename); 2759 if (ret != 0) 2760 goto err_ena; 2761 2762 ret = dsp->ops->setup_algs(dsp); 2763 if (ret != 0) 2764 goto err_ena; 2765 2766 ret = cs_dsp_load_coeff(dsp, coeff_firmware, coeff_filename); 2767 if (ret != 0) 2768 goto err_ena; 2769 2770 /* Initialize caches for enabled and unset controls */ 2771 ret = cs_dsp_coeff_init_control_caches(dsp); 2772 if (ret != 0) 2773 goto err_ena; 2774 2775 if (dsp->ops->disable_core) 2776 dsp->ops->disable_core(dsp); 2777 2778 dsp->booted = true; 2779 2780 mutex_unlock(&dsp->pwr_lock); 2781 2782 return 0; 2783 err_ena: 2784 if (dsp->ops->disable_core) 2785 dsp->ops->disable_core(dsp); 2786 err_mem: 2787 if (dsp->ops->disable_memory) 2788 dsp->ops->disable_memory(dsp); 2789 err_mutex: 2790 mutex_unlock(&dsp->pwr_lock); 2791 2792 return ret; 2793 } 2794 EXPORT_SYMBOL_NS_GPL(cs_dsp_power_up, "FW_CS_DSP"); 2795 2796 /** 2797 * cs_dsp_power_down() - Powers-down the DSP 2798 * @dsp: pointer to DSP structure 2799 * 2800 * cs_dsp_stop() must have been called before this function. The core will be 2801 * fully powered down and so the memory will not be retained. 2802 */ 2803 void cs_dsp_power_down(struct cs_dsp *dsp) 2804 { 2805 struct cs_dsp_coeff_ctl *ctl; 2806 2807 mutex_lock(&dsp->pwr_lock); 2808 2809 cs_dsp_debugfs_clear(dsp); 2810 2811 dsp->fw_id = 0; 2812 dsp->fw_id_version = 0; 2813 2814 dsp->booted = false; 2815 2816 if (dsp->ops->disable_memory) 2817 dsp->ops->disable_memory(dsp); 2818 2819 list_for_each_entry(ctl, &dsp->ctl_list, list) 2820 ctl->enabled = 0; 2821 2822 cs_dsp_free_alg_regions(dsp); 2823 2824 mutex_unlock(&dsp->pwr_lock); 2825 2826 cs_dsp_dbg(dsp, "Shutdown complete\n"); 2827 } 2828 EXPORT_SYMBOL_NS_GPL(cs_dsp_power_down, "FW_CS_DSP"); 2829 2830 static int cs_dsp_adsp2_start_core(struct cs_dsp *dsp) 2831 { 2832 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, 2833 ADSP2_CORE_ENA | ADSP2_START, 2834 ADSP2_CORE_ENA | ADSP2_START); 2835 } 2836 2837 static void cs_dsp_adsp2_stop_core(struct cs_dsp *dsp) 2838 { 2839 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, 2840 ADSP2_CORE_ENA | ADSP2_START, 0); 2841 } 2842 2843 /** 2844 * cs_dsp_run() - Starts the firmware running 2845 * @dsp: pointer to DSP structure 2846 * 2847 * cs_dsp_power_up() must have previously been called successfully. 2848 * 2849 * Return: Zero for success, a negative number on error. 2850 */ 2851 int cs_dsp_run(struct cs_dsp *dsp) 2852 { 2853 int ret; 2854 2855 mutex_lock(&dsp->pwr_lock); 2856 2857 if (!dsp->booted) { 2858 ret = -EIO; 2859 goto err; 2860 } 2861 2862 if (dsp->ops->enable_core) { 2863 ret = dsp->ops->enable_core(dsp); 2864 if (ret != 0) 2865 goto err; 2866 } 2867 2868 if (dsp->client_ops->pre_run) { 2869 ret = dsp->client_ops->pre_run(dsp); 2870 if (ret) 2871 goto err; 2872 } 2873 2874 /* Sync set controls */ 2875 ret = cs_dsp_coeff_sync_controls(dsp); 2876 if (ret != 0) 2877 goto err; 2878 2879 if (dsp->ops->lock_memory) { 2880 ret = dsp->ops->lock_memory(dsp, dsp->lock_regions); 2881 if (ret != 0) { 2882 cs_dsp_err(dsp, "Error configuring MPU: %d\n", ret); 2883 goto err; 2884 } 2885 } 2886 2887 if (dsp->ops->start_core) { 2888 ret = dsp->ops->start_core(dsp); 2889 if (ret != 0) 2890 goto err; 2891 } 2892 2893 dsp->running = true; 2894 2895 if (dsp->client_ops->post_run) { 2896 ret = dsp->client_ops->post_run(dsp); 2897 if (ret) 2898 goto err; 2899 } 2900 2901 mutex_unlock(&dsp->pwr_lock); 2902 2903 return 0; 2904 2905 err: 2906 if (dsp->ops->stop_core) 2907 dsp->ops->stop_core(dsp); 2908 if (dsp->ops->disable_core) 2909 dsp->ops->disable_core(dsp); 2910 mutex_unlock(&dsp->pwr_lock); 2911 2912 return ret; 2913 } 2914 EXPORT_SYMBOL_NS_GPL(cs_dsp_run, "FW_CS_DSP"); 2915 2916 /** 2917 * cs_dsp_stop() - Stops the firmware 2918 * @dsp: pointer to DSP structure 2919 * 2920 * Memory will not be disabled so firmware will remain loaded. 2921 */ 2922 void cs_dsp_stop(struct cs_dsp *dsp) 2923 { 2924 /* Tell the firmware to cleanup */ 2925 cs_dsp_signal_event_controls(dsp, CS_DSP_FW_EVENT_SHUTDOWN); 2926 2927 if (dsp->ops->stop_watchdog) 2928 dsp->ops->stop_watchdog(dsp); 2929 2930 /* Log firmware state, it can be useful for analysis */ 2931 if (dsp->ops->show_fw_status) 2932 dsp->ops->show_fw_status(dsp); 2933 2934 mutex_lock(&dsp->pwr_lock); 2935 2936 if (dsp->client_ops->pre_stop) 2937 dsp->client_ops->pre_stop(dsp); 2938 2939 dsp->running = false; 2940 2941 if (dsp->ops->stop_core) 2942 dsp->ops->stop_core(dsp); 2943 if (dsp->ops->disable_core) 2944 dsp->ops->disable_core(dsp); 2945 2946 if (dsp->client_ops->post_stop) 2947 dsp->client_ops->post_stop(dsp); 2948 2949 mutex_unlock(&dsp->pwr_lock); 2950 2951 cs_dsp_dbg(dsp, "Execution stopped\n"); 2952 } 2953 EXPORT_SYMBOL_NS_GPL(cs_dsp_stop, "FW_CS_DSP"); 2954 2955 static int cs_dsp_halo_start_core(struct cs_dsp *dsp) 2956 { 2957 int ret; 2958 2959 ret = regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, 2960 HALO_CORE_RESET | HALO_CORE_EN, 2961 HALO_CORE_RESET | HALO_CORE_EN); 2962 if (ret) 2963 return ret; 2964 2965 return regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, 2966 HALO_CORE_RESET, 0); 2967 } 2968 2969 static void cs_dsp_halo_stop_core(struct cs_dsp *dsp) 2970 { 2971 regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, 2972 HALO_CORE_EN, 0); 2973 2974 /* reset halo core with CORE_SOFT_RESET */ 2975 regmap_update_bits(dsp->regmap, dsp->base + HALO_CORE_SOFT_RESET, 2976 HALO_CORE_SOFT_RESET_MASK, 1); 2977 } 2978 2979 /** 2980 * cs_dsp_adsp2_init() - Initialise a cs_dsp structure representing a ADSP2 core 2981 * @dsp: pointer to DSP structure 2982 * 2983 * Return: Zero for success, a negative number on error. 2984 */ 2985 int cs_dsp_adsp2_init(struct cs_dsp *dsp) 2986 { 2987 int ret; 2988 2989 switch (dsp->rev) { 2990 case 0: 2991 /* 2992 * Disable the DSP memory by default when in reset for a small 2993 * power saving. 2994 */ 2995 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, 2996 ADSP2_MEM_ENA, 0); 2997 if (ret) { 2998 cs_dsp_err(dsp, 2999 "Failed to clear memory retention: %d\n", ret); 3000 return ret; 3001 } 3002 3003 dsp->ops = &cs_dsp_adsp2_ops[0]; 3004 break; 3005 case 1: 3006 dsp->ops = &cs_dsp_adsp2_ops[1]; 3007 break; 3008 default: 3009 dsp->ops = &cs_dsp_adsp2_ops[2]; 3010 break; 3011 } 3012 3013 return cs_dsp_common_init(dsp); 3014 } 3015 EXPORT_SYMBOL_NS_GPL(cs_dsp_adsp2_init, "FW_CS_DSP"); 3016 3017 /** 3018 * cs_dsp_halo_init() - Initialise a cs_dsp structure representing a HALO Core DSP 3019 * @dsp: pointer to DSP structure 3020 * 3021 * Return: Zero for success, a negative number on error. 3022 */ 3023 int cs_dsp_halo_init(struct cs_dsp *dsp) 3024 { 3025 if (dsp->no_core_startstop) 3026 dsp->ops = &cs_dsp_halo_ao_ops; 3027 else 3028 dsp->ops = &cs_dsp_halo_ops; 3029 3030 return cs_dsp_common_init(dsp); 3031 } 3032 EXPORT_SYMBOL_NS_GPL(cs_dsp_halo_init, "FW_CS_DSP"); 3033 3034 /** 3035 * cs_dsp_remove() - Clean a cs_dsp before deletion 3036 * @dsp: pointer to DSP structure 3037 */ 3038 void cs_dsp_remove(struct cs_dsp *dsp) 3039 { 3040 struct cs_dsp_coeff_ctl *ctl; 3041 3042 while (!list_empty(&dsp->ctl_list)) { 3043 ctl = list_first_entry(&dsp->ctl_list, struct cs_dsp_coeff_ctl, list); 3044 3045 if (dsp->client_ops->control_remove) 3046 dsp->client_ops->control_remove(ctl); 3047 3048 list_del(&ctl->list); 3049 cs_dsp_free_ctl_blk(ctl); 3050 } 3051 } 3052 EXPORT_SYMBOL_NS_GPL(cs_dsp_remove, "FW_CS_DSP"); 3053 3054 /** 3055 * cs_dsp_read_raw_data_block() - Reads a block of data from DSP memory 3056 * @dsp: pointer to DSP structure 3057 * @mem_type: the type of DSP memory containing the data to be read 3058 * @mem_addr: the address of the data within the memory region 3059 * @num_words: the length of the data to read 3060 * @data: a buffer to store the fetched data 3061 * 3062 * If this is used to read unpacked 24-bit memory, each 24-bit DSP word will 3063 * occupy 32-bits in data (MSbyte will be 0). This padding can be removed using 3064 * cs_dsp_remove_padding() 3065 * 3066 * Return: Zero for success, a negative number on error. 3067 */ 3068 int cs_dsp_read_raw_data_block(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, 3069 unsigned int num_words, __be32 *data) 3070 { 3071 struct cs_dsp_region const *mem = cs_dsp_find_region(dsp, mem_type); 3072 unsigned int reg; 3073 int ret; 3074 3075 lockdep_assert_held(&dsp->pwr_lock); 3076 3077 if (!mem) 3078 return -EINVAL; 3079 3080 reg = dsp->ops->region_to_reg(mem, mem_addr); 3081 3082 ret = regmap_raw_read(dsp->regmap, reg, data, 3083 sizeof(*data) * num_words); 3084 if (ret < 0) 3085 return ret; 3086 3087 return 0; 3088 } 3089 EXPORT_SYMBOL_NS_GPL(cs_dsp_read_raw_data_block, "FW_CS_DSP"); 3090 3091 /** 3092 * cs_dsp_read_data_word() - Reads a word from DSP memory 3093 * @dsp: pointer to DSP structure 3094 * @mem_type: the type of DSP memory containing the data to be read 3095 * @mem_addr: the address of the data within the memory region 3096 * @data: a buffer to store the fetched data 3097 * 3098 * Return: Zero for success, a negative number on error. 3099 */ 3100 int cs_dsp_read_data_word(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, u32 *data) 3101 { 3102 __be32 raw; 3103 int ret; 3104 3105 ret = cs_dsp_read_raw_data_block(dsp, mem_type, mem_addr, 1, &raw); 3106 if (ret < 0) 3107 return ret; 3108 3109 *data = be32_to_cpu(raw) & 0x00ffffffu; 3110 3111 return 0; 3112 } 3113 EXPORT_SYMBOL_NS_GPL(cs_dsp_read_data_word, "FW_CS_DSP"); 3114 3115 /** 3116 * cs_dsp_write_data_word() - Writes a word to DSP memory 3117 * @dsp: pointer to DSP structure 3118 * @mem_type: the type of DSP memory containing the data to be written 3119 * @mem_addr: the address of the data within the memory region 3120 * @data: the data to be written 3121 * 3122 * Return: Zero for success, a negative number on error. 3123 */ 3124 int cs_dsp_write_data_word(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, u32 data) 3125 { 3126 struct cs_dsp_region const *mem = cs_dsp_find_region(dsp, mem_type); 3127 __be32 val = cpu_to_be32(data & 0x00ffffffu); 3128 unsigned int reg; 3129 3130 lockdep_assert_held(&dsp->pwr_lock); 3131 3132 if (!mem) 3133 return -EINVAL; 3134 3135 reg = dsp->ops->region_to_reg(mem, mem_addr); 3136 3137 return regmap_raw_write(dsp->regmap, reg, &val, sizeof(val)); 3138 } 3139 EXPORT_SYMBOL_NS_GPL(cs_dsp_write_data_word, "FW_CS_DSP"); 3140 3141 /** 3142 * cs_dsp_remove_padding() - Convert unpacked words to packed bytes 3143 * @buf: buffer containing DSP words read from DSP memory 3144 * @nwords: number of words to convert 3145 * 3146 * DSP words from the register map have pad bytes and the data bytes 3147 * are in swapped order. This swaps to the native endian order and 3148 * strips the pad bytes. 3149 */ 3150 void cs_dsp_remove_padding(u32 *buf, int nwords) 3151 { 3152 const __be32 *pack_in = (__be32 *)buf; 3153 u8 *pack_out = (u8 *)buf; 3154 int i; 3155 3156 for (i = 0; i < nwords; i++) { 3157 u32 word = be32_to_cpu(*pack_in++); 3158 *pack_out++ = (u8)word; 3159 *pack_out++ = (u8)(word >> 8); 3160 *pack_out++ = (u8)(word >> 16); 3161 } 3162 } 3163 EXPORT_SYMBOL_NS_GPL(cs_dsp_remove_padding, "FW_CS_DSP"); 3164 3165 /** 3166 * cs_dsp_adsp2_bus_error() - Handle a DSP bus error interrupt 3167 * @dsp: pointer to DSP structure 3168 * 3169 * The firmware and DSP state will be logged for future analysis. 3170 */ 3171 void cs_dsp_adsp2_bus_error(struct cs_dsp *dsp) 3172 { 3173 unsigned int val; 3174 struct regmap *regmap = dsp->regmap; 3175 int ret = 0; 3176 3177 mutex_lock(&dsp->pwr_lock); 3178 3179 ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val); 3180 if (ret) { 3181 cs_dsp_err(dsp, 3182 "Failed to read Region Lock Ctrl register: %d\n", ret); 3183 goto error; 3184 } 3185 3186 if (val & ADSP2_WDT_TIMEOUT_STS_MASK) { 3187 cs_dsp_err(dsp, "watchdog timeout error\n"); 3188 dsp->ops->stop_watchdog(dsp); 3189 if (dsp->client_ops->watchdog_expired) 3190 dsp->client_ops->watchdog_expired(dsp); 3191 } 3192 3193 if (val & (ADSP2_ADDR_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) { 3194 if (val & ADSP2_ADDR_ERR_MASK) 3195 cs_dsp_err(dsp, "bus error: address error\n"); 3196 else 3197 cs_dsp_err(dsp, "bus error: region lock error\n"); 3198 3199 ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val); 3200 if (ret) { 3201 cs_dsp_err(dsp, 3202 "Failed to read Bus Err Addr register: %d\n", 3203 ret); 3204 goto error; 3205 } 3206 3207 cs_dsp_err(dsp, "bus error address = 0x%x\n", 3208 val & ADSP2_BUS_ERR_ADDR_MASK); 3209 3210 ret = regmap_read(regmap, 3211 dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR, 3212 &val); 3213 if (ret) { 3214 cs_dsp_err(dsp, 3215 "Failed to read Pmem Xmem Err Addr register: %d\n", 3216 ret); 3217 goto error; 3218 } 3219 3220 cs_dsp_err(dsp, "xmem error address = 0x%x\n", 3221 val & ADSP2_XMEM_ERR_ADDR_MASK); 3222 cs_dsp_err(dsp, "pmem error address = 0x%x\n", 3223 (val & ADSP2_PMEM_ERR_ADDR_MASK) >> 3224 ADSP2_PMEM_ERR_ADDR_SHIFT); 3225 } 3226 3227 regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, 3228 ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT); 3229 3230 error: 3231 mutex_unlock(&dsp->pwr_lock); 3232 } 3233 EXPORT_SYMBOL_NS_GPL(cs_dsp_adsp2_bus_error, "FW_CS_DSP"); 3234 3235 /** 3236 * cs_dsp_halo_bus_error() - Handle a DSP bus error interrupt 3237 * @dsp: pointer to DSP structure 3238 * 3239 * The firmware and DSP state will be logged for future analysis. 3240 */ 3241 void cs_dsp_halo_bus_error(struct cs_dsp *dsp) 3242 { 3243 struct regmap *regmap = dsp->regmap; 3244 unsigned int fault[6]; 3245 struct reg_sequence clear[] = { 3246 { dsp->base + HALO_MPU_XM_VIO_STATUS, 0x0 }, 3247 { dsp->base + HALO_MPU_YM_VIO_STATUS, 0x0 }, 3248 { dsp->base + HALO_MPU_PM_VIO_STATUS, 0x0 }, 3249 }; 3250 int ret; 3251 3252 mutex_lock(&dsp->pwr_lock); 3253 3254 ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_1, 3255 fault); 3256 if (ret) { 3257 cs_dsp_warn(dsp, "Failed to read AHB DEBUG_1: %d\n", ret); 3258 goto exit_unlock; 3259 } 3260 3261 cs_dsp_warn(dsp, "AHB: STATUS: 0x%x ADDR: 0x%x\n", 3262 *fault & HALO_AHBM_FLAGS_ERR_MASK, 3263 (*fault & HALO_AHBM_CORE_ERR_ADDR_MASK) >> 3264 HALO_AHBM_CORE_ERR_ADDR_SHIFT); 3265 3266 ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_0, 3267 fault); 3268 if (ret) { 3269 cs_dsp_warn(dsp, "Failed to read AHB DEBUG_0: %d\n", ret); 3270 goto exit_unlock; 3271 } 3272 3273 cs_dsp_warn(dsp, "AHB: SYS_ADDR: 0x%x\n", *fault); 3274 3275 ret = regmap_bulk_read(regmap, dsp->base + HALO_MPU_XM_VIO_ADDR, 3276 fault, ARRAY_SIZE(fault)); 3277 if (ret) { 3278 cs_dsp_warn(dsp, "Failed to read MPU fault info: %d\n", ret); 3279 goto exit_unlock; 3280 } 3281 3282 cs_dsp_warn(dsp, "XM: STATUS:0x%x ADDR:0x%x\n", fault[1], fault[0]); 3283 cs_dsp_warn(dsp, "YM: STATUS:0x%x ADDR:0x%x\n", fault[3], fault[2]); 3284 cs_dsp_warn(dsp, "PM: STATUS:0x%x ADDR:0x%x\n", fault[5], fault[4]); 3285 3286 ret = regmap_multi_reg_write(dsp->regmap, clear, ARRAY_SIZE(clear)); 3287 if (ret) 3288 cs_dsp_warn(dsp, "Failed to clear MPU status: %d\n", ret); 3289 3290 exit_unlock: 3291 mutex_unlock(&dsp->pwr_lock); 3292 } 3293 EXPORT_SYMBOL_NS_GPL(cs_dsp_halo_bus_error, "FW_CS_DSP"); 3294 3295 /** 3296 * cs_dsp_halo_wdt_expire() - Handle DSP watchdog expiry 3297 * @dsp: pointer to DSP structure 3298 * 3299 * This is logged for future analysis. 3300 */ 3301 void cs_dsp_halo_wdt_expire(struct cs_dsp *dsp) 3302 { 3303 mutex_lock(&dsp->pwr_lock); 3304 3305 cs_dsp_warn(dsp, "WDT Expiry Fault\n"); 3306 3307 dsp->ops->stop_watchdog(dsp); 3308 if (dsp->client_ops->watchdog_expired) 3309 dsp->client_ops->watchdog_expired(dsp); 3310 3311 mutex_unlock(&dsp->pwr_lock); 3312 } 3313 EXPORT_SYMBOL_NS_GPL(cs_dsp_halo_wdt_expire, "FW_CS_DSP"); 3314 3315 static const struct cs_dsp_ops cs_dsp_adsp1_ops = { 3316 .validate_version = cs_dsp_validate_version, 3317 .parse_sizes = cs_dsp_adsp1_parse_sizes, 3318 .region_to_reg = cs_dsp_region_to_reg, 3319 }; 3320 3321 static const struct cs_dsp_ops cs_dsp_adsp2_ops[] = { 3322 { 3323 .parse_sizes = cs_dsp_adsp2_parse_sizes, 3324 .validate_version = cs_dsp_validate_version, 3325 .setup_algs = cs_dsp_adsp2_setup_algs, 3326 .region_to_reg = cs_dsp_region_to_reg, 3327 3328 .show_fw_status = cs_dsp_adsp2_show_fw_status, 3329 3330 .enable_memory = cs_dsp_adsp2_enable_memory, 3331 .disable_memory = cs_dsp_adsp2_disable_memory, 3332 3333 .enable_core = cs_dsp_adsp2_enable_core, 3334 .disable_core = cs_dsp_adsp2_disable_core, 3335 3336 .start_core = cs_dsp_adsp2_start_core, 3337 .stop_core = cs_dsp_adsp2_stop_core, 3338 3339 }, 3340 { 3341 .parse_sizes = cs_dsp_adsp2_parse_sizes, 3342 .validate_version = cs_dsp_validate_version, 3343 .setup_algs = cs_dsp_adsp2_setup_algs, 3344 .region_to_reg = cs_dsp_region_to_reg, 3345 3346 .show_fw_status = cs_dsp_adsp2v2_show_fw_status, 3347 3348 .enable_memory = cs_dsp_adsp2_enable_memory, 3349 .disable_memory = cs_dsp_adsp2_disable_memory, 3350 .lock_memory = cs_dsp_adsp2_lock, 3351 3352 .enable_core = cs_dsp_adsp2v2_enable_core, 3353 .disable_core = cs_dsp_adsp2v2_disable_core, 3354 3355 .start_core = cs_dsp_adsp2_start_core, 3356 .stop_core = cs_dsp_adsp2_stop_core, 3357 }, 3358 { 3359 .parse_sizes = cs_dsp_adsp2_parse_sizes, 3360 .validate_version = cs_dsp_validate_version, 3361 .setup_algs = cs_dsp_adsp2_setup_algs, 3362 .region_to_reg = cs_dsp_region_to_reg, 3363 3364 .show_fw_status = cs_dsp_adsp2v2_show_fw_status, 3365 .stop_watchdog = cs_dsp_stop_watchdog, 3366 3367 .enable_memory = cs_dsp_adsp2_enable_memory, 3368 .disable_memory = cs_dsp_adsp2_disable_memory, 3369 .lock_memory = cs_dsp_adsp2_lock, 3370 3371 .enable_core = cs_dsp_adsp2v2_enable_core, 3372 .disable_core = cs_dsp_adsp2v2_disable_core, 3373 3374 .start_core = cs_dsp_adsp2_start_core, 3375 .stop_core = cs_dsp_adsp2_stop_core, 3376 }, 3377 }; 3378 3379 static const struct cs_dsp_ops cs_dsp_halo_ops = { 3380 .parse_sizes = cs_dsp_adsp2_parse_sizes, 3381 .validate_version = cs_dsp_halo_validate_version, 3382 .setup_algs = cs_dsp_halo_setup_algs, 3383 .region_to_reg = cs_dsp_halo_region_to_reg, 3384 3385 .show_fw_status = cs_dsp_halo_show_fw_status, 3386 .stop_watchdog = cs_dsp_halo_stop_watchdog, 3387 3388 .lock_memory = cs_dsp_halo_configure_mpu, 3389 3390 .start_core = cs_dsp_halo_start_core, 3391 .stop_core = cs_dsp_halo_stop_core, 3392 }; 3393 3394 static const struct cs_dsp_ops cs_dsp_halo_ao_ops = { 3395 .parse_sizes = cs_dsp_adsp2_parse_sizes, 3396 .validate_version = cs_dsp_halo_validate_version, 3397 .setup_algs = cs_dsp_halo_setup_algs, 3398 .region_to_reg = cs_dsp_halo_region_to_reg, 3399 .show_fw_status = cs_dsp_halo_show_fw_status, 3400 }; 3401 3402 /** 3403 * cs_dsp_chunk_write() - Format data to a DSP memory chunk 3404 * @ch: Pointer to the chunk structure 3405 * @nbits: Number of bits to write 3406 * @val: Value to write 3407 * 3408 * This function sequentially writes values into the format required for DSP 3409 * memory, it handles both inserting of the padding bytes and converting to 3410 * big endian. Note that data is only committed to the chunk when a whole DSP 3411 * words worth of data is available. 3412 * 3413 * Return: Zero for success, a negative number on error. 3414 */ 3415 int cs_dsp_chunk_write(struct cs_dsp_chunk *ch, int nbits, u32 val) 3416 { 3417 int nwrite, i; 3418 3419 nwrite = min(CS_DSP_DATA_WORD_BITS - ch->cachebits, nbits); 3420 3421 ch->cache <<= nwrite; 3422 ch->cache |= val >> (nbits - nwrite); 3423 ch->cachebits += nwrite; 3424 nbits -= nwrite; 3425 3426 if (ch->cachebits == CS_DSP_DATA_WORD_BITS) { 3427 if (cs_dsp_chunk_end(ch)) 3428 return -ENOSPC; 3429 3430 ch->cache &= 0xFFFFFF; 3431 for (i = 0; i < sizeof(ch->cache); i++, ch->cache <<= BITS_PER_BYTE) 3432 *ch->data++ = (ch->cache & 0xFF000000) >> CS_DSP_DATA_WORD_BITS; 3433 3434 ch->bytes += sizeof(ch->cache); 3435 ch->cachebits = 0; 3436 } 3437 3438 if (nbits) 3439 return cs_dsp_chunk_write(ch, nbits, val); 3440 3441 return 0; 3442 } 3443 EXPORT_SYMBOL_NS_GPL(cs_dsp_chunk_write, "FW_CS_DSP"); 3444 3445 /** 3446 * cs_dsp_chunk_flush() - Pad remaining data with zero and commit to chunk 3447 * @ch: Pointer to the chunk structure 3448 * 3449 * As cs_dsp_chunk_write only writes data when a whole DSP word is ready to 3450 * be written out it is possible that some data will remain in the cache, this 3451 * function will pad that data with zeros upto a whole DSP word and write out. 3452 * 3453 * Return: Zero for success, a negative number on error. 3454 */ 3455 int cs_dsp_chunk_flush(struct cs_dsp_chunk *ch) 3456 { 3457 if (!ch->cachebits) 3458 return 0; 3459 3460 return cs_dsp_chunk_write(ch, CS_DSP_DATA_WORD_BITS - ch->cachebits, 0); 3461 } 3462 EXPORT_SYMBOL_NS_GPL(cs_dsp_chunk_flush, "FW_CS_DSP"); 3463 3464 /** 3465 * cs_dsp_chunk_read() - Parse data from a DSP memory chunk 3466 * @ch: Pointer to the chunk structure 3467 * @nbits: Number of bits to read 3468 * 3469 * This function sequentially reads values from a DSP memory formatted buffer, 3470 * it handles both removing of the padding bytes and converting from big endian. 3471 * 3472 * Return: A negative number is returned on error, otherwise the read value. 3473 */ 3474 int cs_dsp_chunk_read(struct cs_dsp_chunk *ch, int nbits) 3475 { 3476 int nread, i; 3477 u32 result; 3478 3479 if (!ch->cachebits) { 3480 if (cs_dsp_chunk_end(ch)) 3481 return -ENOSPC; 3482 3483 ch->cache = 0; 3484 ch->cachebits = CS_DSP_DATA_WORD_BITS; 3485 3486 for (i = 0; i < sizeof(ch->cache); i++, ch->cache <<= BITS_PER_BYTE) 3487 ch->cache |= *ch->data++; 3488 3489 ch->bytes += sizeof(ch->cache); 3490 } 3491 3492 nread = min(ch->cachebits, nbits); 3493 nbits -= nread; 3494 3495 result = ch->cache >> ((sizeof(ch->cache) * BITS_PER_BYTE) - nread); 3496 ch->cache <<= nread; 3497 ch->cachebits -= nread; 3498 3499 if (nbits) 3500 result = (result << nbits) | cs_dsp_chunk_read(ch, nbits); 3501 3502 return result; 3503 } 3504 EXPORT_SYMBOL_NS_GPL(cs_dsp_chunk_read, "FW_CS_DSP"); 3505 3506 3507 struct cs_dsp_wseq_op { 3508 struct list_head list; 3509 u32 address; 3510 u32 data; 3511 u16 offset; 3512 u8 operation; 3513 }; 3514 3515 static void cs_dsp_wseq_clear(struct cs_dsp *dsp, struct cs_dsp_wseq *wseq) 3516 { 3517 struct cs_dsp_wseq_op *op, *op_tmp; 3518 3519 list_for_each_entry_safe(op, op_tmp, &wseq->ops, list) { 3520 list_del(&op->list); 3521 devm_kfree(dsp->dev, op); 3522 } 3523 } 3524 3525 static int cs_dsp_populate_wseq(struct cs_dsp *dsp, struct cs_dsp_wseq *wseq) 3526 { 3527 struct cs_dsp_wseq_op *op = NULL; 3528 struct cs_dsp_chunk chunk; 3529 u8 *words; 3530 int ret; 3531 3532 if (!wseq->ctl) { 3533 cs_dsp_err(dsp, "No control for write sequence\n"); 3534 return -EINVAL; 3535 } 3536 3537 words = kzalloc(wseq->ctl->len, GFP_KERNEL); 3538 if (!words) 3539 return -ENOMEM; 3540 3541 ret = cs_dsp_coeff_read_ctrl(wseq->ctl, 0, words, wseq->ctl->len); 3542 if (ret) { 3543 cs_dsp_err(dsp, "Failed to read %s: %d\n", wseq->ctl->subname, ret); 3544 goto err_free; 3545 } 3546 3547 INIT_LIST_HEAD(&wseq->ops); 3548 3549 chunk = cs_dsp_chunk(words, wseq->ctl->len); 3550 3551 while (!cs_dsp_chunk_end(&chunk)) { 3552 op = devm_kzalloc(dsp->dev, sizeof(*op), GFP_KERNEL); 3553 if (!op) { 3554 ret = -ENOMEM; 3555 goto err_free; 3556 } 3557 3558 op->offset = cs_dsp_chunk_bytes(&chunk); 3559 op->operation = cs_dsp_chunk_read(&chunk, 8); 3560 3561 switch (op->operation) { 3562 case CS_DSP_WSEQ_END: 3563 op->data = WSEQ_END_OF_SCRIPT; 3564 break; 3565 case CS_DSP_WSEQ_UNLOCK: 3566 op->data = cs_dsp_chunk_read(&chunk, 16); 3567 break; 3568 case CS_DSP_WSEQ_ADDR8: 3569 op->address = cs_dsp_chunk_read(&chunk, 8); 3570 op->data = cs_dsp_chunk_read(&chunk, 32); 3571 break; 3572 case CS_DSP_WSEQ_H16: 3573 case CS_DSP_WSEQ_L16: 3574 op->address = cs_dsp_chunk_read(&chunk, 24); 3575 op->data = cs_dsp_chunk_read(&chunk, 16); 3576 break; 3577 case CS_DSP_WSEQ_FULL: 3578 op->address = cs_dsp_chunk_read(&chunk, 32); 3579 op->data = cs_dsp_chunk_read(&chunk, 32); 3580 break; 3581 default: 3582 ret = -EINVAL; 3583 cs_dsp_err(dsp, "Unsupported op: %X\n", op->operation); 3584 devm_kfree(dsp->dev, op); 3585 goto err_free; 3586 } 3587 3588 list_add_tail(&op->list, &wseq->ops); 3589 3590 if (op->operation == CS_DSP_WSEQ_END) 3591 break; 3592 } 3593 3594 if (op && op->operation != CS_DSP_WSEQ_END) { 3595 cs_dsp_err(dsp, "%s missing end terminator\n", wseq->ctl->subname); 3596 ret = -ENOENT; 3597 } 3598 3599 err_free: 3600 kfree(words); 3601 3602 return ret; 3603 } 3604 3605 /** 3606 * cs_dsp_wseq_init() - Initialize write sequences contained within the loaded DSP firmware 3607 * @dsp: Pointer to DSP structure 3608 * @wseqs: List of write sequences to initialize 3609 * @num_wseqs: Number of write sequences to initialize 3610 * 3611 * Return: Zero for success, a negative number on error. 3612 */ 3613 int cs_dsp_wseq_init(struct cs_dsp *dsp, struct cs_dsp_wseq *wseqs, unsigned int num_wseqs) 3614 { 3615 int i, ret; 3616 3617 lockdep_assert_held(&dsp->pwr_lock); 3618 3619 for (i = 0; i < num_wseqs; i++) { 3620 ret = cs_dsp_populate_wseq(dsp, &wseqs[i]); 3621 if (ret) { 3622 cs_dsp_wseq_clear(dsp, &wseqs[i]); 3623 return ret; 3624 } 3625 } 3626 3627 return 0; 3628 } 3629 EXPORT_SYMBOL_NS_GPL(cs_dsp_wseq_init, "FW_CS_DSP"); 3630 3631 static struct cs_dsp_wseq_op *cs_dsp_wseq_find_op(u32 addr, u8 op_code, 3632 struct list_head *wseq_ops) 3633 { 3634 struct cs_dsp_wseq_op *op; 3635 3636 list_for_each_entry(op, wseq_ops, list) { 3637 if (op->operation == op_code && op->address == addr) 3638 return op; 3639 } 3640 3641 return NULL; 3642 } 3643 3644 /** 3645 * cs_dsp_wseq_write() - Add or update an entry in a write sequence 3646 * @dsp: Pointer to a DSP structure 3647 * @wseq: Write sequence to write to 3648 * @addr: Address of the register to be written to 3649 * @data: Data to be written 3650 * @op_code: The type of operation of the new entry 3651 * @update: If true, searches for the first entry in the write sequence with 3652 * the same address and op_code, and replaces it. If false, creates a new entry 3653 * at the tail 3654 * 3655 * This function formats register address and value pairs into the format 3656 * required for write sequence entries, and either updates or adds the 3657 * new entry into the write sequence. 3658 * 3659 * If update is set to true and no matching entry is found, it will add a new entry. 3660 * 3661 * Return: Zero for success, a negative number on error. 3662 */ 3663 int cs_dsp_wseq_write(struct cs_dsp *dsp, struct cs_dsp_wseq *wseq, 3664 u32 addr, u32 data, u8 op_code, bool update) 3665 { 3666 struct cs_dsp_wseq_op *op_end, *op_new = NULL; 3667 u32 words[WSEQ_OP_MAX_WORDS]; 3668 struct cs_dsp_chunk chunk; 3669 int new_op_size, ret; 3670 3671 if (update) 3672 op_new = cs_dsp_wseq_find_op(addr, op_code, &wseq->ops); 3673 3674 /* If entry to update is not found, treat it as a new operation */ 3675 if (!op_new) { 3676 op_end = cs_dsp_wseq_find_op(0, CS_DSP_WSEQ_END, &wseq->ops); 3677 if (!op_end) { 3678 cs_dsp_err(dsp, "Missing terminator for %s\n", wseq->ctl->subname); 3679 return -EINVAL; 3680 } 3681 3682 op_new = devm_kzalloc(dsp->dev, sizeof(*op_new), GFP_KERNEL); 3683 if (!op_new) 3684 return -ENOMEM; 3685 3686 op_new->operation = op_code; 3687 op_new->address = addr; 3688 op_new->offset = op_end->offset; 3689 update = false; 3690 } 3691 3692 op_new->data = data; 3693 3694 chunk = cs_dsp_chunk(words, sizeof(words)); 3695 cs_dsp_chunk_write(&chunk, 8, op_new->operation); 3696 3697 switch (op_code) { 3698 case CS_DSP_WSEQ_FULL: 3699 cs_dsp_chunk_write(&chunk, 32, op_new->address); 3700 cs_dsp_chunk_write(&chunk, 32, op_new->data); 3701 break; 3702 case CS_DSP_WSEQ_L16: 3703 case CS_DSP_WSEQ_H16: 3704 cs_dsp_chunk_write(&chunk, 24, op_new->address); 3705 cs_dsp_chunk_write(&chunk, 16, op_new->data); 3706 break; 3707 default: 3708 ret = -EINVAL; 3709 cs_dsp_err(dsp, "Operation %X not supported\n", op_code); 3710 goto op_new_free; 3711 } 3712 3713 new_op_size = cs_dsp_chunk_bytes(&chunk); 3714 3715 if (!update) { 3716 if (wseq->ctl->len - op_end->offset < new_op_size) { 3717 cs_dsp_err(dsp, "Not enough memory in %s for entry\n", wseq->ctl->subname); 3718 ret = -E2BIG; 3719 goto op_new_free; 3720 } 3721 3722 op_end->offset += new_op_size; 3723 3724 ret = cs_dsp_coeff_write_ctrl(wseq->ctl, op_end->offset / sizeof(u32), 3725 &op_end->data, sizeof(u32)); 3726 if (ret) 3727 goto op_new_free; 3728 3729 list_add_tail(&op_new->list, &op_end->list); 3730 } 3731 3732 ret = cs_dsp_coeff_write_ctrl(wseq->ctl, op_new->offset / sizeof(u32), 3733 words, new_op_size); 3734 if (ret) 3735 goto op_new_free; 3736 3737 return 0; 3738 3739 op_new_free: 3740 devm_kfree(dsp->dev, op_new); 3741 3742 return ret; 3743 } 3744 EXPORT_SYMBOL_NS_GPL(cs_dsp_wseq_write, "FW_CS_DSP"); 3745 3746 /** 3747 * cs_dsp_wseq_multi_write() - Add or update multiple entries in a write sequence 3748 * @dsp: Pointer to a DSP structure 3749 * @wseq: Write sequence to write to 3750 * @reg_seq: List of address-data pairs 3751 * @num_regs: Number of address-data pairs 3752 * @op_code: The types of operations of the new entries 3753 * @update: If true, searches for the first entry in the write sequence with 3754 * the same address and op_code, and replaces it. If false, creates a new entry 3755 * at the tail 3756 * 3757 * This function calls cs_dsp_wseq_write() for multiple address-data pairs. 3758 * 3759 * Return: Zero for success, a negative number on error. 3760 */ 3761 int cs_dsp_wseq_multi_write(struct cs_dsp *dsp, struct cs_dsp_wseq *wseq, 3762 const struct reg_sequence *reg_seq, int num_regs, 3763 u8 op_code, bool update) 3764 { 3765 int i, ret; 3766 3767 for (i = 0; i < num_regs; i++) { 3768 ret = cs_dsp_wseq_write(dsp, wseq, reg_seq[i].reg, 3769 reg_seq[i].def, op_code, update); 3770 if (ret) 3771 return ret; 3772 } 3773 3774 return 0; 3775 } 3776 EXPORT_SYMBOL_NS_GPL(cs_dsp_wseq_multi_write, "FW_CS_DSP"); 3777 3778 MODULE_DESCRIPTION("Cirrus Logic DSP Support"); 3779 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 3780 MODULE_LICENSE("GPL v2"); 3781