1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ADMV1013 driver
4 *
5 * Copyright 2021 Analog Devices Inc.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/bits.h>
10 #include <linux/clk.h>
11 #include <linux/device.h>
12 #include <linux/iio/iio.h>
13 #include <linux/module.h>
14 #include <linux/notifier.h>
15 #include <linux/property.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/spi/spi.h>
18 #include <linux/units.h>
19
20 #include <linux/unaligned.h>
21
22 /* ADMV1013 Register Map */
23 #define ADMV1013_REG_SPI_CONTROL 0x00
24 #define ADMV1013_REG_ALARM 0x01
25 #define ADMV1013_REG_ALARM_MASKS 0x02
26 #define ADMV1013_REG_ENABLE 0x03
27 #define ADMV1013_REG_LO_AMP_I 0x05
28 #define ADMV1013_REG_LO_AMP_Q 0x06
29 #define ADMV1013_REG_OFFSET_ADJUST_I 0x07
30 #define ADMV1013_REG_OFFSET_ADJUST_Q 0x08
31 #define ADMV1013_REG_QUAD 0x09
32 #define ADMV1013_REG_VVA_TEMP_COMP 0x0A
33
34 /* ADMV1013_REG_SPI_CONTROL Map */
35 #define ADMV1013_PARITY_EN_MSK BIT(15)
36 #define ADMV1013_SPI_SOFT_RESET_MSK BIT(14)
37 #define ADMV1013_CHIP_ID_MSK GENMASK(11, 4)
38 #define ADMV1013_CHIP_ID 0xA
39 #define ADMV1013_REVISION_ID_MSK GENMASK(3, 0)
40
41 /* ADMV1013_REG_ALARM Map */
42 #define ADMV1013_PARITY_ERROR_MSK BIT(15)
43 #define ADMV1013_TOO_FEW_ERRORS_MSK BIT(14)
44 #define ADMV1013_TOO_MANY_ERRORS_MSK BIT(13)
45 #define ADMV1013_ADDRESS_RANGE_ERROR_MSK BIT(12)
46
47 /* ADMV1013_REG_ENABLE Map */
48 #define ADMV1013_VGA_PD_MSK BIT(15)
49 #define ADMV1013_MIXER_PD_MSK BIT(14)
50 #define ADMV1013_QUAD_PD_MSK GENMASK(13, 11)
51 #define ADMV1013_BG_PD_MSK BIT(10)
52 #define ADMV1013_MIXER_IF_EN_MSK BIT(7)
53 #define ADMV1013_DET_EN_MSK BIT(5)
54
55 /* ADMV1013_REG_LO_AMP Map */
56 #define ADMV1013_LOAMP_PH_ADJ_FINE_MSK GENMASK(13, 7)
57 #define ADMV1013_MIXER_VGATE_MSK GENMASK(6, 0)
58
59 /* ADMV1013_REG_OFFSET_ADJUST Map */
60 #define ADMV1013_MIXER_OFF_ADJ_P_MSK GENMASK(15, 9)
61 #define ADMV1013_MIXER_OFF_ADJ_N_MSK GENMASK(8, 2)
62
63 /* ADMV1013_REG_QUAD Map */
64 #define ADMV1013_QUAD_SE_MODE_MSK GENMASK(9, 6)
65 #define ADMV1013_QUAD_FILTERS_MSK GENMASK(3, 0)
66
67 /* ADMV1013_REG_VVA_TEMP_COMP Map */
68 #define ADMV1013_VVA_TEMP_COMP_MSK GENMASK(15, 0)
69
70 /* ADMV1013 Miscellaneous Defines */
71 #define ADMV1013_READ BIT(7)
72 #define ADMV1013_REG_ADDR_READ_MSK GENMASK(6, 1)
73 #define ADMV1013_REG_ADDR_WRITE_MSK GENMASK(22, 17)
74 #define ADMV1013_REG_DATA_MSK GENMASK(16, 1)
75
76 enum {
77 ADMV1013_IQ_MODE,
78 ADMV1013_IF_MODE
79 };
80
81 enum {
82 ADMV1013_RFMOD_I_CALIBPHASE,
83 ADMV1013_RFMOD_Q_CALIBPHASE,
84 };
85
86 enum {
87 ADMV1013_SE_MODE_POS,
88 ADMV1013_SE_MODE_NEG,
89 ADMV1013_SE_MODE_DIFF,
90 };
91
92 struct admv1013_state {
93 struct spi_device *spi;
94 struct clk *clkin;
95 /* Protect against concurrent accesses to the device and to data */
96 struct mutex lock;
97 struct notifier_block nb;
98 unsigned int input_mode;
99 unsigned int quad_se_mode;
100 bool det_en;
101 u8 data[3] __aligned(IIO_DMA_MINALIGN);
102 };
103
__admv1013_spi_read(struct admv1013_state * st,unsigned int reg,unsigned int * val)104 static int __admv1013_spi_read(struct admv1013_state *st, unsigned int reg,
105 unsigned int *val)
106 {
107 int ret;
108 struct spi_transfer t = {0};
109
110 st->data[0] = ADMV1013_READ | FIELD_PREP(ADMV1013_REG_ADDR_READ_MSK, reg);
111 st->data[1] = 0x0;
112 st->data[2] = 0x0;
113
114 t.rx_buf = &st->data[0];
115 t.tx_buf = &st->data[0];
116 t.len = 3;
117
118 ret = spi_sync_transfer(st->spi, &t, 1);
119 if (ret)
120 return ret;
121
122 *val = FIELD_GET(ADMV1013_REG_DATA_MSK, get_unaligned_be24(&st->data[0]));
123
124 return ret;
125 }
126
admv1013_spi_read(struct admv1013_state * st,unsigned int reg,unsigned int * val)127 static int admv1013_spi_read(struct admv1013_state *st, unsigned int reg,
128 unsigned int *val)
129 {
130 int ret;
131
132 mutex_lock(&st->lock);
133 ret = __admv1013_spi_read(st, reg, val);
134 mutex_unlock(&st->lock);
135
136 return ret;
137 }
138
__admv1013_spi_write(struct admv1013_state * st,unsigned int reg,unsigned int val)139 static int __admv1013_spi_write(struct admv1013_state *st,
140 unsigned int reg,
141 unsigned int val)
142 {
143 put_unaligned_be24(FIELD_PREP(ADMV1013_REG_DATA_MSK, val) |
144 FIELD_PREP(ADMV1013_REG_ADDR_WRITE_MSK, reg), &st->data[0]);
145
146 return spi_write(st->spi, &st->data[0], 3);
147 }
148
admv1013_spi_write(struct admv1013_state * st,unsigned int reg,unsigned int val)149 static int admv1013_spi_write(struct admv1013_state *st, unsigned int reg,
150 unsigned int val)
151 {
152 int ret;
153
154 mutex_lock(&st->lock);
155 ret = __admv1013_spi_write(st, reg, val);
156 mutex_unlock(&st->lock);
157
158 return ret;
159 }
160
__admv1013_spi_update_bits(struct admv1013_state * st,unsigned int reg,unsigned int mask,unsigned int val)161 static int __admv1013_spi_update_bits(struct admv1013_state *st, unsigned int reg,
162 unsigned int mask, unsigned int val)
163 {
164 int ret;
165 unsigned int data, temp;
166
167 ret = __admv1013_spi_read(st, reg, &data);
168 if (ret)
169 return ret;
170
171 temp = (data & ~mask) | (val & mask);
172
173 return __admv1013_spi_write(st, reg, temp);
174 }
175
admv1013_spi_update_bits(struct admv1013_state * st,unsigned int reg,unsigned int mask,unsigned int val)176 static int admv1013_spi_update_bits(struct admv1013_state *st, unsigned int reg,
177 unsigned int mask, unsigned int val)
178 {
179 int ret;
180
181 mutex_lock(&st->lock);
182 ret = __admv1013_spi_update_bits(st, reg, mask, val);
183 mutex_unlock(&st->lock);
184
185 return ret;
186 }
187
admv1013_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)188 static int admv1013_read_raw(struct iio_dev *indio_dev,
189 struct iio_chan_spec const *chan,
190 int *val, int *val2, long info)
191 {
192 struct admv1013_state *st = iio_priv(indio_dev);
193 unsigned int data, addr;
194 int ret;
195
196 switch (info) {
197 case IIO_CHAN_INFO_CALIBBIAS:
198 switch (chan->channel) {
199 case IIO_MOD_I:
200 addr = ADMV1013_REG_OFFSET_ADJUST_I;
201 break;
202 case IIO_MOD_Q:
203 addr = ADMV1013_REG_OFFSET_ADJUST_Q;
204 break;
205 default:
206 return -EINVAL;
207 }
208
209 ret = admv1013_spi_read(st, addr, &data);
210 if (ret)
211 return ret;
212
213 if (!chan->channel)
214 *val = FIELD_GET(ADMV1013_MIXER_OFF_ADJ_P_MSK, data);
215 else
216 *val = FIELD_GET(ADMV1013_MIXER_OFF_ADJ_N_MSK, data);
217
218 return IIO_VAL_INT;
219 default:
220 return -EINVAL;
221 }
222 }
223
admv1013_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)224 static int admv1013_write_raw(struct iio_dev *indio_dev,
225 struct iio_chan_spec const *chan,
226 int val, int val2, long info)
227 {
228 struct admv1013_state *st = iio_priv(indio_dev);
229 unsigned int addr, data, msk;
230
231 switch (info) {
232 case IIO_CHAN_INFO_CALIBBIAS:
233 switch (chan->channel2) {
234 case IIO_MOD_I:
235 addr = ADMV1013_REG_OFFSET_ADJUST_I;
236 break;
237 case IIO_MOD_Q:
238 addr = ADMV1013_REG_OFFSET_ADJUST_Q;
239 break;
240 default:
241 return -EINVAL;
242 }
243
244 if (!chan->channel) {
245 msk = ADMV1013_MIXER_OFF_ADJ_P_MSK;
246 data = FIELD_PREP(ADMV1013_MIXER_OFF_ADJ_P_MSK, val);
247 } else {
248 msk = ADMV1013_MIXER_OFF_ADJ_N_MSK;
249 data = FIELD_PREP(ADMV1013_MIXER_OFF_ADJ_N_MSK, val);
250 }
251
252 return admv1013_spi_update_bits(st, addr, msk, data);
253 default:
254 return -EINVAL;
255 }
256 }
257
admv1013_read(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,char * buf)258 static ssize_t admv1013_read(struct iio_dev *indio_dev,
259 uintptr_t private,
260 const struct iio_chan_spec *chan,
261 char *buf)
262 {
263 struct admv1013_state *st = iio_priv(indio_dev);
264 unsigned int data, addr;
265 int ret;
266
267 switch ((u32)private) {
268 case ADMV1013_RFMOD_I_CALIBPHASE:
269 addr = ADMV1013_REG_LO_AMP_I;
270 break;
271 case ADMV1013_RFMOD_Q_CALIBPHASE:
272 addr = ADMV1013_REG_LO_AMP_Q;
273 break;
274 default:
275 return -EINVAL;
276 }
277
278 ret = admv1013_spi_read(st, addr, &data);
279 if (ret)
280 return ret;
281
282 data = FIELD_GET(ADMV1013_LOAMP_PH_ADJ_FINE_MSK, data);
283
284 return sysfs_emit(buf, "%u\n", data);
285 }
286
admv1013_write(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)287 static ssize_t admv1013_write(struct iio_dev *indio_dev,
288 uintptr_t private,
289 const struct iio_chan_spec *chan,
290 const char *buf, size_t len)
291 {
292 struct admv1013_state *st = iio_priv(indio_dev);
293 unsigned int data;
294 int ret;
295
296 ret = kstrtou32(buf, 10, &data);
297 if (ret)
298 return ret;
299
300 data = FIELD_PREP(ADMV1013_LOAMP_PH_ADJ_FINE_MSK, data);
301
302 switch ((u32)private) {
303 case ADMV1013_RFMOD_I_CALIBPHASE:
304 ret = admv1013_spi_update_bits(st, ADMV1013_REG_LO_AMP_I,
305 ADMV1013_LOAMP_PH_ADJ_FINE_MSK,
306 data);
307 if (ret)
308 return ret;
309 break;
310 case ADMV1013_RFMOD_Q_CALIBPHASE:
311 ret = admv1013_spi_update_bits(st, ADMV1013_REG_LO_AMP_Q,
312 ADMV1013_LOAMP_PH_ADJ_FINE_MSK,
313 data);
314 if (ret)
315 return ret;
316 break;
317 default:
318 return -EINVAL;
319 }
320
321 return len;
322 }
323
admv1013_update_quad_filters(struct admv1013_state * st)324 static int admv1013_update_quad_filters(struct admv1013_state *st)
325 {
326 unsigned int filt_raw;
327 u64 rate = clk_get_rate(st->clkin);
328
329 if (rate >= (5400 * HZ_PER_MHZ) && rate <= (7000 * HZ_PER_MHZ))
330 filt_raw = 15;
331 else if (rate >= (5400 * HZ_PER_MHZ) && rate <= (8000 * HZ_PER_MHZ))
332 filt_raw = 10;
333 else if (rate >= (6600 * HZ_PER_MHZ) && rate <= (9200 * HZ_PER_MHZ))
334 filt_raw = 5;
335 else
336 filt_raw = 0;
337
338 return __admv1013_spi_update_bits(st, ADMV1013_REG_QUAD,
339 ADMV1013_QUAD_FILTERS_MSK,
340 FIELD_PREP(ADMV1013_QUAD_FILTERS_MSK, filt_raw));
341 }
342
admv1013_update_mixer_vgate(struct admv1013_state * st,int vcm)343 static int admv1013_update_mixer_vgate(struct admv1013_state *st, int vcm)
344 {
345 unsigned int mixer_vgate;
346
347 if (vcm <= 1800000)
348 mixer_vgate = (2389 * vcm / 1000000 + 8100) / 100;
349 else if (vcm > 1800000 && vcm <= 2600000)
350 mixer_vgate = (2375 * vcm / 1000000 + 125) / 100;
351 else
352 return -EINVAL;
353
354 return __admv1013_spi_update_bits(st, ADMV1013_REG_LO_AMP_I,
355 ADMV1013_MIXER_VGATE_MSK,
356 FIELD_PREP(ADMV1013_MIXER_VGATE_MSK, mixer_vgate));
357 }
358
admv1013_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int write_val,unsigned int * read_val)359 static int admv1013_reg_access(struct iio_dev *indio_dev,
360 unsigned int reg,
361 unsigned int write_val,
362 unsigned int *read_val)
363 {
364 struct admv1013_state *st = iio_priv(indio_dev);
365
366 if (read_val)
367 return admv1013_spi_read(st, reg, read_val);
368 else
369 return admv1013_spi_write(st, reg, write_val);
370 }
371
372 static const struct iio_info admv1013_info = {
373 .read_raw = admv1013_read_raw,
374 .write_raw = admv1013_write_raw,
375 .debugfs_reg_access = &admv1013_reg_access,
376 };
377
378 static const char * const admv1013_vcc_regs[] = {
379 "vcc-drv", "vcc2-drv", "vcc-vva", "vcc-amp1", "vcc-amp2",
380 "vcc-env", "vcc-bg", "vcc-bg2", "vcc-mixer", "vcc-quad"
381 };
382
admv1013_freq_change(struct notifier_block * nb,unsigned long action,void * data)383 static int admv1013_freq_change(struct notifier_block *nb, unsigned long action, void *data)
384 {
385 struct admv1013_state *st = container_of(nb, struct admv1013_state, nb);
386 int ret;
387
388 if (action == POST_RATE_CHANGE) {
389 mutex_lock(&st->lock);
390 ret = notifier_from_errno(admv1013_update_quad_filters(st));
391 mutex_unlock(&st->lock);
392 return ret;
393 }
394
395 return NOTIFY_OK;
396 }
397
398 #define _ADMV1013_EXT_INFO(_name, _shared, _ident) { \
399 .name = _name, \
400 .read = admv1013_read, \
401 .write = admv1013_write, \
402 .private = _ident, \
403 .shared = _shared, \
404 }
405
406 static const struct iio_chan_spec_ext_info admv1013_ext_info[] = {
407 _ADMV1013_EXT_INFO("i_calibphase", IIO_SEPARATE, ADMV1013_RFMOD_I_CALIBPHASE),
408 _ADMV1013_EXT_INFO("q_calibphase", IIO_SEPARATE, ADMV1013_RFMOD_Q_CALIBPHASE),
409 { }
410 };
411
412 #define ADMV1013_CHAN_PHASE(_channel, _channel2, _admv1013_ext_info) { \
413 .type = IIO_ALTVOLTAGE, \
414 .output = 0, \
415 .indexed = 1, \
416 .channel2 = _channel2, \
417 .channel = _channel, \
418 .differential = 1, \
419 .ext_info = _admv1013_ext_info, \
420 }
421
422 #define ADMV1013_CHAN_CALIB(_channel, rf_comp) { \
423 .type = IIO_ALTVOLTAGE, \
424 .output = 0, \
425 .indexed = 1, \
426 .channel = _channel, \
427 .channel2 = IIO_MOD_##rf_comp, \
428 .info_mask_separate = BIT(IIO_CHAN_INFO_CALIBBIAS), \
429 }
430
431 static const struct iio_chan_spec admv1013_channels[] = {
432 ADMV1013_CHAN_PHASE(0, 1, admv1013_ext_info),
433 ADMV1013_CHAN_CALIB(0, I),
434 ADMV1013_CHAN_CALIB(0, Q),
435 ADMV1013_CHAN_CALIB(1, I),
436 ADMV1013_CHAN_CALIB(1, Q),
437 };
438
admv1013_init(struct admv1013_state * st,int vcm_uv)439 static int admv1013_init(struct admv1013_state *st, int vcm_uv)
440 {
441 int ret;
442 unsigned int data;
443 struct device *dev = &st->spi->dev;
444
445 /* Perform a software reset */
446 ret = __admv1013_spi_update_bits(st, ADMV1013_REG_SPI_CONTROL,
447 ADMV1013_SPI_SOFT_RESET_MSK,
448 FIELD_PREP(ADMV1013_SPI_SOFT_RESET_MSK, 1));
449 if (ret)
450 return ret;
451
452 ret = __admv1013_spi_update_bits(st, ADMV1013_REG_SPI_CONTROL,
453 ADMV1013_SPI_SOFT_RESET_MSK,
454 FIELD_PREP(ADMV1013_SPI_SOFT_RESET_MSK, 0));
455 if (ret)
456 return ret;
457
458 ret = __admv1013_spi_read(st, ADMV1013_REG_SPI_CONTROL, &data);
459 if (ret)
460 return ret;
461
462 data = FIELD_GET(ADMV1013_CHIP_ID_MSK, data);
463 if (data != ADMV1013_CHIP_ID)
464 return dev_err_probe(dev, -EINVAL, "Invalid Chip ID.\n");
465
466 ret = __admv1013_spi_write(st, ADMV1013_REG_VVA_TEMP_COMP, 0xE700);
467 if (ret)
468 return ret;
469
470 switch (st->quad_se_mode) {
471 case ADMV1013_SE_MODE_POS:
472 data = 6;
473 break;
474 case ADMV1013_SE_MODE_NEG:
475 data = 9;
476 break;
477 case ADMV1013_SE_MODE_DIFF:
478 data = 12;
479 break;
480 default:
481 return -EINVAL;
482 }
483
484 ret = __admv1013_spi_update_bits(st, ADMV1013_REG_QUAD,
485 ADMV1013_QUAD_SE_MODE_MSK,
486 FIELD_PREP(ADMV1013_QUAD_SE_MODE_MSK, data));
487 if (ret)
488 return ret;
489
490 ret = admv1013_update_mixer_vgate(st, vcm_uv);
491 if (ret)
492 return ret;
493
494 ret = admv1013_update_quad_filters(st);
495 if (ret)
496 return ret;
497
498 return __admv1013_spi_update_bits(st, ADMV1013_REG_ENABLE,
499 ADMV1013_DET_EN_MSK |
500 ADMV1013_MIXER_IF_EN_MSK,
501 st->det_en |
502 st->input_mode);
503 }
504
admv1013_powerdown(void * data)505 static void admv1013_powerdown(void *data)
506 {
507 unsigned int enable_reg, enable_reg_msk;
508
509 /* Disable all components in the Enable Register */
510 enable_reg_msk = ADMV1013_VGA_PD_MSK |
511 ADMV1013_MIXER_PD_MSK |
512 ADMV1013_QUAD_PD_MSK |
513 ADMV1013_BG_PD_MSK |
514 ADMV1013_MIXER_IF_EN_MSK |
515 ADMV1013_DET_EN_MSK;
516
517 enable_reg = FIELD_PREP(ADMV1013_VGA_PD_MSK, 1) |
518 FIELD_PREP(ADMV1013_MIXER_PD_MSK, 1) |
519 FIELD_PREP(ADMV1013_QUAD_PD_MSK, 7) |
520 FIELD_PREP(ADMV1013_BG_PD_MSK, 1) |
521 FIELD_PREP(ADMV1013_MIXER_IF_EN_MSK, 0) |
522 FIELD_PREP(ADMV1013_DET_EN_MSK, 0);
523
524 admv1013_spi_update_bits(data, ADMV1013_REG_ENABLE, enable_reg_msk, enable_reg);
525 }
526
527 static const char * const admv1013_input_modes[] = {
528 [ADMV1013_IQ_MODE] = "iq",
529 [ADMV1013_IF_MODE] = "if",
530 };
531
532 static const char * const admv1013_quad_se_modes[] = {
533 [ADMV1013_SE_MODE_POS] = "se-pos",
534 [ADMV1013_SE_MODE_NEG] = "se-neg",
535 [ADMV1013_SE_MODE_DIFF] = "diff",
536 };
537
admv1013_properties_parse(struct admv1013_state * st)538 static int admv1013_properties_parse(struct admv1013_state *st)
539 {
540 int ret;
541 struct device *dev = &st->spi->dev;
542
543 st->det_en = device_property_read_bool(dev, "adi,detector-enable");
544
545 ret = device_property_match_property_string(dev, "adi,input-mode",
546 admv1013_input_modes,
547 ARRAY_SIZE(admv1013_input_modes));
548 st->input_mode = ret >= 0 ? ret : ADMV1013_IQ_MODE;
549
550 ret = device_property_match_property_string(dev, "adi,quad-se-mode",
551 admv1013_quad_se_modes,
552 ARRAY_SIZE(admv1013_quad_se_modes));
553 st->quad_se_mode = ret >= 0 ? ret : ADMV1013_SE_MODE_DIFF;
554
555 ret = devm_regulator_bulk_get_enable(dev,
556 ARRAY_SIZE(admv1013_vcc_regs),
557 admv1013_vcc_regs);
558 if (ret) {
559 dev_err_probe(dev, ret,
560 "Failed to request VCC regulators\n");
561 return ret;
562 }
563
564 return 0;
565 }
566
admv1013_probe(struct spi_device * spi)567 static int admv1013_probe(struct spi_device *spi)
568 {
569 struct iio_dev *indio_dev;
570 struct admv1013_state *st;
571 struct device *dev = &spi->dev;
572 int ret, vcm_uv;
573
574 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
575 if (!indio_dev)
576 return -ENOMEM;
577
578 st = iio_priv(indio_dev);
579
580 indio_dev->info = &admv1013_info;
581 indio_dev->name = "admv1013";
582 indio_dev->channels = admv1013_channels;
583 indio_dev->num_channels = ARRAY_SIZE(admv1013_channels);
584
585 st->spi = spi;
586
587 ret = admv1013_properties_parse(st);
588 if (ret)
589 return ret;
590
591 ret = devm_regulator_get_enable_read_voltage(dev, "vcm");
592 if (ret < 0)
593 return dev_err_probe(dev, ret,
594 "failed to get the common-mode voltage\n");
595
596 vcm_uv = ret;
597
598 st->clkin = devm_clk_get_enabled(dev, "lo_in");
599 if (IS_ERR(st->clkin))
600 return dev_err_probe(dev, PTR_ERR(st->clkin),
601 "failed to get the LO input clock\n");
602
603 st->nb.notifier_call = admv1013_freq_change;
604 ret = devm_clk_notifier_register(dev, st->clkin, &st->nb);
605 if (ret)
606 return ret;
607
608 mutex_init(&st->lock);
609
610 ret = admv1013_init(st, vcm_uv);
611 if (ret)
612 return dev_err_probe(dev, ret, "admv1013 init failed\n");
613
614 ret = devm_add_action_or_reset(dev, admv1013_powerdown, st);
615 if (ret)
616 return ret;
617
618 return devm_iio_device_register(dev, indio_dev);
619 }
620
621 static const struct spi_device_id admv1013_id[] = {
622 { .name = "admv1013" },
623 { }
624 };
625 MODULE_DEVICE_TABLE(spi, admv1013_id);
626
627 static const struct of_device_id admv1013_of_match[] = {
628 { .compatible = "adi,admv1013" },
629 { }
630 };
631 MODULE_DEVICE_TABLE(of, admv1013_of_match);
632
633 static struct spi_driver admv1013_driver = {
634 .driver = {
635 .name = "admv1013",
636 .of_match_table = admv1013_of_match,
637 },
638 .probe = admv1013_probe,
639 .id_table = admv1013_id,
640 };
641 module_spi_driver(admv1013_driver);
642
643 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com");
644 MODULE_DESCRIPTION("Analog Devices ADMV1013");
645 MODULE_LICENSE("GPL v2");
646