1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2020 Linaro Limited
4 *
5 * Based on original driver:
6 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
7 *
8 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/iio/adc/qcom-vadc-common.h>
13 #include <linux/iio/consumer.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/regmap.h>
19 #include <linux/thermal.h>
20
21 #include <linux/unaligned.h>
22
23 #include "../thermal_hwmon.h"
24
25 /*
26 * Thermal monitoring block consists of 8 (ADC_TM5_NUM_CHANNELS) channels. Each
27 * channel is programmed to use one of ADC channels for voltage comparison.
28 * Voltages are programmed using ADC codes, so we have to convert temp to
29 * voltage and then to ADC code value.
30 *
31 * Configuration of TM channels must match configuration of corresponding ADC
32 * channels.
33 */
34
35 #define ADC5_MAX_CHANNEL 0xc0
36 #define ADC_TM5_NUM_CHANNELS 8
37
38 #define ADC_TM5_STATUS_LOW 0x0a
39
40 #define ADC_TM5_STATUS_HIGH 0x0b
41
42 #define ADC_TM5_NUM_BTM 0x0f
43
44 #define ADC_TM5_ADC_DIG_PARAM 0x42
45
46 #define ADC_TM5_FAST_AVG_CTL (ADC_TM5_ADC_DIG_PARAM + 1)
47 #define ADC_TM5_FAST_AVG_EN BIT(7)
48
49 #define ADC_TM5_MEAS_INTERVAL_CTL (ADC_TM5_ADC_DIG_PARAM + 2)
50 #define ADC_TM5_TIMER1 3 /* 3.9ms */
51
52 #define ADC_TM5_MEAS_INTERVAL_CTL2 (ADC_TM5_ADC_DIG_PARAM + 3)
53 #define ADC_TM5_MEAS_INTERVAL_CTL2_MASK 0xf0
54 #define ADC_TM5_TIMER2 10 /* 1 second */
55 #define ADC_TM5_MEAS_INTERVAL_CTL3_MASK 0xf
56 #define ADC_TM5_TIMER3 4 /* 4 second */
57
58 #define ADC_TM_EN_CTL1 0x46
59 #define ADC_TM_EN BIT(7)
60 #define ADC_TM_CONV_REQ 0x47
61 #define ADC_TM_CONV_REQ_EN BIT(7)
62
63 #define ADC_TM5_M_CHAN_BASE 0x60
64
65 #define ADC_TM5_M_ADC_CH_SEL_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 0)
66 #define ADC_TM5_M_LOW_THR0(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 1)
67 #define ADC_TM5_M_LOW_THR1(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 2)
68 #define ADC_TM5_M_HIGH_THR0(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 3)
69 #define ADC_TM5_M_HIGH_THR1(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 4)
70 #define ADC_TM5_M_MEAS_INTERVAL_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 5)
71 #define ADC_TM5_M_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 6)
72 #define ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK 0xf
73 #define ADC_TM5_M_CTL_CAL_SEL_MASK 0x30
74 #define ADC_TM5_M_CTL_CAL_VAL 0x40
75 #define ADC_TM5_M_EN(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 7)
76 #define ADC_TM5_M_MEAS_EN BIT(7)
77 #define ADC_TM5_M_HIGH_THR_INT_EN BIT(1)
78 #define ADC_TM5_M_LOW_THR_INT_EN BIT(0)
79
80 #define ADC_TM_GEN2_STATUS1 0x08
81 #define ADC_TM_GEN2_STATUS_LOW_SET 0x09
82 #define ADC_TM_GEN2_STATUS_LOW_CLR 0x0a
83 #define ADC_TM_GEN2_STATUS_HIGH_SET 0x0b
84 #define ADC_TM_GEN2_STATUS_HIGH_CLR 0x0c
85
86 #define ADC_TM_GEN2_CFG_HS_SET 0x0d
87 #define ADC_TM_GEN2_CFG_HS_FLAG BIT(0)
88 #define ADC_TM_GEN2_CFG_HS_CLR 0x0e
89
90 #define ADC_TM_GEN2_SID 0x40
91
92 #define ADC_TM_GEN2_CH_CTL 0x41
93 #define ADC_TM_GEN2_TM_CH_SEL GENMASK(7, 5)
94 #define ADC_TM_GEN2_MEAS_INT_SEL GENMASK(3, 2)
95
96 #define ADC_TM_GEN2_ADC_DIG_PARAM 0x42
97 #define ADC_TM_GEN2_CTL_CAL_SEL GENMASK(5, 4)
98 #define ADC_TM_GEN2_CTL_DEC_RATIO_MASK GENMASK(3, 2)
99
100 #define ADC_TM_GEN2_FAST_AVG_CTL 0x43
101 #define ADC_TM_GEN2_FAST_AVG_EN BIT(7)
102
103 #define ADC_TM_GEN2_ADC_CH_SEL_CTL 0x44
104
105 #define ADC_TM_GEN2_DELAY_CTL 0x45
106 #define ADC_TM_GEN2_HW_SETTLE_DELAY GENMASK(3, 0)
107
108 #define ADC_TM_GEN2_EN_CTL1 0x46
109 #define ADC_TM_GEN2_EN BIT(7)
110
111 #define ADC_TM_GEN2_CONV_REQ 0x47
112 #define ADC_TM_GEN2_CONV_REQ_EN BIT(7)
113
114 #define ADC_TM_GEN2_LOW_THR0 0x49
115 #define ADC_TM_GEN2_LOW_THR1 0x4a
116 #define ADC_TM_GEN2_HIGH_THR0 0x4b
117 #define ADC_TM_GEN2_HIGH_THR1 0x4c
118 #define ADC_TM_GEN2_LOWER_MASK(n) ((n) & GENMASK(7, 0))
119 #define ADC_TM_GEN2_UPPER_MASK(n) (((n) & GENMASK(15, 8)) >> 8)
120
121 #define ADC_TM_GEN2_MEAS_IRQ_EN 0x4d
122 #define ADC_TM_GEN2_MEAS_EN BIT(7)
123 #define ADC_TM5_GEN2_HIGH_THR_INT_EN BIT(1)
124 #define ADC_TM5_GEN2_LOW_THR_INT_EN BIT(0)
125
126 #define ADC_TM_GEN2_MEAS_INT_LSB 0x50
127 #define ADC_TM_GEN2_MEAS_INT_MSB 0x51
128 #define ADC_TM_GEN2_MEAS_INT_MODE 0x52
129
130 #define ADC_TM_GEN2_Mn_DATA0(n) ((n * 2) + 0xa0)
131 #define ADC_TM_GEN2_Mn_DATA1(n) ((n * 2) + 0xa1)
132 #define ADC_TM_GEN2_DATA_SHIFT 8
133
134 enum adc5_timer_select {
135 ADC5_TIMER_SEL_1 = 0,
136 ADC5_TIMER_SEL_2,
137 ADC5_TIMER_SEL_3,
138 ADC5_TIMER_SEL_NONE,
139 };
140
141 enum adc5_gen {
142 ADC_TM5,
143 ADC_TM_HC,
144 ADC_TM5_GEN2,
145 ADC_TM5_MAX
146 };
147
148 enum adc_tm5_cal_method {
149 ADC_TM5_NO_CAL = 0,
150 ADC_TM5_RATIOMETRIC_CAL,
151 ADC_TM5_ABSOLUTE_CAL
152 };
153
154 enum adc_tm_gen2_time_select {
155 MEAS_INT_50MS = 0,
156 MEAS_INT_100MS,
157 MEAS_INT_1S,
158 MEAS_INT_SET,
159 MEAS_INT_NONE,
160 };
161
162 struct adc_tm5_chip;
163 struct adc_tm5_channel;
164
165 struct adc_tm5_data {
166 const u32 full_scale_code_volt;
167 unsigned int *decimation;
168 unsigned int *hw_settle;
169 int (*disable_channel)(struct adc_tm5_channel *channel);
170 int (*configure)(struct adc_tm5_channel *channel, int low, int high);
171 irqreturn_t (*isr)(int irq, void *data);
172 int (*init)(struct adc_tm5_chip *chip);
173 char *irq_name;
174 int gen;
175 };
176
177 /**
178 * struct adc_tm5_channel - ADC Thermal Monitoring channel data.
179 * @channel: channel number.
180 * @adc_channel: corresponding ADC channel number.
181 * @cal_method: calibration method.
182 * @prescale: channel scaling performed on the input signal.
183 * @hw_settle_time: the time between AMUX being configured and the
184 * start of conversion.
185 * @decimation: sampling rate supported for the channel.
186 * @avg_samples: ability to provide single result from the ADC
187 * that is an average of multiple measurements.
188 * @high_thr_en: channel upper voltage threshold enable state.
189 * @low_thr_en: channel lower voltage threshold enable state.
190 * @meas_en: recurring measurement enable state
191 * @iio: IIO channel instance used by this channel.
192 * @chip: ADC TM chip instance.
193 * @tzd: thermal zone device used by this channel.
194 */
195 struct adc_tm5_channel {
196 unsigned int channel;
197 unsigned int adc_channel;
198 enum adc_tm5_cal_method cal_method;
199 unsigned int prescale;
200 unsigned int hw_settle_time;
201 unsigned int decimation; /* For Gen2 ADC_TM */
202 unsigned int avg_samples; /* For Gen2 ADC_TM */
203 bool high_thr_en; /* For Gen2 ADC_TM */
204 bool low_thr_en; /* For Gen2 ADC_TM */
205 bool meas_en; /* For Gen2 ADC_TM */
206 struct iio_channel *iio;
207 struct adc_tm5_chip *chip;
208 struct thermal_zone_device *tzd;
209 };
210
211 /**
212 * struct adc_tm5_chip - ADC Thermal Monitoring properties
213 * @regmap: SPMI ADC5 Thermal Monitoring peripheral register map field.
214 * @dev: SPMI ADC5 device.
215 * @data: software configuration data.
216 * @channels: array of ADC TM channel data.
217 * @nchannels: amount of channels defined/allocated
218 * @decimation: sampling rate supported for the channel.
219 * Applies to all channels, used only on Gen1 ADC_TM.
220 * @avg_samples: ability to provide single result from the ADC
221 * that is an average of multiple measurements. Applies to all
222 * channels, used only on Gen1 ADC_TM.
223 * @base: base address of TM registers.
224 * @adc_mutex_lock: ADC_TM mutex lock, used only on Gen2 ADC_TM.
225 * It is used to ensure only one ADC channel configuration
226 * is done at a time using the shared set of configuration
227 * registers.
228 */
229 struct adc_tm5_chip {
230 struct regmap *regmap;
231 struct device *dev;
232 const struct adc_tm5_data *data;
233 struct adc_tm5_channel *channels;
234 unsigned int nchannels;
235 unsigned int decimation;
236 unsigned int avg_samples;
237 u16 base;
238 struct mutex adc_mutex_lock;
239 };
240
adc_tm5_read(struct adc_tm5_chip * adc_tm,u16 offset,u8 * data,int len)241 static int adc_tm5_read(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len)
242 {
243 return regmap_bulk_read(adc_tm->regmap, adc_tm->base + offset, data, len);
244 }
245
adc_tm5_write(struct adc_tm5_chip * adc_tm,u16 offset,u8 * data,int len)246 static int adc_tm5_write(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len)
247 {
248 return regmap_bulk_write(adc_tm->regmap, adc_tm->base + offset, data, len);
249 }
250
adc_tm5_reg_update(struct adc_tm5_chip * adc_tm,u16 offset,u8 mask,u8 val)251 static int adc_tm5_reg_update(struct adc_tm5_chip *adc_tm, u16 offset, u8 mask, u8 val)
252 {
253 return regmap_write_bits(adc_tm->regmap, adc_tm->base + offset, mask, val);
254 }
255
adc_tm5_isr(int irq,void * data)256 static irqreturn_t adc_tm5_isr(int irq, void *data)
257 {
258 struct adc_tm5_chip *chip = data;
259 u8 status_low, status_high, ctl;
260 int ret, i;
261
262 ret = adc_tm5_read(chip, ADC_TM5_STATUS_LOW, &status_low, sizeof(status_low));
263 if (unlikely(ret)) {
264 dev_err(chip->dev, "read status low failed: %d\n", ret);
265 return IRQ_HANDLED;
266 }
267
268 ret = adc_tm5_read(chip, ADC_TM5_STATUS_HIGH, &status_high, sizeof(status_high));
269 if (unlikely(ret)) {
270 dev_err(chip->dev, "read status high failed: %d\n", ret);
271 return IRQ_HANDLED;
272 }
273
274 for (i = 0; i < chip->nchannels; i++) {
275 bool upper_set = false, lower_set = false;
276 unsigned int ch = chip->channels[i].channel;
277
278 /* No TZD, we warned at the boot time */
279 if (!chip->channels[i].tzd)
280 continue;
281
282 ret = adc_tm5_read(chip, ADC_TM5_M_EN(ch), &ctl, sizeof(ctl));
283 if (unlikely(ret)) {
284 dev_err(chip->dev, "ctl read failed: %d, channel %d\n", ret, i);
285 continue;
286 }
287
288 if (!(ctl & ADC_TM5_M_MEAS_EN))
289 continue;
290
291 lower_set = (status_low & BIT(ch)) &&
292 (ctl & ADC_TM5_M_LOW_THR_INT_EN);
293
294 upper_set = (status_high & BIT(ch)) &&
295 (ctl & ADC_TM5_M_HIGH_THR_INT_EN);
296
297 if (upper_set || lower_set)
298 thermal_zone_device_update(chip->channels[i].tzd,
299 THERMAL_EVENT_UNSPECIFIED);
300 }
301
302 return IRQ_HANDLED;
303 }
304
adc_tm5_gen2_isr(int irq,void * data)305 static irqreturn_t adc_tm5_gen2_isr(int irq, void *data)
306 {
307 struct adc_tm5_chip *chip = data;
308 u8 status_low, status_high;
309 int ret, i;
310
311 ret = adc_tm5_read(chip, ADC_TM_GEN2_STATUS_LOW_CLR, &status_low, sizeof(status_low));
312 if (ret) {
313 dev_err(chip->dev, "read status_low failed: %d\n", ret);
314 return IRQ_HANDLED;
315 }
316
317 ret = adc_tm5_read(chip, ADC_TM_GEN2_STATUS_HIGH_CLR, &status_high, sizeof(status_high));
318 if (ret) {
319 dev_err(chip->dev, "read status_high failed: %d\n", ret);
320 return IRQ_HANDLED;
321 }
322
323 ret = adc_tm5_write(chip, ADC_TM_GEN2_STATUS_LOW_CLR, &status_low, sizeof(status_low));
324 if (ret < 0) {
325 dev_err(chip->dev, "clear status low failed with %d\n", ret);
326 return IRQ_HANDLED;
327 }
328
329 ret = adc_tm5_write(chip, ADC_TM_GEN2_STATUS_HIGH_CLR, &status_high, sizeof(status_high));
330 if (ret < 0) {
331 dev_err(chip->dev, "clear status high failed with %d\n", ret);
332 return IRQ_HANDLED;
333 }
334
335 for (i = 0; i < chip->nchannels; i++) {
336 bool upper_set = false, lower_set = false;
337 unsigned int ch = chip->channels[i].channel;
338
339 /* No TZD, we warned at the boot time */
340 if (!chip->channels[i].tzd)
341 continue;
342
343 if (!chip->channels[i].meas_en)
344 continue;
345
346 lower_set = (status_low & BIT(ch)) &&
347 (chip->channels[i].low_thr_en);
348
349 upper_set = (status_high & BIT(ch)) &&
350 (chip->channels[i].high_thr_en);
351
352 if (upper_set || lower_set)
353 thermal_zone_device_update(chip->channels[i].tzd,
354 THERMAL_EVENT_UNSPECIFIED);
355 }
356
357 return IRQ_HANDLED;
358 }
359
adc_tm5_get_temp(struct thermal_zone_device * tz,int * temp)360 static int adc_tm5_get_temp(struct thermal_zone_device *tz, int *temp)
361 {
362 struct adc_tm5_channel *channel = thermal_zone_device_priv(tz);
363 int ret;
364
365 if (!channel || !channel->iio)
366 return -EINVAL;
367
368 ret = iio_read_channel_processed(channel->iio, temp);
369 if (ret < 0)
370 return ret;
371
372 return 0;
373 }
374
adc_tm5_disable_channel(struct adc_tm5_channel * channel)375 static int adc_tm5_disable_channel(struct adc_tm5_channel *channel)
376 {
377 struct adc_tm5_chip *chip = channel->chip;
378 unsigned int reg = ADC_TM5_M_EN(channel->channel);
379
380 return adc_tm5_reg_update(chip, reg,
381 ADC_TM5_M_MEAS_EN |
382 ADC_TM5_M_HIGH_THR_INT_EN |
383 ADC_TM5_M_LOW_THR_INT_EN,
384 0);
385 }
386
387 #define ADC_TM_GEN2_POLL_DELAY_MIN_US 100
388 #define ADC_TM_GEN2_POLL_DELAY_MAX_US 110
389 #define ADC_TM_GEN2_POLL_RETRY_COUNT 3
390
adc_tm5_gen2_conv_req(struct adc_tm5_chip * chip)391 static int32_t adc_tm5_gen2_conv_req(struct adc_tm5_chip *chip)
392 {
393 int ret;
394 u8 data;
395 unsigned int count;
396
397 data = ADC_TM_GEN2_EN;
398 ret = adc_tm5_write(chip, ADC_TM_GEN2_EN_CTL1, &data, 1);
399 if (ret < 0) {
400 dev_err(chip->dev, "adc-tm enable failed with %d\n", ret);
401 return ret;
402 }
403
404 data = ADC_TM_GEN2_CFG_HS_FLAG;
405 ret = adc_tm5_write(chip, ADC_TM_GEN2_CFG_HS_SET, &data, 1);
406 if (ret < 0) {
407 dev_err(chip->dev, "adc-tm handshake failed with %d\n", ret);
408 return ret;
409 }
410
411 data = ADC_TM_GEN2_CONV_REQ_EN;
412 ret = adc_tm5_write(chip, ADC_TM_GEN2_CONV_REQ, &data, 1);
413 if (ret < 0) {
414 dev_err(chip->dev, "adc-tm request conversion failed with %d\n", ret);
415 return ret;
416 }
417
418 /*
419 * SW sets a handshake bit and waits for PBS to clear it
420 * before the next conversion request can be queued.
421 */
422
423 for (count = 0; count < ADC_TM_GEN2_POLL_RETRY_COUNT; count++) {
424 ret = adc_tm5_read(chip, ADC_TM_GEN2_CFG_HS_SET, &data, sizeof(data));
425 if (ret < 0) {
426 dev_err(chip->dev, "adc-tm read failed with %d\n", ret);
427 return ret;
428 }
429
430 if (!(data & ADC_TM_GEN2_CFG_HS_FLAG))
431 return ret;
432 usleep_range(ADC_TM_GEN2_POLL_DELAY_MIN_US,
433 ADC_TM_GEN2_POLL_DELAY_MAX_US);
434 }
435
436 dev_err(chip->dev, "adc-tm conversion request handshake timed out\n");
437
438 return -ETIMEDOUT;
439 }
440
adc_tm5_gen2_disable_channel(struct adc_tm5_channel * channel)441 static int adc_tm5_gen2_disable_channel(struct adc_tm5_channel *channel)
442 {
443 struct adc_tm5_chip *chip = channel->chip;
444 int ret;
445 u8 val;
446
447 mutex_lock(&chip->adc_mutex_lock);
448
449 channel->meas_en = false;
450 channel->high_thr_en = false;
451 channel->low_thr_en = false;
452
453 ret = adc_tm5_read(chip, ADC_TM_GEN2_CH_CTL, &val, sizeof(val));
454 if (ret < 0) {
455 dev_err(chip->dev, "adc-tm block read failed with %d\n", ret);
456 goto disable_fail;
457 }
458
459 val &= ~ADC_TM_GEN2_TM_CH_SEL;
460 val |= FIELD_PREP(ADC_TM_GEN2_TM_CH_SEL, channel->channel);
461
462 ret = adc_tm5_write(chip, ADC_TM_GEN2_CH_CTL, &val, 1);
463 if (ret < 0) {
464 dev_err(chip->dev, "adc-tm channel disable failed with %d\n", ret);
465 goto disable_fail;
466 }
467
468 val = 0;
469 ret = adc_tm5_write(chip, ADC_TM_GEN2_MEAS_IRQ_EN, &val, 1);
470 if (ret < 0) {
471 dev_err(chip->dev, "adc-tm interrupt disable failed with %d\n", ret);
472 goto disable_fail;
473 }
474
475
476 ret = adc_tm5_gen2_conv_req(channel->chip);
477 if (ret < 0)
478 dev_err(chip->dev, "adc-tm channel configure failed with %d\n", ret);
479
480 disable_fail:
481 mutex_unlock(&chip->adc_mutex_lock);
482 return ret;
483 }
484
adc_tm5_enable(struct adc_tm5_chip * chip)485 static int adc_tm5_enable(struct adc_tm5_chip *chip)
486 {
487 int ret;
488 u8 data;
489
490 data = ADC_TM_EN;
491 ret = adc_tm5_write(chip, ADC_TM_EN_CTL1, &data, sizeof(data));
492 if (ret < 0) {
493 dev_err(chip->dev, "adc-tm enable failed\n");
494 return ret;
495 }
496
497 data = ADC_TM_CONV_REQ_EN;
498 ret = adc_tm5_write(chip, ADC_TM_CONV_REQ, &data, sizeof(data));
499 if (ret < 0) {
500 dev_err(chip->dev, "adc-tm request conversion failed\n");
501 return ret;
502 }
503
504 return 0;
505 }
506
adc_tm5_configure(struct adc_tm5_channel * channel,int low,int high)507 static int adc_tm5_configure(struct adc_tm5_channel *channel, int low, int high)
508 {
509 struct adc_tm5_chip *chip = channel->chip;
510 u8 buf[8];
511 u16 reg = ADC_TM5_M_ADC_CH_SEL_CTL(channel->channel);
512 int ret;
513
514 ret = adc_tm5_read(chip, reg, buf, sizeof(buf));
515 if (ret) {
516 dev_err(chip->dev, "channel %d params read failed: %d\n", channel->channel, ret);
517 return ret;
518 }
519
520 buf[0] = channel->adc_channel;
521
522 /* High temperature corresponds to low voltage threshold */
523 if (high != INT_MAX) {
524 u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale,
525 chip->data->full_scale_code_volt, high);
526
527 put_unaligned_le16(adc_code, &buf[1]);
528 buf[7] |= ADC_TM5_M_LOW_THR_INT_EN;
529 } else {
530 buf[7] &= ~ADC_TM5_M_LOW_THR_INT_EN;
531 }
532
533 /* Low temperature corresponds to high voltage threshold */
534 if (low != -INT_MAX) {
535 u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale,
536 chip->data->full_scale_code_volt, low);
537
538 put_unaligned_le16(adc_code, &buf[3]);
539 buf[7] |= ADC_TM5_M_HIGH_THR_INT_EN;
540 } else {
541 buf[7] &= ~ADC_TM5_M_HIGH_THR_INT_EN;
542 }
543
544 buf[5] = ADC5_TIMER_SEL_2;
545
546 /* Set calibration select, hw_settle delay */
547 buf[6] &= ~ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK;
548 buf[6] |= FIELD_PREP(ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK, channel->hw_settle_time);
549 buf[6] &= ~ADC_TM5_M_CTL_CAL_SEL_MASK;
550 buf[6] |= FIELD_PREP(ADC_TM5_M_CTL_CAL_SEL_MASK, channel->cal_method);
551
552 buf[7] |= ADC_TM5_M_MEAS_EN;
553
554 ret = adc_tm5_write(chip, reg, buf, sizeof(buf));
555 if (ret) {
556 dev_err(chip->dev, "channel %d params write failed: %d\n", channel->channel, ret);
557 return ret;
558 }
559
560 return adc_tm5_enable(chip);
561 }
562
adc_tm5_gen2_configure(struct adc_tm5_channel * channel,int low,int high)563 static int adc_tm5_gen2_configure(struct adc_tm5_channel *channel, int low, int high)
564 {
565 struct adc_tm5_chip *chip = channel->chip;
566 int ret;
567 u8 buf[14];
568 u16 adc_code;
569
570 mutex_lock(&chip->adc_mutex_lock);
571
572 channel->meas_en = true;
573
574 ret = adc_tm5_read(chip, ADC_TM_GEN2_SID, buf, sizeof(buf));
575 if (ret < 0) {
576 dev_err(chip->dev, "adc-tm block read failed with %d\n", ret);
577 goto config_fail;
578 }
579
580 /* Set SID from virtual channel number */
581 buf[0] = channel->adc_channel >> 8;
582
583 /* Set TM channel number used and measurement interval */
584 buf[1] &= ~ADC_TM_GEN2_TM_CH_SEL;
585 buf[1] |= FIELD_PREP(ADC_TM_GEN2_TM_CH_SEL, channel->channel);
586 buf[1] &= ~ADC_TM_GEN2_MEAS_INT_SEL;
587 buf[1] |= FIELD_PREP(ADC_TM_GEN2_MEAS_INT_SEL, MEAS_INT_1S);
588
589 buf[2] &= ~ADC_TM_GEN2_CTL_DEC_RATIO_MASK;
590 buf[2] |= FIELD_PREP(ADC_TM_GEN2_CTL_DEC_RATIO_MASK, channel->decimation);
591 buf[2] &= ~ADC_TM_GEN2_CTL_CAL_SEL;
592 buf[2] |= FIELD_PREP(ADC_TM_GEN2_CTL_CAL_SEL, channel->cal_method);
593
594 buf[3] = channel->avg_samples | ADC_TM_GEN2_FAST_AVG_EN;
595
596 buf[4] = channel->adc_channel & 0xff;
597
598 buf[5] = channel->hw_settle_time & ADC_TM_GEN2_HW_SETTLE_DELAY;
599
600 /* High temperature corresponds to low voltage threshold */
601 if (high != INT_MAX) {
602 channel->low_thr_en = true;
603 adc_code = qcom_adc_tm5_gen2_temp_res_scale(high);
604 put_unaligned_le16(adc_code, &buf[9]);
605 } else {
606 channel->low_thr_en = false;
607 }
608
609 /* Low temperature corresponds to high voltage threshold */
610 if (low != -INT_MAX) {
611 channel->high_thr_en = true;
612 adc_code = qcom_adc_tm5_gen2_temp_res_scale(low);
613 put_unaligned_le16(adc_code, &buf[11]);
614 } else {
615 channel->high_thr_en = false;
616 }
617
618 buf[13] = ADC_TM_GEN2_MEAS_EN;
619 if (channel->high_thr_en)
620 buf[13] |= ADC_TM5_GEN2_HIGH_THR_INT_EN;
621 if (channel->low_thr_en)
622 buf[13] |= ADC_TM5_GEN2_LOW_THR_INT_EN;
623
624 ret = adc_tm5_write(chip, ADC_TM_GEN2_SID, buf, sizeof(buf));
625 if (ret) {
626 dev_err(chip->dev, "channel %d params write failed: %d\n", channel->channel, ret);
627 goto config_fail;
628 }
629
630 ret = adc_tm5_gen2_conv_req(channel->chip);
631 if (ret < 0)
632 dev_err(chip->dev, "adc-tm channel configure failed with %d\n", ret);
633
634 config_fail:
635 mutex_unlock(&chip->adc_mutex_lock);
636 return ret;
637 }
638
adc_tm5_set_trips(struct thermal_zone_device * tz,int low,int high)639 static int adc_tm5_set_trips(struct thermal_zone_device *tz, int low, int high)
640 {
641 struct adc_tm5_channel *channel = thermal_zone_device_priv(tz);
642 struct adc_tm5_chip *chip;
643 int ret;
644
645 if (!channel)
646 return -EINVAL;
647
648 chip = channel->chip;
649 dev_dbg(chip->dev, "%d:low(mdegC):%d, high(mdegC):%d\n",
650 channel->channel, low, high);
651
652 if (high == INT_MAX && low <= -INT_MAX)
653 ret = chip->data->disable_channel(channel);
654 else
655 ret = chip->data->configure(channel, low, high);
656
657 return ret;
658 }
659
660 static const struct thermal_zone_device_ops adc_tm5_thermal_ops = {
661 .get_temp = adc_tm5_get_temp,
662 .set_trips = adc_tm5_set_trips,
663 };
664
adc_tm5_register_tzd(struct adc_tm5_chip * adc_tm)665 static int adc_tm5_register_tzd(struct adc_tm5_chip *adc_tm)
666 {
667 unsigned int i;
668 struct thermal_zone_device *tzd;
669
670 for (i = 0; i < adc_tm->nchannels; i++) {
671 adc_tm->channels[i].chip = adc_tm;
672 tzd = devm_thermal_of_zone_register(adc_tm->dev,
673 adc_tm->channels[i].channel,
674 &adc_tm->channels[i],
675 &adc_tm5_thermal_ops);
676 if (IS_ERR(tzd)) {
677 if (PTR_ERR(tzd) == -ENODEV) {
678 dev_dbg(adc_tm->dev, "thermal sensor on channel %d is not used\n",
679 adc_tm->channels[i].channel);
680 continue;
681 }
682
683 dev_err(adc_tm->dev, "Error registering TZ zone for channel %d: %ld\n",
684 adc_tm->channels[i].channel, PTR_ERR(tzd));
685 return PTR_ERR(tzd);
686 }
687 adc_tm->channels[i].tzd = tzd;
688 devm_thermal_add_hwmon_sysfs(adc_tm->dev, tzd);
689 }
690
691 return 0;
692 }
693
adc_tm_hc_init(struct adc_tm5_chip * chip)694 static int adc_tm_hc_init(struct adc_tm5_chip *chip)
695 {
696 unsigned int i;
697 u8 buf[2];
698 int ret;
699
700 for (i = 0; i < chip->nchannels; i++) {
701 if (chip->channels[i].channel >= ADC_TM5_NUM_CHANNELS) {
702 dev_err(chip->dev, "Invalid channel %d\n", chip->channels[i].channel);
703 return -EINVAL;
704 }
705 }
706
707 buf[0] = chip->decimation;
708 buf[1] = chip->avg_samples | ADC_TM5_FAST_AVG_EN;
709
710 ret = adc_tm5_write(chip, ADC_TM5_ADC_DIG_PARAM, buf, sizeof(buf));
711 if (ret)
712 dev_err(chip->dev, "block write failed: %d\n", ret);
713
714 return ret;
715 }
716
adc_tm5_init(struct adc_tm5_chip * chip)717 static int adc_tm5_init(struct adc_tm5_chip *chip)
718 {
719 u8 buf[4], channels_available;
720 int ret;
721 unsigned int i;
722
723 ret = adc_tm5_read(chip, ADC_TM5_NUM_BTM,
724 &channels_available, sizeof(channels_available));
725 if (ret) {
726 dev_err(chip->dev, "read failed for BTM channels\n");
727 return ret;
728 }
729
730 for (i = 0; i < chip->nchannels; i++) {
731 if (chip->channels[i].channel >= channels_available) {
732 dev_err(chip->dev, "Invalid channel %d\n", chip->channels[i].channel);
733 return -EINVAL;
734 }
735 }
736
737 buf[0] = chip->decimation;
738 buf[1] = chip->avg_samples | ADC_TM5_FAST_AVG_EN;
739 buf[2] = ADC_TM5_TIMER1;
740 buf[3] = FIELD_PREP(ADC_TM5_MEAS_INTERVAL_CTL2_MASK, ADC_TM5_TIMER2) |
741 FIELD_PREP(ADC_TM5_MEAS_INTERVAL_CTL3_MASK, ADC_TM5_TIMER3);
742
743 ret = adc_tm5_write(chip, ADC_TM5_ADC_DIG_PARAM, buf, sizeof(buf));
744 if (ret) {
745 dev_err(chip->dev, "block write failed: %d\n", ret);
746 return ret;
747 }
748
749 return ret;
750 }
751
adc_tm5_gen2_init(struct adc_tm5_chip * chip)752 static int adc_tm5_gen2_init(struct adc_tm5_chip *chip)
753 {
754 u8 channels_available;
755 int ret;
756 unsigned int i;
757
758 ret = adc_tm5_read(chip, ADC_TM5_NUM_BTM,
759 &channels_available, sizeof(channels_available));
760 if (ret) {
761 dev_err(chip->dev, "read failed for BTM channels\n");
762 return ret;
763 }
764
765 for (i = 0; i < chip->nchannels; i++) {
766 if (chip->channels[i].channel >= channels_available) {
767 dev_err(chip->dev, "Invalid channel %d\n", chip->channels[i].channel);
768 return -EINVAL;
769 }
770 }
771
772 mutex_init(&chip->adc_mutex_lock);
773
774 return ret;
775 }
776
adc_tm5_get_dt_channel_data(struct adc_tm5_chip * adc_tm,struct adc_tm5_channel * channel,struct device_node * node)777 static int adc_tm5_get_dt_channel_data(struct adc_tm5_chip *adc_tm,
778 struct adc_tm5_channel *channel,
779 struct device_node *node)
780 {
781 const char *name = node->name;
782 u32 chan, value, adc_channel, varr[2];
783 int ret;
784 struct device *dev = adc_tm->dev;
785 struct of_phandle_args args;
786
787 ret = of_property_read_u32(node, "reg", &chan);
788 if (ret) {
789 dev_err(dev, "%s: invalid channel number %d\n", name, ret);
790 return ret;
791 }
792
793 if (chan >= ADC_TM5_NUM_CHANNELS) {
794 dev_err(dev, "%s: channel number too big: %d\n", name, chan);
795 return -EINVAL;
796 }
797
798 channel->channel = chan;
799
800 /*
801 * We are tied to PMIC's ADC controller, which always use single
802 * argument for channel number. So don't bother parsing
803 * #io-channel-cells, just enforce cell_count = 1.
804 */
805 ret = of_parse_phandle_with_fixed_args(node, "io-channels", 1, 0, &args);
806 if (ret < 0) {
807 dev_err(dev, "%s: error parsing ADC channel number %d: %d\n", name, chan, ret);
808 return ret;
809 }
810 of_node_put(args.np);
811
812 if (args.args_count != 1) {
813 dev_err(dev, "%s: invalid args count for ADC channel %d\n", name, chan);
814 return -EINVAL;
815 }
816
817 adc_channel = args.args[0];
818 if (adc_tm->data->gen == ADC_TM5_GEN2)
819 adc_channel &= 0xff;
820
821 if (adc_channel >= ADC5_MAX_CHANNEL) {
822 dev_err(dev, "%s: invalid ADC channel number %d\n", name, chan);
823 return -EINVAL;
824 }
825 channel->adc_channel = args.args[0];
826
827 channel->iio = devm_fwnode_iio_channel_get_by_name(adc_tm->dev,
828 of_fwnode_handle(node), NULL);
829 if (IS_ERR(channel->iio))
830 return dev_err_probe(dev, PTR_ERR(channel->iio), "%s: error getting channel\n",
831 name);
832
833 ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2);
834 if (!ret) {
835 ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]);
836 if (ret < 0) {
837 dev_err(dev, "%s: invalid pre-scaling <%d %d>\n",
838 name, varr[0], varr[1]);
839 return ret;
840 }
841 channel->prescale = ret;
842 } else {
843 /* 1:1 prescale is index 0 */
844 channel->prescale = 0;
845 }
846
847 ret = of_property_read_u32(node, "qcom,hw-settle-time-us", &value);
848 if (!ret) {
849 ret = qcom_adc5_hw_settle_time_from_dt(value, adc_tm->data->hw_settle);
850 if (ret < 0) {
851 dev_err(dev, "%s invalid hw-settle-time-us %d us\n",
852 name, value);
853 return ret;
854 }
855 channel->hw_settle_time = ret;
856 } else {
857 channel->hw_settle_time = VADC_DEF_HW_SETTLE_TIME;
858 }
859
860 if (of_property_read_bool(node, "qcom,ratiometric"))
861 channel->cal_method = ADC_TM5_RATIOMETRIC_CAL;
862 else
863 channel->cal_method = ADC_TM5_ABSOLUTE_CAL;
864
865 if (adc_tm->data->gen == ADC_TM5_GEN2) {
866 ret = of_property_read_u32(node, "qcom,decimation", &value);
867 if (!ret) {
868 ret = qcom_adc5_decimation_from_dt(value, adc_tm->data->decimation);
869 if (ret < 0) {
870 dev_err(dev, "invalid decimation %d\n", value);
871 return ret;
872 }
873 channel->decimation = ret;
874 } else {
875 channel->decimation = ADC5_DECIMATION_DEFAULT;
876 }
877
878 ret = of_property_read_u32(node, "qcom,avg-samples", &value);
879 if (!ret) {
880 ret = qcom_adc5_avg_samples_from_dt(value);
881 if (ret < 0) {
882 dev_err(dev, "invalid avg-samples %d\n", value);
883 return ret;
884 }
885 channel->avg_samples = ret;
886 } else {
887 channel->avg_samples = VADC_DEF_AVG_SAMPLES;
888 }
889 }
890
891 return 0;
892 }
893
894 static const struct adc_tm5_data adc_tm5_data_pmic = {
895 .full_scale_code_volt = 0x70e4,
896 .decimation = (unsigned int []) { 250, 420, 840 },
897 .hw_settle = (unsigned int []) { 15, 100, 200, 300, 400, 500, 600, 700,
898 1000, 2000, 4000, 8000, 16000, 32000,
899 64000, 128000 },
900 .disable_channel = adc_tm5_disable_channel,
901 .configure = adc_tm5_configure,
902 .isr = adc_tm5_isr,
903 .init = adc_tm5_init,
904 .irq_name = "pm-adc-tm5",
905 .gen = ADC_TM5,
906 };
907
908 static const struct adc_tm5_data adc_tm_hc_data_pmic = {
909 .full_scale_code_volt = 0x70e4,
910 .decimation = (unsigned int []) { 256, 512, 1024 },
911 .hw_settle = (unsigned int []) { 0, 100, 200, 300, 400, 500, 600, 700,
912 1000, 2000, 4000, 6000, 8000, 10000 },
913 .disable_channel = adc_tm5_disable_channel,
914 .configure = adc_tm5_configure,
915 .isr = adc_tm5_isr,
916 .init = adc_tm_hc_init,
917 .irq_name = "pm-adc-tm5",
918 .gen = ADC_TM_HC,
919 };
920
921 static const struct adc_tm5_data adc_tm5_gen2_data_pmic = {
922 .full_scale_code_volt = 0x70e4,
923 .decimation = (unsigned int []) { 85, 340, 1360 },
924 .hw_settle = (unsigned int []) { 15, 100, 200, 300, 400, 500, 600, 700,
925 1000, 2000, 4000, 8000, 16000, 32000,
926 64000, 128000 },
927 .disable_channel = adc_tm5_gen2_disable_channel,
928 .configure = adc_tm5_gen2_configure,
929 .isr = adc_tm5_gen2_isr,
930 .init = adc_tm5_gen2_init,
931 .irq_name = "pm-adc-tm5-gen2",
932 .gen = ADC_TM5_GEN2,
933 };
934
adc_tm5_get_dt_data(struct adc_tm5_chip * adc_tm,struct device_node * node)935 static int adc_tm5_get_dt_data(struct adc_tm5_chip *adc_tm, struct device_node *node)
936 {
937 struct adc_tm5_channel *channels;
938 u32 value;
939 int ret;
940 struct device *dev = adc_tm->dev;
941
942 adc_tm->nchannels = of_get_available_child_count(node);
943 if (!adc_tm->nchannels)
944 return -EINVAL;
945
946 adc_tm->channels = devm_kcalloc(dev, adc_tm->nchannels,
947 sizeof(*adc_tm->channels), GFP_KERNEL);
948 if (!adc_tm->channels)
949 return -ENOMEM;
950
951 channels = adc_tm->channels;
952
953 adc_tm->data = of_device_get_match_data(dev);
954 if (!adc_tm->data)
955 adc_tm->data = &adc_tm5_data_pmic;
956
957 ret = of_property_read_u32(node, "qcom,decimation", &value);
958 if (!ret) {
959 ret = qcom_adc5_decimation_from_dt(value, adc_tm->data->decimation);
960 if (ret < 0) {
961 dev_err(dev, "invalid decimation %d\n", value);
962 return ret;
963 }
964 adc_tm->decimation = ret;
965 } else {
966 adc_tm->decimation = ADC5_DECIMATION_DEFAULT;
967 }
968
969 ret = of_property_read_u32(node, "qcom,avg-samples", &value);
970 if (!ret) {
971 ret = qcom_adc5_avg_samples_from_dt(value);
972 if (ret < 0) {
973 dev_err(dev, "invalid avg-samples %d\n", value);
974 return ret;
975 }
976 adc_tm->avg_samples = ret;
977 } else {
978 adc_tm->avg_samples = VADC_DEF_AVG_SAMPLES;
979 }
980
981 for_each_available_child_of_node_scoped(node, child) {
982 ret = adc_tm5_get_dt_channel_data(adc_tm, channels, child);
983 if (ret)
984 return ret;
985
986 channels++;
987 }
988
989 return 0;
990 }
991
adc_tm5_probe(struct platform_device * pdev)992 static int adc_tm5_probe(struct platform_device *pdev)
993 {
994 struct device_node *node = pdev->dev.of_node;
995 struct device *dev = &pdev->dev;
996 struct adc_tm5_chip *adc_tm;
997 struct regmap *regmap;
998 int ret, irq;
999 u32 reg;
1000
1001 regmap = dev_get_regmap(dev->parent, NULL);
1002 if (!regmap)
1003 return -ENODEV;
1004
1005 ret = of_property_read_u32(node, "reg", ®);
1006 if (ret)
1007 return ret;
1008
1009 adc_tm = devm_kzalloc(&pdev->dev, sizeof(*adc_tm), GFP_KERNEL);
1010 if (!adc_tm)
1011 return -ENOMEM;
1012
1013 adc_tm->regmap = regmap;
1014 adc_tm->dev = dev;
1015 adc_tm->base = reg;
1016
1017 irq = platform_get_irq(pdev, 0);
1018 if (irq < 0)
1019 return irq;
1020
1021 ret = adc_tm5_get_dt_data(adc_tm, node);
1022 if (ret)
1023 return dev_err_probe(dev, ret, "get dt data failed\n");
1024
1025 ret = adc_tm->data->init(adc_tm);
1026 if (ret) {
1027 dev_err(dev, "adc-tm init failed\n");
1028 return ret;
1029 }
1030
1031 ret = adc_tm5_register_tzd(adc_tm);
1032 if (ret) {
1033 dev_err(dev, "tzd register failed\n");
1034 return ret;
1035 }
1036
1037 return devm_request_threaded_irq(dev, irq, NULL, adc_tm->data->isr,
1038 IRQF_ONESHOT, adc_tm->data->irq_name, adc_tm);
1039 }
1040
1041 static const struct of_device_id adc_tm5_match_table[] = {
1042 {
1043 .compatible = "qcom,spmi-adc-tm5",
1044 .data = &adc_tm5_data_pmic,
1045 },
1046 {
1047 .compatible = "qcom,spmi-adc-tm-hc",
1048 .data = &adc_tm_hc_data_pmic,
1049 },
1050 {
1051 .compatible = "qcom,spmi-adc-tm5-gen2",
1052 .data = &adc_tm5_gen2_data_pmic,
1053 },
1054 { }
1055 };
1056 MODULE_DEVICE_TABLE(of, adc_tm5_match_table);
1057
1058 static struct platform_driver adc_tm5_driver = {
1059 .driver = {
1060 .name = "qcom-spmi-adc-tm5",
1061 .of_match_table = adc_tm5_match_table,
1062 },
1063 .probe = adc_tm5_probe,
1064 };
1065 module_platform_driver(adc_tm5_driver);
1066
1067 MODULE_DESCRIPTION("SPMI PMIC Thermal Monitor ADC driver");
1068 MODULE_LICENSE("GPL v2");
1069 MODULE_IMPORT_NS("IIO_CONSUMER");
1070