1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AD9833/AD9834/AD9837/AD9838 SPI DDS driver
4 *
5 * Copyright 2010-2011 Analog Devices Inc.
6 */
7
8 #include <linux/bits.h>
9 #include <linux/clk.h>
10 #include <linux/dev_printk.h>
11 #include <linux/err.h>
12 #include <linux/kstrtox.h>
13 #include <linux/module.h>
14 #include <linux/mutex.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/spi/spi.h>
17 #include <linux/string.h>
18 #include <linux/sysfs.h>
19 #include <linux/types.h>
20
21 #include <asm/byteorder.h>
22 #include <asm/div64.h>
23
24 #include <linux/iio/iio.h>
25 #include <linux/iio/sysfs.h>
26
27 #include "dds.h"
28
29 /* Registers */
30
31 #define AD9834_REG_CMD 0
32 #define AD9834_REG_FREQ0 BIT(14)
33 #define AD9834_REG_FREQ1 BIT(15)
34 #define AD9834_REG_PHASE0 (BIT(15) | BIT(14))
35 #define AD9834_REG_PHASE1 (BIT(15) | BIT(14) | BIT(13))
36
37 /* Command Control Bits */
38
39 #define AD9834_B28 BIT(13)
40 #define AD9834_HLB BIT(12)
41 #define AD9834_FSEL BIT(11)
42 #define AD9834_PSEL BIT(10)
43 #define AD9834_PIN_SW BIT(9)
44 #define AD9834_RESET BIT(8)
45 #define AD9834_SLEEP1 BIT(7)
46 #define AD9834_SLEEP12 BIT(6)
47 #define AD9834_OPBITEN BIT(5)
48 #define AD9834_SIGN_PIB BIT(4)
49 #define AD9834_DIV2 BIT(3)
50 #define AD9834_MODE BIT(1)
51
52 #define AD9834_FREQ_BITS 28
53 #define AD9834_PHASE_BITS 12
54
55 #define RES_MASK(bits) (BIT(bits) - 1)
56
57 /**
58 * struct ad9834_state - driver instance specific data
59 * @spi: spi_device
60 * @mclk: external master clock
61 * @control: cached control word
62 * @devid: device id
63 * @xfer: default spi transfer
64 * @msg: default spi message
65 * @freq_xfer: tuning word spi transfer
66 * @freq_msg: tuning word spi message
67 * @lock: protect sensor state
68 * @data: spi transmit buffer
69 * @freq_data: tuning word spi transmit buffer
70 */
71
72 struct ad9834_state {
73 struct spi_device *spi;
74 struct clk *mclk;
75 unsigned short control;
76 unsigned short devid;
77 struct spi_transfer xfer;
78 struct spi_message msg;
79 struct spi_transfer freq_xfer[2];
80 struct spi_message freq_msg;
81 struct mutex lock; /* protect sensor state */
82
83 /*
84 * DMA (thus cache coherency maintenance) requires the
85 * transfer buffers to live in their own cache lines.
86 */
87 __be16 data __aligned(IIO_DMA_MINALIGN);
88 __be16 freq_data[2];
89 };
90
91 /*
92 * ad9834_supported_device_ids:
93 */
94
95 enum ad9834_supported_device_ids {
96 ID_AD9833,
97 ID_AD9834,
98 ID_AD9837,
99 ID_AD9838,
100 };
101
ad9834_calc_freqreg(unsigned long mclk,unsigned long fout)102 static unsigned int ad9834_calc_freqreg(unsigned long mclk, unsigned long fout)
103 {
104 unsigned long long freqreg = (u64)fout * (u64)BIT(AD9834_FREQ_BITS);
105
106 do_div(freqreg, mclk);
107 return freqreg;
108 }
109
ad9834_write_frequency(struct ad9834_state * st,unsigned long addr,unsigned long fout)110 static int ad9834_write_frequency(struct ad9834_state *st,
111 unsigned long addr, unsigned long fout)
112 {
113 unsigned long clk_freq;
114 unsigned long regval;
115
116 clk_freq = clk_get_rate(st->mclk);
117
118 if (!clk_freq || fout > (clk_freq / 2))
119 return -EINVAL;
120
121 regval = ad9834_calc_freqreg(clk_freq, fout);
122
123 st->freq_data[0] = cpu_to_be16(addr | (regval &
124 RES_MASK(AD9834_FREQ_BITS / 2)));
125 st->freq_data[1] = cpu_to_be16(addr | ((regval >>
126 (AD9834_FREQ_BITS / 2)) &
127 RES_MASK(AD9834_FREQ_BITS / 2)));
128
129 return spi_sync(st->spi, &st->freq_msg);
130 }
131
ad9834_write_phase(struct ad9834_state * st,unsigned long addr,unsigned long phase)132 static int ad9834_write_phase(struct ad9834_state *st,
133 unsigned long addr, unsigned long phase)
134 {
135 if (phase >= BIT(AD9834_PHASE_BITS))
136 return -EINVAL;
137 st->data = cpu_to_be16(addr | phase);
138
139 return spi_sync(st->spi, &st->msg);
140 }
141
ad9834_write(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)142 static ssize_t ad9834_write(struct device *dev,
143 struct device_attribute *attr,
144 const char *buf,
145 size_t len)
146 {
147 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
148 struct ad9834_state *st = iio_priv(indio_dev);
149 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
150 int ret;
151 unsigned long val;
152
153 ret = kstrtoul(buf, 10, &val);
154 if (ret)
155 return ret;
156
157 mutex_lock(&st->lock);
158 switch ((u32)this_attr->address) {
159 case AD9834_REG_FREQ0:
160 case AD9834_REG_FREQ1:
161 ret = ad9834_write_frequency(st, this_attr->address, val);
162 break;
163 case AD9834_REG_PHASE0:
164 case AD9834_REG_PHASE1:
165 ret = ad9834_write_phase(st, this_attr->address, val);
166 break;
167 case AD9834_OPBITEN:
168 if (st->control & AD9834_MODE) {
169 ret = -EINVAL; /* AD9834 reserved mode */
170 break;
171 }
172
173 if (val)
174 st->control |= AD9834_OPBITEN;
175 else
176 st->control &= ~AD9834_OPBITEN;
177
178 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
179 ret = spi_sync(st->spi, &st->msg);
180 break;
181 case AD9834_PIN_SW:
182 if (val)
183 st->control |= AD9834_PIN_SW;
184 else
185 st->control &= ~AD9834_PIN_SW;
186 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
187 ret = spi_sync(st->spi, &st->msg);
188 break;
189 case AD9834_FSEL:
190 case AD9834_PSEL:
191 if (!val) {
192 st->control &= ~(this_attr->address | AD9834_PIN_SW);
193 } else if (val == 1) {
194 st->control |= this_attr->address;
195 st->control &= ~AD9834_PIN_SW;
196 } else {
197 ret = -EINVAL;
198 break;
199 }
200 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
201 ret = spi_sync(st->spi, &st->msg);
202 break;
203 case AD9834_RESET:
204 if (val)
205 st->control &= ~AD9834_RESET;
206 else
207 st->control |= AD9834_RESET;
208
209 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
210 ret = spi_sync(st->spi, &st->msg);
211 break;
212 default:
213 ret = -ENODEV;
214 }
215 mutex_unlock(&st->lock);
216
217 return ret ? ret : len;
218 }
219
ad9834_store_wavetype(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)220 static ssize_t ad9834_store_wavetype(struct device *dev,
221 struct device_attribute *attr,
222 const char *buf,
223 size_t len)
224 {
225 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
226 struct ad9834_state *st = iio_priv(indio_dev);
227 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
228 int ret = 0;
229 bool is_ad9833_7 = (st->devid == ID_AD9833) || (st->devid == ID_AD9837);
230
231 mutex_lock(&st->lock);
232
233 switch ((u32)this_attr->address) {
234 case 0:
235 if (sysfs_streq(buf, "sine")) {
236 st->control &= ~AD9834_MODE;
237 if (is_ad9833_7)
238 st->control &= ~AD9834_OPBITEN;
239 } else if (sysfs_streq(buf, "triangle")) {
240 if (is_ad9833_7) {
241 st->control &= ~AD9834_OPBITEN;
242 st->control |= AD9834_MODE;
243 } else if (st->control & AD9834_OPBITEN) {
244 ret = -EINVAL; /* AD9834 reserved mode */
245 } else {
246 st->control |= AD9834_MODE;
247 }
248 } else if (is_ad9833_7 && sysfs_streq(buf, "square")) {
249 st->control &= ~AD9834_MODE;
250 st->control |= AD9834_OPBITEN;
251 } else {
252 ret = -EINVAL;
253 }
254
255 break;
256 case 1:
257 if (sysfs_streq(buf, "square") &&
258 !(st->control & AD9834_MODE)) {
259 st->control &= ~AD9834_MODE;
260 st->control |= AD9834_OPBITEN;
261 } else {
262 ret = -EINVAL;
263 }
264 break;
265 default:
266 ret = -EINVAL;
267 break;
268 }
269
270 if (!ret) {
271 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
272 ret = spi_sync(st->spi, &st->msg);
273 }
274 mutex_unlock(&st->lock);
275
276 return ret ? ret : len;
277 }
278
279 static
ad9834_show_out0_wavetype_available(struct device * dev,struct device_attribute * attr,char * buf)280 ssize_t ad9834_show_out0_wavetype_available(struct device *dev,
281 struct device_attribute *attr,
282 char *buf)
283 {
284 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
285 struct ad9834_state *st = iio_priv(indio_dev);
286
287 if (st->devid == ID_AD9833 || st->devid == ID_AD9837)
288 return sysfs_emit(buf, "sine triangle square\n");
289 if (st->control & AD9834_OPBITEN)
290 return sysfs_emit(buf, "sine\n");
291 return sysfs_emit(buf, "sine triangle\n");
292 }
293
294 static IIO_DEVICE_ATTR(out_altvoltage0_out0_wavetype_available, 0444,
295 ad9834_show_out0_wavetype_available, NULL, 0);
296
297 static
ad9834_show_out1_wavetype_available(struct device * dev,struct device_attribute * attr,char * buf)298 ssize_t ad9834_show_out1_wavetype_available(struct device *dev,
299 struct device_attribute *attr,
300 char *buf)
301 {
302 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
303 struct ad9834_state *st = iio_priv(indio_dev);
304
305 if (st->control & AD9834_MODE)
306 return sysfs_emit(buf, "\n");
307 return sysfs_emit(buf, "square\n");
308 }
309
310 static IIO_DEVICE_ATTR(out_altvoltage0_out1_wavetype_available, 0444,
311 ad9834_show_out1_wavetype_available, NULL, 0);
312
313 /*
314 * see dds.h for further information
315 */
316
317 static IIO_DEV_ATTR_FREQ(0200, 0, 0, NULL, ad9834_write, AD9834_REG_FREQ0);
318 static IIO_DEV_ATTR_FREQ(0200, 0, 1, NULL, ad9834_write, AD9834_REG_FREQ1);
319 static IIO_DEV_ATTR_FREQSYMBOL(0200, 0, NULL, ad9834_write, AD9834_FSEL);
320 static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
321
322 static IIO_DEV_ATTR_PHASE(0200, 0, 0, NULL, ad9834_write, AD9834_REG_PHASE0);
323 static IIO_DEV_ATTR_PHASE(0200, 0, 1, NULL, ad9834_write, AD9834_REG_PHASE1);
324 static IIO_DEV_ATTR_PHASESYMBOL(0200, 0, NULL, ad9834_write, AD9834_PSEL);
325 static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
326
327 static IIO_DEV_ATTR_PINCONTROL_EN(0200, 0, NULL, ad9834_write, AD9834_PIN_SW);
328 static IIO_DEV_ATTR_OUT_ENABLE(0200, 0, NULL, ad9834_write, AD9834_RESET);
329 static IIO_DEV_ATTR_OUTY_ENABLE(0200, 0, 1, NULL, ad9834_write, AD9834_OPBITEN);
330 static IIO_DEV_ATTR_OUT_WAVETYPE(0200, 0, 0, ad9834_store_wavetype, 0);
331 static IIO_DEV_ATTR_OUT_WAVETYPE(0200, 0, 1, ad9834_store_wavetype, 1);
332
333 static struct attribute *ad9834_attributes[] = {
334 &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
335 &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
336 &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
337 &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
338 &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
339 &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
340 &iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr,
341 &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
342 &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
343 &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
344 &iio_dev_attr_out_altvoltage0_out1_enable.dev_attr.attr,
345 &iio_dev_attr_out_altvoltage0_out0_wavetype.dev_attr.attr,
346 &iio_dev_attr_out_altvoltage0_out1_wavetype.dev_attr.attr,
347 &iio_dev_attr_out_altvoltage0_out0_wavetype_available.dev_attr.attr,
348 &iio_dev_attr_out_altvoltage0_out1_wavetype_available.dev_attr.attr,
349 NULL,
350 };
351
352 static struct attribute *ad9833_attributes[] = {
353 &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
354 &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
355 &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
356 &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
357 &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
358 &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
359 &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
360 &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
361 &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
362 &iio_dev_attr_out_altvoltage0_out0_wavetype.dev_attr.attr,
363 &iio_dev_attr_out_altvoltage0_out0_wavetype_available.dev_attr.attr,
364 NULL,
365 };
366
367 static const struct attribute_group ad9834_attribute_group = {
368 .attrs = ad9834_attributes,
369 };
370
371 static const struct attribute_group ad9833_attribute_group = {
372 .attrs = ad9833_attributes,
373 };
374
375 static const struct iio_info ad9834_info = {
376 .attrs = &ad9834_attribute_group,
377 };
378
379 static const struct iio_info ad9833_info = {
380 .attrs = &ad9833_attribute_group,
381 };
382
ad9834_probe(struct spi_device * spi)383 static int ad9834_probe(struct spi_device *spi)
384 {
385 struct ad9834_state *st;
386 struct iio_dev *indio_dev;
387 int ret;
388
389 ret = devm_regulator_get_enable(&spi->dev, "avdd");
390 if (ret)
391 return dev_err_probe(&spi->dev, ret, "Failed to enable specified AVDD supply\n");
392
393 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
394 if (!indio_dev)
395 return -ENOMEM;
396 st = iio_priv(indio_dev);
397 mutex_init(&st->lock);
398 st->mclk = devm_clk_get_enabled(&spi->dev, NULL);
399 if (IS_ERR(st->mclk))
400 return dev_err_probe(&spi->dev, PTR_ERR(st->mclk),
401 "Failed to enable master clock\n");
402
403 st->spi = spi;
404 st->devid = spi_get_device_id(spi)->driver_data;
405 indio_dev->name = spi_get_device_id(spi)->name;
406 switch (st->devid) {
407 case ID_AD9833:
408 case ID_AD9837:
409 indio_dev->info = &ad9833_info;
410 break;
411 default:
412 indio_dev->info = &ad9834_info;
413 break;
414 }
415 indio_dev->modes = INDIO_DIRECT_MODE;
416
417 /* Setup default messages */
418
419 st->xfer.tx_buf = &st->data;
420 st->xfer.len = 2;
421
422 spi_message_init(&st->msg);
423 spi_message_add_tail(&st->xfer, &st->msg);
424
425 st->freq_xfer[0].tx_buf = &st->freq_data[0];
426 st->freq_xfer[0].len = 2;
427 st->freq_xfer[0].cs_change = 1;
428 st->freq_xfer[1].tx_buf = &st->freq_data[1];
429 st->freq_xfer[1].len = 2;
430
431 spi_message_init(&st->freq_msg);
432 spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
433 spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
434
435 st->control = AD9834_B28 | AD9834_RESET;
436 st->control |= AD9834_DIV2;
437
438 if (st->devid == ID_AD9834)
439 st->control |= AD9834_SIGN_PIB;
440
441 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
442 ret = spi_sync(st->spi, &st->msg);
443 if (ret)
444 return dev_err_probe(&spi->dev, ret,
445 "device init failed\n");
446
447 ret = ad9834_write_frequency(st, AD9834_REG_FREQ0, 1000000);
448 if (ret)
449 return ret;
450
451 ret = ad9834_write_frequency(st, AD9834_REG_FREQ1, 5000000);
452 if (ret)
453 return ret;
454
455 ret = ad9834_write_phase(st, AD9834_REG_PHASE0, 512);
456 if (ret)
457 return ret;
458
459 ret = ad9834_write_phase(st, AD9834_REG_PHASE1, 1024);
460 if (ret)
461 return ret;
462
463 return devm_iio_device_register(&spi->dev, indio_dev);
464 }
465
466 static const struct spi_device_id ad9834_id[] = {
467 { .name = "ad9833", .driver_data = ID_AD9833 },
468 { .name = "ad9834", .driver_data = ID_AD9834 },
469 { .name = "ad9837", .driver_data = ID_AD9837 },
470 { .name = "ad9838", .driver_data = ID_AD9838 },
471 { }
472 };
473 MODULE_DEVICE_TABLE(spi, ad9834_id);
474
475 static const struct of_device_id ad9834_of_match[] = {
476 {.compatible = "adi,ad9833"},
477 {.compatible = "adi,ad9834"},
478 {.compatible = "adi,ad9837"},
479 {.compatible = "adi,ad9838"},
480 { }
481 };
482
483 MODULE_DEVICE_TABLE(of, ad9834_of_match);
484
485 static struct spi_driver ad9834_driver = {
486 .driver = {
487 .name = "ad9834",
488 .of_match_table = ad9834_of_match
489 },
490 .probe = ad9834_probe,
491 .id_table = ad9834_id,
492 };
493 module_spi_driver(ad9834_driver);
494
495 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
496 MODULE_DESCRIPTION("Analog Devices AD9833/AD9834/AD9837/AD9838 DDS");
497 MODULE_LICENSE("GPL v2");
498