1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AD9833/AD9834/AD9837/AD9838 SPI DDS driver
4 *
5 * Copyright 2010-2011 Analog Devices Inc.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/interrupt.h>
10 #include <linux/workqueue.h>
11 #include <linux/device.h>
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/sysfs.h>
15 #include <linux/list.h>
16 #include <linux/spi/spi.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/err.h>
19 #include <linux/module.h>
20 #include <asm/div64.h>
21
22 #include <linux/iio/iio.h>
23 #include <linux/iio/sysfs.h>
24
25 #include "dds.h"
26
27 /* Registers */
28
29 #define AD9834_REG_CMD 0
30 #define AD9834_REG_FREQ0 BIT(14)
31 #define AD9834_REG_FREQ1 BIT(15)
32 #define AD9834_REG_PHASE0 (BIT(15) | BIT(14))
33 #define AD9834_REG_PHASE1 (BIT(15) | BIT(14) | BIT(13))
34
35 /* Command Control Bits */
36
37 #define AD9834_B28 BIT(13)
38 #define AD9834_HLB BIT(12)
39 #define AD9834_FSEL BIT(11)
40 #define AD9834_PSEL BIT(10)
41 #define AD9834_PIN_SW BIT(9)
42 #define AD9834_RESET BIT(8)
43 #define AD9834_SLEEP1 BIT(7)
44 #define AD9834_SLEEP12 BIT(6)
45 #define AD9834_OPBITEN BIT(5)
46 #define AD9834_SIGN_PIB BIT(4)
47 #define AD9834_DIV2 BIT(3)
48 #define AD9834_MODE BIT(1)
49
50 #define AD9834_FREQ_BITS 28
51 #define AD9834_PHASE_BITS 12
52
53 #define RES_MASK(bits) (BIT(bits) - 1)
54
55 /**
56 * struct ad9834_state - driver instance specific data
57 * @spi: spi_device
58 * @mclk: external master clock
59 * @control: cached control word
60 * @devid: device id
61 * @xfer: default spi transfer
62 * @msg: default spi message
63 * @freq_xfer: tuning word spi transfer
64 * @freq_msg: tuning word spi message
65 * @lock: protect sensor state
66 * @data: spi transmit buffer
67 * @freq_data: tuning word spi transmit buffer
68 */
69
70 struct ad9834_state {
71 struct spi_device *spi;
72 struct clk *mclk;
73 unsigned short control;
74 unsigned short devid;
75 struct spi_transfer xfer;
76 struct spi_message msg;
77 struct spi_transfer freq_xfer[2];
78 struct spi_message freq_msg;
79 struct mutex lock; /* protect sensor state */
80
81 /*
82 * DMA (thus cache coherency maintenance) requires the
83 * transfer buffers to live in their own cache lines.
84 */
85 __be16 data __aligned(IIO_DMA_MINALIGN);
86 __be16 freq_data[2];
87 };
88
89 /*
90 * ad9834_supported_device_ids:
91 */
92
93 enum ad9834_supported_device_ids {
94 ID_AD9833,
95 ID_AD9834,
96 ID_AD9837,
97 ID_AD9838,
98 };
99
ad9834_calc_freqreg(unsigned long mclk,unsigned long fout)100 static unsigned int ad9834_calc_freqreg(unsigned long mclk, unsigned long fout)
101 {
102 unsigned long long freqreg = (u64)fout * (u64)BIT(AD9834_FREQ_BITS);
103
104 do_div(freqreg, mclk);
105 return freqreg;
106 }
107
ad9834_write_frequency(struct ad9834_state * st,unsigned long addr,unsigned long fout)108 static int ad9834_write_frequency(struct ad9834_state *st,
109 unsigned long addr, unsigned long fout)
110 {
111 unsigned long clk_freq;
112 unsigned long regval;
113
114 clk_freq = clk_get_rate(st->mclk);
115
116 if (!clk_freq || fout > (clk_freq / 2))
117 return -EINVAL;
118
119 regval = ad9834_calc_freqreg(clk_freq, fout);
120
121 st->freq_data[0] = cpu_to_be16(addr | (regval &
122 RES_MASK(AD9834_FREQ_BITS / 2)));
123 st->freq_data[1] = cpu_to_be16(addr | ((regval >>
124 (AD9834_FREQ_BITS / 2)) &
125 RES_MASK(AD9834_FREQ_BITS / 2)));
126
127 return spi_sync(st->spi, &st->freq_msg);
128 }
129
ad9834_write_phase(struct ad9834_state * st,unsigned long addr,unsigned long phase)130 static int ad9834_write_phase(struct ad9834_state *st,
131 unsigned long addr, unsigned long phase)
132 {
133 if (phase >= BIT(AD9834_PHASE_BITS))
134 return -EINVAL;
135 st->data = cpu_to_be16(addr | phase);
136
137 return spi_sync(st->spi, &st->msg);
138 }
139
ad9834_write(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)140 static ssize_t ad9834_write(struct device *dev,
141 struct device_attribute *attr,
142 const char *buf,
143 size_t len)
144 {
145 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
146 struct ad9834_state *st = iio_priv(indio_dev);
147 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
148 int ret;
149 unsigned long val;
150
151 ret = kstrtoul(buf, 10, &val);
152 if (ret)
153 return ret;
154
155 mutex_lock(&st->lock);
156 switch ((u32)this_attr->address) {
157 case AD9834_REG_FREQ0:
158 case AD9834_REG_FREQ1:
159 ret = ad9834_write_frequency(st, this_attr->address, val);
160 break;
161 case AD9834_REG_PHASE0:
162 case AD9834_REG_PHASE1:
163 ret = ad9834_write_phase(st, this_attr->address, val);
164 break;
165 case AD9834_OPBITEN:
166 if (st->control & AD9834_MODE) {
167 ret = -EINVAL; /* AD9843 reserved mode */
168 break;
169 }
170
171 if (val)
172 st->control |= AD9834_OPBITEN;
173 else
174 st->control &= ~AD9834_OPBITEN;
175
176 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
177 ret = spi_sync(st->spi, &st->msg);
178 break;
179 case AD9834_PIN_SW:
180 if (val)
181 st->control |= AD9834_PIN_SW;
182 else
183 st->control &= ~AD9834_PIN_SW;
184 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
185 ret = spi_sync(st->spi, &st->msg);
186 break;
187 case AD9834_FSEL:
188 case AD9834_PSEL:
189 if (!val) {
190 st->control &= ~(this_attr->address | AD9834_PIN_SW);
191 } else if (val == 1) {
192 st->control |= this_attr->address;
193 st->control &= ~AD9834_PIN_SW;
194 } else {
195 ret = -EINVAL;
196 break;
197 }
198 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
199 ret = spi_sync(st->spi, &st->msg);
200 break;
201 case AD9834_RESET:
202 if (val)
203 st->control &= ~AD9834_RESET;
204 else
205 st->control |= AD9834_RESET;
206
207 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
208 ret = spi_sync(st->spi, &st->msg);
209 break;
210 default:
211 ret = -ENODEV;
212 }
213 mutex_unlock(&st->lock);
214
215 return ret ? ret : len;
216 }
217
ad9834_store_wavetype(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)218 static ssize_t ad9834_store_wavetype(struct device *dev,
219 struct device_attribute *attr,
220 const char *buf,
221 size_t len)
222 {
223 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
224 struct ad9834_state *st = iio_priv(indio_dev);
225 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
226 int ret = 0;
227 bool is_ad9833_7 = (st->devid == ID_AD9833) || (st->devid == ID_AD9837);
228
229 mutex_lock(&st->lock);
230
231 switch ((u32)this_attr->address) {
232 case 0:
233 if (sysfs_streq(buf, "sine")) {
234 st->control &= ~AD9834_MODE;
235 if (is_ad9833_7)
236 st->control &= ~AD9834_OPBITEN;
237 } else if (sysfs_streq(buf, "triangle")) {
238 if (is_ad9833_7) {
239 st->control &= ~AD9834_OPBITEN;
240 st->control |= AD9834_MODE;
241 } else if (st->control & AD9834_OPBITEN) {
242 ret = -EINVAL; /* AD9843 reserved mode */
243 } else {
244 st->control |= AD9834_MODE;
245 }
246 } else if (is_ad9833_7 && sysfs_streq(buf, "square")) {
247 st->control &= ~AD9834_MODE;
248 st->control |= AD9834_OPBITEN;
249 } else {
250 ret = -EINVAL;
251 }
252
253 break;
254 case 1:
255 if (sysfs_streq(buf, "square") &&
256 !(st->control & AD9834_MODE)) {
257 st->control &= ~AD9834_MODE;
258 st->control |= AD9834_OPBITEN;
259 } else {
260 ret = -EINVAL;
261 }
262 break;
263 default:
264 ret = -EINVAL;
265 break;
266 }
267
268 if (!ret) {
269 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
270 ret = spi_sync(st->spi, &st->msg);
271 }
272 mutex_unlock(&st->lock);
273
274 return ret ? ret : len;
275 }
276
277 static
ad9834_show_out0_wavetype_available(struct device * dev,struct device_attribute * attr,char * buf)278 ssize_t ad9834_show_out0_wavetype_available(struct device *dev,
279 struct device_attribute *attr,
280 char *buf)
281 {
282 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
283 struct ad9834_state *st = iio_priv(indio_dev);
284
285 if (st->devid == ID_AD9833 || st->devid == ID_AD9837)
286 return sysfs_emit(buf, "sine triangle square\n");
287 if (st->control & AD9834_OPBITEN)
288 return sysfs_emit(buf, "sine\n");
289 return sysfs_emit(buf, "sine triangle\n");
290 }
291
292 static IIO_DEVICE_ATTR(out_altvoltage0_out0_wavetype_available, 0444,
293 ad9834_show_out0_wavetype_available, NULL, 0);
294
295 static
ad9834_show_out1_wavetype_available(struct device * dev,struct device_attribute * attr,char * buf)296 ssize_t ad9834_show_out1_wavetype_available(struct device *dev,
297 struct device_attribute *attr,
298 char *buf)
299 {
300 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
301 struct ad9834_state *st = iio_priv(indio_dev);
302
303 if (st->control & AD9834_MODE)
304 return sysfs_emit(buf, "\n");
305 return sysfs_emit(buf, "square\n");
306 }
307
308 static IIO_DEVICE_ATTR(out_altvoltage0_out1_wavetype_available, 0444,
309 ad9834_show_out1_wavetype_available, NULL, 0);
310
311 /*
312 * see dds.h for further information
313 */
314
315 static IIO_DEV_ATTR_FREQ(0, 0, 0200, NULL, ad9834_write, AD9834_REG_FREQ0);
316 static IIO_DEV_ATTR_FREQ(0, 1, 0200, NULL, ad9834_write, AD9834_REG_FREQ1);
317 static IIO_DEV_ATTR_FREQSYMBOL(0, 0200, NULL, ad9834_write, AD9834_FSEL);
318 static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
319
320 static IIO_DEV_ATTR_PHASE(0, 0, 0200, NULL, ad9834_write, AD9834_REG_PHASE0);
321 static IIO_DEV_ATTR_PHASE(0, 1, 0200, NULL, ad9834_write, AD9834_REG_PHASE1);
322 static IIO_DEV_ATTR_PHASESYMBOL(0, 0200, NULL, ad9834_write, AD9834_PSEL);
323 static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
324
325 static IIO_DEV_ATTR_PINCONTROL_EN(0, 0200, NULL, ad9834_write, AD9834_PIN_SW);
326 static IIO_DEV_ATTR_OUT_ENABLE(0, 0200, NULL, ad9834_write, AD9834_RESET);
327 static IIO_DEV_ATTR_OUTY_ENABLE(0, 1, 0200, NULL, ad9834_write, AD9834_OPBITEN);
328 static IIO_DEV_ATTR_OUT_WAVETYPE(0, 0, ad9834_store_wavetype, 0);
329 static IIO_DEV_ATTR_OUT_WAVETYPE(0, 1, ad9834_store_wavetype, 1);
330
331 static struct attribute *ad9834_attributes[] = {
332 &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
333 &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
334 &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
335 &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
336 &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
337 &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
338 &iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr,
339 &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
340 &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
341 &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
342 &iio_dev_attr_out_altvoltage0_out1_enable.dev_attr.attr,
343 &iio_dev_attr_out_altvoltage0_out0_wavetype.dev_attr.attr,
344 &iio_dev_attr_out_altvoltage0_out1_wavetype.dev_attr.attr,
345 &iio_dev_attr_out_altvoltage0_out0_wavetype_available.dev_attr.attr,
346 &iio_dev_attr_out_altvoltage0_out1_wavetype_available.dev_attr.attr,
347 NULL,
348 };
349
350 static struct attribute *ad9833_attributes[] = {
351 &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
352 &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
353 &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
354 &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
355 &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
356 &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
357 &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
358 &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
359 &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
360 &iio_dev_attr_out_altvoltage0_out0_wavetype.dev_attr.attr,
361 &iio_dev_attr_out_altvoltage0_out0_wavetype_available.dev_attr.attr,
362 NULL,
363 };
364
365 static const struct attribute_group ad9834_attribute_group = {
366 .attrs = ad9834_attributes,
367 };
368
369 static const struct attribute_group ad9833_attribute_group = {
370 .attrs = ad9833_attributes,
371 };
372
373 static const struct iio_info ad9834_info = {
374 .attrs = &ad9834_attribute_group,
375 };
376
377 static const struct iio_info ad9833_info = {
378 .attrs = &ad9833_attribute_group,
379 };
380
ad9834_probe(struct spi_device * spi)381 static int ad9834_probe(struct spi_device *spi)
382 {
383 struct ad9834_state *st;
384 struct iio_dev *indio_dev;
385 int ret;
386
387 ret = devm_regulator_get_enable(&spi->dev, "avdd");
388 if (ret)
389 return dev_err_probe(&spi->dev, ret, "Failed to enable specified AVDD supply\n");
390
391 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
392 if (!indio_dev) {
393 ret = -ENOMEM;
394 return ret;
395 }
396 st = iio_priv(indio_dev);
397 mutex_init(&st->lock);
398 st->mclk = devm_clk_get_enabled(&spi->dev, NULL);
399 if (IS_ERR(st->mclk)) {
400 dev_err(&spi->dev, "Failed to enable master clock\n");
401 return PTR_ERR(st->mclk);
402 }
403
404 st->spi = spi;
405 st->devid = spi_get_device_id(spi)->driver_data;
406 indio_dev->name = spi_get_device_id(spi)->name;
407 switch (st->devid) {
408 case ID_AD9833:
409 case ID_AD9837:
410 indio_dev->info = &ad9833_info;
411 break;
412 default:
413 indio_dev->info = &ad9834_info;
414 break;
415 }
416 indio_dev->modes = INDIO_DIRECT_MODE;
417
418 /* Setup default messages */
419
420 st->xfer.tx_buf = &st->data;
421 st->xfer.len = 2;
422
423 spi_message_init(&st->msg);
424 spi_message_add_tail(&st->xfer, &st->msg);
425
426 st->freq_xfer[0].tx_buf = &st->freq_data[0];
427 st->freq_xfer[0].len = 2;
428 st->freq_xfer[0].cs_change = 1;
429 st->freq_xfer[1].tx_buf = &st->freq_data[1];
430 st->freq_xfer[1].len = 2;
431
432 spi_message_init(&st->freq_msg);
433 spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
434 spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
435
436 st->control = AD9834_B28 | AD9834_RESET;
437 st->control |= AD9834_DIV2;
438
439 if (st->devid == ID_AD9834)
440 st->control |= AD9834_SIGN_PIB;
441
442 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
443 ret = spi_sync(st->spi, &st->msg);
444 if (ret) {
445 dev_err(&spi->dev, "device init failed\n");
446 return ret;
447 }
448
449 ret = ad9834_write_frequency(st, AD9834_REG_FREQ0, 1000000);
450 if (ret)
451 return ret;
452
453 ret = ad9834_write_frequency(st, AD9834_REG_FREQ1, 5000000);
454 if (ret)
455 return ret;
456
457 ret = ad9834_write_phase(st, AD9834_REG_PHASE0, 512);
458 if (ret)
459 return ret;
460
461 ret = ad9834_write_phase(st, AD9834_REG_PHASE1, 1024);
462 if (ret)
463 return ret;
464
465 return devm_iio_device_register(&spi->dev, indio_dev);
466 }
467
468 static const struct spi_device_id ad9834_id[] = {
469 {"ad9833", ID_AD9833},
470 {"ad9834", ID_AD9834},
471 {"ad9837", ID_AD9837},
472 {"ad9838", ID_AD9838},
473 { }
474 };
475 MODULE_DEVICE_TABLE(spi, ad9834_id);
476
477 static const struct of_device_id ad9834_of_match[] = {
478 {.compatible = "adi,ad9833"},
479 {.compatible = "adi,ad9834"},
480 {.compatible = "adi,ad9837"},
481 {.compatible = "adi,ad9838"},
482 { }
483 };
484
485 MODULE_DEVICE_TABLE(of, ad9834_of_match);
486
487 static struct spi_driver ad9834_driver = {
488 .driver = {
489 .name = "ad9834",
490 .of_match_table = ad9834_of_match
491 },
492 .probe = ad9834_probe,
493 .id_table = ad9834_id,
494 };
495 module_spi_driver(ad9834_driver);
496
497 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
498 MODULE_DESCRIPTION("Analog Devices AD9833/AD9834/AD9837/AD9838 DDS");
499 MODULE_LICENSE("GPL v2");
500